SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can be used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for the SATA controller, the below sequence is expected.
1. Assert the SATA controlle
This patch series updates the ceva driver to add support for Xilinx GT phy.
This also updates the documentation with the device tree binding required
for working with Xilinx GT phy.
---
Changes in V2:
- Added backward compatibility with the older sequence of the CEVA controller.
- Update dt-bind
charlcd_write() is invoked as a VFS->write() callback and as such it is
always invoked from preemptible context and may sleep.
charlcd_puts() is invoked from register/unregister callback which is
preemtible. The reboot notifier callback is also invoked from
preemptible context.
Therefore there is
From: Miklos Szeredi
[ Upstream commit f2b00be488730522d0fb7a8a5de663febdcefe0a ]
If a capability is stored on disk in v2 format cap_inode_getsecurity() will
currently return in v2 format unconditionally.
This is wrong: v2 cap should be equivalent to a v3 cap with zero rootid,
and so the same c
From: Hans de Goede
[ Upstream commit 67fbe02a5cebc3c653610f12e3c0424e58450153 ]
Recently userspace has started making more use of SW_TABLET_MODE
(when an input-dev reports this).
Specifically recent GNOME3 versions will:
1. When SW_TABLET_MODE is reported and is reporting 0:
1.1 Disable acce
From: Benjamin Valentin
[ Upstream commit 9bbd77d5bbc9aff8cb74d805c31751f5f0691ba8 ]
There is a fork of this driver on GitHub [0] that has been updated
with new device IDs.
Merge those into the mainline driver, so the out-of-tree fork is not
needed for users of those devices anymore.
[0] https
On Mon, Feb 08, 2021 at 11:12:52PM +0900, Hector Martin wrote:
> On 08/02/2021 21.40, Arnd Bergmann wrote:
> > On Mon, Feb 8, 2021 at 1:13 PM Krzysztof Kozlowski wrote:
> > >
> > > On Mon, Feb 08, 2021 at 08:56:53PM +0900, Hector Martin 'marcan' wrote:
> > > > On 08/02/2021 20.04, Krzysztof Kozlo
From: Masahiro Yamada
[ Upstream commit f4c3b83b75b91c5059726cb91e3165cc01764ce7 ]
With commit 1e860048c53e ("gcc-plugins: simplify GCC plugin-dev
capability test") applied, this hunk can be way simplified because
now scripts/gcc-plugins/Kconfig only checks plugin-version.h
Signed-off-by: Masah
From: Johan Jonker
[ Upstream commit 94a5400f8b966c91c49991bae41c2ef911b935ac ]
A test with the command below gives this error:
/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: video-codec@ff66:
'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+'
The rkvdec driver gets it
From: Miklos Szeredi
[ Upstream commit 554677b97257b0b69378bd74e521edb7e94769ff ]
The vfs_getxattr() in ovl_xattr_set() is used to check whether an xattr
exist on a lower layer file that is to be removed. If the xattr does not
exist, then no need to copy up the file.
This call of vfs_getxattr(
From: Dafna Hirschfeld
[ Upstream commit 31f190e0ccac8b75d33fdc95a797c526cf9b149e ]
Each entry in the array is a 20 bits value composed of 16 bits unsigned
integer and 4 bits fractional part. So the type should change to __u32.
In addition add a documentation of how the measurements are done.
S
From: Robin Murphy
[ Upstream commit 74532de460ec664e5a725507d1b59aa9e4d40776 ]
NanoPi R2S is headless, so rightly does not enable any of the display
interface hardware, which currently provokes an obnoxious error in the
boot log from the fake DRM device failing to find anything to bind to.
It p
From: Tony Lindgren
[ Upstream commit 7078a5ba7a58e5db07583b176f8a03e0b8714731 ]
We have rst_map_012 used for various accelerators like dsp, ipu and iva.
For these use cases, we have rstctrl bit 2 control the subsystem module
reset, and have and bits 0 and 1 control the accelerator specific
feat
From: Amir Goldstein
[ Upstream commit 03fedf93593c82538b18476d8c4f0e8f8435ea70 ]
When inode has no listxattr op of its own (e.g. squashfs) vfs_listxattr
calls the LSM inode_listsecurity hooks to list the xattrs that LSMs will
intercept in inode_getxattr hooks.
When selinux LSM is installed but
From: Dafna Hirschfeld
[ Upstream commit a76f8dc8be471028540df24749e99a3ec0ac7c94 ]
hist_bins is an array of type __u32. Each entry represent
a 20 bit fixed point value as documented inline.
The cast to u8 when setting the values is wrong. Remove it.
Signed-off-by: Dafna Hirschfeld
Reviewed-by
From: AngeloGioacchino Del Regno
[ Upstream commit 2dce6db70c77bbe639f5cd9cc796fb8f2694a7d0 ]
The Goodix GT9286 is a capacitive touch sensor IC based on GT1x.
This chip can be found on a number of smartphones, including the
F(x)tec Pro 1 and the Elephone U.
This has been tested on F(x)Tec Pro1
From: Bjorn Andersson
[ Upstream commit 93f2a11580a9732c1d90f9e01a7e9facc825658f ]
The GCC_LPASS_Q6_AXI_CLK and GCC_LPASS_SWAY_CLK clocks may not be
touched on a typical UEFI based SDM845 device, but when the kernel is
built with CONFIG_SDM_LPASSCC_845 this happens, unless they are marked
as pro
From: Tony Lindgren
[ Upstream commit 06862d789ddde8a99c1e579e934ca17c15a84755 ]
We get suspcious RCU usage splats with cpuidle in several places in
omap_enter_idle_coupled() with the kernel debug options enabled:
RCU used illegally from extended quiescent state!
...
(_raw_spin_lock_irqsave)
(o
From: Marc Zyngier
[ Upstream commit 43f20b1c6140896916f4e91aacc166830a7ba849 ]
It recently became apparent that the lack of a 'device_type = "pci"'
in the PCIe root complex node for rk3399 is a violation of the PCI
binding, as documented in IEEE Std 1275-1994. Changes to the kernel's
parsing of
On Fri, 22 Jan 2021, Thomas Bogendoerfer wrote:
> I couldn't find any user of the dubious vpe_getcwd so far. So remove it and
> get rid of another set_fs(KERNEL_DS).
IIRC it served as the path for the SP-side program to load in the AP/SP
model. Or something like that. There may have been an a
On Mon, Feb 08, 2021 at 07:24:59AM -0800, kan.li...@linux.intel.com wrote:
> diff --git a/arch/x86/include/asm/processor.h
> b/arch/x86/include/asm/processor.h
> index c20a52b..1f25ac9 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -139,6 +139,16 @@ s
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
Reviewed-by: Marco Felsch
Reviewed-by: Fabio Estevam
---
v4
On Fri 2021-02-05 14:50:56, Andy Shevchenko wrote:
> On Fri, Feb 5, 2021 at 1:35 PM Richard Fitzgerald
> wrote:
> > On 04/02/2021 16:35, Petr Mladek wrote:
> > > On Wed 2021-02-03 21:45:55, Andy Shevchenko wrote:
> > >> On Wed, Feb 03, 2021 at 04:50:07PM +, Richard Fitzgerald wrote:
> > >> Thi
On Mon, Feb 08, 2021 at 04:27:36PM +0100, Andrew Lunn wrote:
> On Mon, Feb 08, 2021 at 05:03:22PM +0300, Serge Semin wrote:
> > It has been noticed that RTL8211E PHY stops detecting and reporting events
> > when EEE is successfully advertised and RXC stopping in LPI is enabled.
> > The freeze happe
On 08/02/21 18:31, Sean Christopherson wrote:
On Mon, Feb 08, 2021, Paolo Bonzini wrote:
On 07/02/21 16:42, Jing Liu wrote:
In KVM, "guest_fpu" serves for any guest task working on this vcpu
during vmexit and vmenter. We provide a pre-allocated guest_fpu space
and entire "guest_fpu.state_mask"
On 08/02/2021 15:18, Andy Shevchenko wrote:
On Mon, Feb 08, 2021 at 02:01:52PM +, Richard Fitzgerald wrote:
The existing code attempted to handle numbers by doing a strto[u]l(),
ignoring the field width, and then repeatedly dividing to extract the
field out of the full converted value. If th
On 08.02.2021 18:50, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-01-18 08:14:41)
>> This was omitted when first adding the clocks for these SoCs.
>>
> I believe they were omitted because the system crashed if they were
> touched. Is that still the case?
No, rpmcc XO seems to work fine, no
Quoting Bjorn Andersson (2021-01-20 14:37:41)
> Add clocks provides by RPMH in the Qualcomm SC8180x platform.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
Quoting Bjorn Andersson (2021-01-20 14:37:40)
> Add Qualcomm SC8180x to the list of compatibles for the RPMHCC binding.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
Quoting Taniya Das (2021-01-19 23:47:51)
> There are intermittent GDSC power-up failures observed for titan top
> gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
> enabled from probe.
>
> Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of
> clk o
On Fri, Feb 05, 2021 at 04:39:13PM +0100, Andrey Konovalov wrote:
> Export mte_enable_kernel_sync() and mte_set_report_once() to fix:
>
> ERROR: modpost: "mte_enable_kernel_sync" [lib/test_kasan.ko] undefined!
> ERROR: modpost: "mte_set_report_once" [lib/test_kasan.ko] undefined!
Please put this
On Mon, Feb 08, 2021, Yanan Wang wrote:
> Add a macro to get string of the backing source memory type, so that
> application can add choices for source types in the help() function,
> and users can specify which type to use for testing.
>
> Signed-off-by: Yanan Wang
> ---
> tools/testing/selftes
Quoting Srinivas Kandagatla (2021-01-19 03:38:51)
> For some reason global GFM_MASK ended up with bit 1 instead of bit 0.
> Remove the global GFM_MASK and reuse mux_mask field.
>
> Fixes: a2d8f507803e ("clk: qcom: Add support to LPASS AUDIO_CC Glitch Free
> Mux clocks")
> Signed-off-by: Srinivas
Quoting Konrad Dybcio (2021-01-18 08:14:41)
> This was omitted when first adding the clocks for these SoCs.
>
I believe they were omitted because the system crashed if they were
touched. Is that still the case?
> Fixes: b4297844995 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
> Signe
On Sun, Feb 07, 2021 at 11:13:52AM -0500, Sasha Levin wrote:
> + (u8)(LINUX_VERSION_MAJOR), (u8)(LINUX_VERSION_PATCHLEVEL),
> + (u16)(LINUX_VERSION_SUBLEVEL));
No need for the casts and braces.
Otherwise this looks good, but please also kill off KERNEL_VERSION
and LINUX_KE
On 08/02/21 16:29, Vincent Guittot wrote:
> On Fri, 5 Feb 2021 at 21:07, Valentin Schneider
> wrote:
>>
>> Perhaps I can still keep 5/8 with something like
>>
>> if (!rq->misfit_task_load)
>> return false;
>>
>> do {
>> if (capacity_greater(group->sgc->max_capacity, rq->cpu
On Mon 08 Feb 11:21 CST 2021, Kalle Valo wrote:
> Amit Pundir writes:
>
> > Hi Kalle,
> >
> > On Mon, 7 Dec 2020 at 22:25, Kalle Valo wrote:
> >>
> >> This is firmware version specific, right? There's also enum
> >> ath10k_fw_features which is embedded within firmware-N.bin, we could add
> >> a
On Mon, 8 Feb 2021 07:06:58 -0600 Seth Forshee
wrote:
> On Sun, Feb 07, 2021 at 05:48:31PM +0300, Kirill A. Shutemov wrote:
> > On Fri, Feb 05, 2021 at 05:06:20PM -0600, Seth Forshee wrote:
> > > This feature requires ino_t be 64-bits, which is true for every
> > > 64-bit architecture but s390,
Le 26/01/2021 à 11:21, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of January 26, 2021 12:48 am:
syscall_64.c will be reused almost as is for PPC32.
Rename it syscall.c
Could you rename it to interrupt.c instead? A system call is an
interrupt, and the file now also h
Quoting Manivannan Sadhasivam (2021-01-17 20:11:56)
> Add a driver for the SDX55 APCS clock controller. It is part of the APCS
> hardware block, which among other things implements also a combined mux
> and half integer divider functionality. The APCS clock controller has 3
> parent clocks:
>
> 1.
On Mon, Feb 08, 2021, Andy Lutomirski wrote:
> On Mon, Feb 8, 2021 at 9:11 AM Sean Christopherson wrote:
> >
> > On Sun, Feb 07, 2021, Andy Lutomirski wrote:
> > >
>
> > > How much of the register state is revealed to the VMM when we do a
> > > TDVMCALL?
> > > Presumably we should fully sanitize
Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> Changes in v2:
>
> * Modified the max_register value as per the SDX55 IPC offset in mailbox
> driver.
>
> Manivannan Sadhasivam (5):
> dt-bindings: mailbox: Add binding for SDX55 APCS
> mailbox: qcom: Add support for SDX55 APCS IPC
I th
Quoting Manivannan Sadhasivam (2021-01-17 20:11:54)
> Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX55.
>
> Signed-off-by: Manivannan Sadhasivam
> ---
Applied to clk-next
Le 26/01/2021 à 11:18, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of January 26, 2021 12:48 am:
Save r3 in regs->orig_r3 in system_call_exception()
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_64.S | 1 -
arch/powerpc/kernel/syscall.c | 2 ++
2
Quoting Manivannan Sadhasivam (2021-01-17 20:11:55)
> Add support for PLL found in Qualcomm SDX55 platforms which is used to
> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
> frequency clock to the CPU above 1GHz as compared to the other sources
> like GPLL0.
>
> In this
On Mon, Feb 08, 2021 at 09:28:24AM -0800, Darrick J. Wong wrote:
> On Mon, Feb 09, 2021 at 09:11:40AM -0800, Paul E. McKenney wrote:
> > On Mon, Feb 08, 2021 at 10:44:58AM -0500, Brian Foster wrote:
> > > On Mon, Feb 08, 2021 at 06:57:24AM -0800, Paul E. McKenney wrote:
> > > > On Mon, Feb 08, 2021
On Mon, Feb 08, 2021 at 08:42:36PM +0530, Calvin Johnson wrote:
> +int fwnode_mdiobus_register_phy(struct mii_bus *bus,
> + struct fwnode_handle *child, u32 addr)
> +{
> + struct mii_timestamper *mii_ts;
If you initialise this to NULL...
> + struct phy_device *
On Sat, 6 Feb 2021 04:19:59 +0530 Geetha sowjanya wrote:
> The current admin function (AF) driver and the netdev driver supports
> OcteonTx2 silicon variants. The same OcteonTx2's
> Resource Virtualization Unit (RVU) is carried forward to the next-gen
> silicon ie OcteonTx3, with some changes and f
On 2/8/21 7:00 AM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.4.97 release.
> There are 65 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should
Em Mon, 08 Feb 2021 13:57:56 -0300
Ezequiel Garcia escreveu:
> On Mon, 2021-02-08 at 18:46 +0200, Sakari Ailus wrote:
> > Hi Ezequiel,
> >
> > Thanks for addressing this.
> >
> > On Mon, Feb 08, 2021 at 01:42:21PM -0300, Ezequiel Garcia wrote:
> > > Hi Stephen,
> > >
> > > On Mon, 2021-02-08
> +int follow_invalidate_pte(struct mm_struct *mm, unsigned long address,
> + struct mmu_notifier_range *range, pte_t **ptepp,
> pmd_t **pmdpp,
> + spinlock_t **ptlp);
This adds a very pointless overy long line.
> +/**
> + * follow_pte - look up PTE at
Do you want 20% Daily Profit ?
You can invest in Bitcoin now
Kindly give me your response
On Mon, Feb 8, 2021 at 9:11 AM Sean Christopherson wrote:
>
> On Sun, Feb 07, 2021, Andy Lutomirski wrote:
> >
> > How much of the register state is revealed to the VMM when we do a TDVMCALL?
> > Presumably we should fully sanitize all register state that shows up in
> > cleartext on the other en
On Mon, Feb 09, 2021 at 09:11:40AM -0800, Paul E. McKenney wrote:
> On Mon, Feb 08, 2021 at 10:44:58AM -0500, Brian Foster wrote:
> > On Mon, Feb 08, 2021 at 06:57:24AM -0800, Paul E. McKenney wrote:
> > > On Mon, Feb 08, 2021 at 09:07:24AM -0500, Brian Foster wrote:
> > > > On Fri, Feb 05, 2021 at
On Sat, Feb 06, 2021 at 11:08:27PM +0800, Leo Yan wrote:
> To get the changes in the commit:
>
> "coresight: etm-perf: Clarify comment on perf options".
>
> Signed-off-by: Leo Yan
> Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
> ---
> tools/include/linux/coresight-pmu.h | 17
On Mon, Feb 08, 2021 at 06:14:38PM +0800, Yafang Shao wrote:
> It is strange to combine "pr_err" with "INFO", so let's remove the
> prefix completely.
So is this the right thing to do? Should it be pr_info() instead?
Many of these messages do not appear to be error messages, but
rather informatio
On Mon, Feb 08, 2021, Paolo Bonzini wrote:
> On 07/02/21 16:42, Jing Liu wrote:
> > |In KVM, "guest_fpu" serves for any guest task working on this vcpu
> > during vmexit and vmenter. We provide a pre-allocated guest_fpu space
> > and entire "guest_fpu.state_mask" to avoid each dynamic features
> >
On Fri, 5 Feb 2021 at 13:58, Steven Price wrote:
>
> The VMM may not wish to have it's own mapping of guest memory mapped
> with PROT_MTE because this causes problems if the VMM has tag checking
> enabled (the guest controls the tags in physical RAM and it's unlikely
> the tags are correct for the
On Mon, Feb 08, 2021 at 11:27:30AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Feb 05, 2021 at 05:39:34AM +0900, Hector Martin wrote:
> > Amusingly, this wasn't yet documented, even though this vendor prefix
> > has been used since time immemorial on PPC.
> >
> > Signed-off-by: Hector Martin
> >
On 2/8/21 7:00 AM, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.257 release.
> There are 43 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should
On Mon, Feb 08, 2021 at 08:17:34PM +0300, Alexey Dobriyan wrote:
> On Mon, Feb 08, 2021 at 03:22:44PM +, Matthew Wilcox wrote:
> > On Mon, Feb 08, 2021 at 03:14:28PM +, Kalesh Singh wrote:
> > > - seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\n",
> > > + seq_printf(m, "pos:\t%lli\nfla
On Mon, Feb 08, 2021, Dave Hansen wrote:
> On 2/8/21 8:16 AM, Jing Liu wrote:
> > -#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
> > -
> > static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
> > {
> > struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
> > @@ -4494,7 +4492,8
Le 05/07/2018 à 10:53, Christophe Leroy a écrit :
The generic implementation of strlen() reads strings byte per byte.
This patch implements strlen() in assembly based on a read of entire
words, in the same spirit as what some other arches and glibc do.
strlen() selftest on an provid
On Mon, Feb 08, 2021 at 09:14:53AM -0800, Guenter Roeck wrote:
> On Sun, Feb 07, 2021 at 09:22:44AM +0100, Greg Kroah-Hartman wrote:
> [ ... ]
> > > There are lots (35) of "KERNEL_VERSION(4, 5, 0)" in chromeos-4.4.
> > > That should not matter with the clamped LINUX_VERSION_CODE, but
> > > I'd pref
Amit Pundir writes:
> Hi Kalle,
>
> On Mon, 7 Dec 2020 at 22:25, Kalle Valo wrote:
>>
>> This is firmware version specific, right? There's also enum
>> ath10k_fw_features which is embedded within firmware-N.bin, we could add
>> a new flag there. But that means that a correct firmware-N.bin is ne
On Mon, Feb 08, 2021 at 03:22:44PM +, Matthew Wilcox wrote:
> On Mon, Feb 08, 2021 at 03:14:28PM +, Kalesh Singh wrote:
> > - seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\n",
> > + seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\ninode_no:\t%lu\n",
>
> You changed it everywh
On Sat, 6 Feb 2021 12:13:43 +0100, Krzysztof Kozlowski wrote:
> The driver can match only via the DT table so the table should be always
> used and the of_match_ptr does not have any sense (this also allows ACPI
> matching via PRP0001, even though it might be not relevant here). This
> fixes compi
On Sat, 6 Feb 2021 12:17:15 +0100, Krzysztof Kozlowski wrote:
> Correct kerneldoc to fix W=1 warnings:
>
> drivers/memory/samsung/exynos5422-dmc.c:290: warning:
> expecting prototype for find_target_freq_id(). Prototype was for
> find_target_freq_idx() instead
> drivers/memory/sam
On Sun, 7 Feb 2021 16:02:50 +0800, Jiapeng Chong wrote:
> Fix the following coccicheck warning:
>
> drivers/memory/tegra/tegra186-emc.c:158:0-23: WARNING:
> tegra186_emc_debug_max_rate_fops should be defined with
> DEFINE_DEBUGFS_ATTRIBUTE.
>
> drivers/memory/tegra/tegra186-emc.c:128:0-23: WARNIN
On Fri, Feb 05, 2021 at 06:58:52PM +0100, Christoph Hellwig wrote:
> On Wed, Feb 03, 2021 at 02:36:38PM -0500, Konrad Rzeszutek Wilk wrote:
> > > So what? If you guys want to provide a new capability you'll have to do
> > > work. And designing a new protocol based around the fact that the
> > > h
On Sun, Feb 07, 2021 at 09:22:44AM +0100, Greg Kroah-Hartman wrote:
[ ... ]
> > There are lots (35) of "KERNEL_VERSION(4, 5, 0)" in chromeos-4.4.
> > That should not matter with the clamped LINUX_VERSION_CODE, but
> > I'd prefer to clamp KERNEL_VERSION as well just to be sure. On
> > top of that, s
On Mon, Feb 08, 2021 at 10:44:58AM -0500, Brian Foster wrote:
> On Mon, Feb 08, 2021 at 06:57:24AM -0800, Paul E. McKenney wrote:
> > On Mon, Feb 08, 2021 at 09:07:24AM -0500, Brian Foster wrote:
> > > On Fri, Feb 05, 2021 at 09:12:40AM -0800, Paul E. McKenney wrote:
> > > > On Fri, Feb 05, 2021 at
On Sat, 6 Feb 2021 14:36:14 +0100, Krzysztof Kozlowski wrote:
> Include headers to fix W=1 build warnings:
>
> arch/arm/mach-s3c/irq-s3c24xx.c:389:5: warning:
> no previous prototype for ‘s3c24xx_set_fiq’ [-Wmissing-prototypes]
> arch/arm/mach-s3c/irq-s3c24xx.c:683:13: warning:
> no pr
On Sun, Feb 07, 2021, Andy Lutomirski wrote:
>
> > On Feb 7, 2021, at 2:31 PM, Dave Hansen wrote:
> >
> > On 2/7/21 12:29 PM, Kirill A. Shutemov wrote:
> >>> Couldn't you just have one big helper that takes *all* the registers
> >>> that get used in any TDVMCALL and sets all the rcx bits? The
From: Ioana Ciornei
Add some new MC firmware commands that can be received through the
userspace ioctl interface - *get_max_frame_length and *_get_counter.
Signed-off-by: Ioana Ciornei
---
drivers/bus/fsl-mc/fsl-mc-uapi.c | 50
1 file changed, 50 insertions(+)
From: Ioana Ciornei
A new object type was recently added in MC. This has to be added in the
fsl-mc bus device type list so that it can be properly listed.
Signed-off-by: Ioana Ciornei
---
drivers/bus/fsl-mc/fsl-mc-bus.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/bus/fsl
On 2/6/21 12:46 PM, Moritz Fischer wrote:
> Russ,
>
> On Fri, Feb 05, 2021 at 10:25:21AM -0800, Russ Weight wrote:
>> Port enable is not complete until ACK = 0. Change
>> __afu_port_enable() to guarantee that the enable process
>> is complete by polling for ACK == 0.
>>
>> Reviewed-by: Tom Rix
On Sat, 6 Feb 2021 14:36:14 +0100, Krzysztof Kozlowski wrote:
> Include headers to fix W=1 build warnings:
>
> arch/arm/mach-s3c/irq-s3c24xx.c:389:5: warning:
> no previous prototype for ‘s3c24xx_set_fiq’ [-Wmissing-prototypes]
> arch/arm/mach-s3c/irq-s3c24xx.c:683:13: warning:
> no pr
From: Dan Carpenter
The "desc" pointer can't possibly be NULL here. If we can't find the
correct "desc" then tt points to the last element of the
fsl_mc_accepted_cmds[] array. Fix this by testing if
"i == FSL_MC_NUM_ACCEPTED_CMDS" instead.
Fixes: 2cf1e703f066 ("bus: fsl-mc: add fsl-mc userspac
> -Original Message-
> From: Rob Herring
> Sent: Monday, February 8, 2021 10:55 AM
> To: Leo Li
> Cc: linux-arm-ker...@lists.infradead.org; Oleksij Rempel privat.de>; Rob Herring ; Krzysztof Kozlowski
> ; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Shawn Guo
> Subjec
On Mon, Feb 8, 2021 at 7:20 AM Steen Hegelund
wrote:
>
> Hi Rob,
>
> On Fri, 2021-02-05 at 16:35 -0600, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On Wed, Jan 20, 2021 at 09:19:21AM +0100, Steen Hegelund wrote:
> >
From: Ioana Ciornei
This patch set adds a fix on the userspace support of the fsl-mc bus.
Other than that, a missing device type is added and some other commands
to the list of the accepted ones.
Dan Carpenter (1):
bus: fsl-mc: Fix test for end of loop
Ioana Ciornei (2):
bus: fsl-mc: add th
Does this patch fix an issue raised previously? Or should they be used together?
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2466541.html
IMHO using this patch alone won’t fix the issue --
Best,
- Tong
> On Feb 8, 2021, at 5:41 AM, Gerd Hoffmann wrote:
>
> Specifically do not
Also print out the phandle ID on error message, as a debug aid.
Signed-off-by: Enrico Weigelt, metux IT consult
---
drivers/of/base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 161a23631472..8a348f0d3c5e 100644
--- a/driver
On 2/8/21 4:48 PM, Johan Hovold wrote:
The to_usb_serial_port() macro is implemented using container_of() so
there's no need to check for NULL.
Note that neither bus match() or probe() is ever called with a NULL
struct device pointer so the checks weren't just misplaced.
Signed-off-by: Johan Ho
On Mon, Feb 08, 2021 at 08:46:23AM -0800, Sean Christopherson wrote:
> On Mon, Feb 08, 2021, Peter Zijlstra wrote:
> > On Mon, Feb 08, 2021 at 08:23:01AM -0800, Andi Kleen wrote:
> > > > > +#ifdef CONFIG_INTEL_TDX_GUEST
> > > > > +DEFINE_IDTENTRY(exc_virtualization_exception)
> > > > > +{
> > > > >
On Sat, 6 Feb 2021 19:18:16 -0800 menglong8.d...@gmail.com wrote:
> From: Menglong Dong
>
> The bit mask for MSG_* seems a little confused here. Replace it
> with BIT() to make it clear to understand.
>
> Changes since v1:
> - use BIT() instead of BIT_MASK()
>
> Signed-off-by: Menglong Dong
Greeting
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to approach you through this media it is because it serves the fastest
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Hello Sebastian,
Thanks for the feedback!
On Thu, 2021-01-28 at 11:33 +0100, Sebastian Andrzej Siewior wrote:
> On 2021-01-28 03:55:06 [-0300], Leonardo Bras wrote:
> > Currently, during flush_smp_call_function_queue():
> > - All items are transversed once, for inverting.
> > - The SYNC items are
On Fri, 22 Jan 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> kgdb fails to build when the FPU support is disabled:
>
> arch/mips/kernel/kgdb.c: In function 'dbg_set_reg':
> arch/mips/kernel/kgdb.c:147:35: error: 'struct thread_struct' has no member
> named 'fpu'
> 147 |memcpy((voi
On Mon, 2021-02-08 at 18:46 +0200, Sakari Ailus wrote:
> Hi Ezequiel,
>
> Thanks for addressing this.
>
> On Mon, Feb 08, 2021 at 01:42:21PM -0300, Ezequiel Garcia wrote:
> > Hi Stephen,
> >
> > On Mon, 2021-02-08 at 23:37 +1100, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > After merging t
MTE provides a mode that asynchronously updates the TFSR_EL1 register
when a tag check exception is detected.
To take advantage of this mode the kernel has to verify the status of
the register at:
1. Context switching
2. Return to user/EL0 (Not required in entry from EL0 since the kernel
did
From: Andrey Konovalov
Asynchronous KASAN mode doesn't guarantee that a tag fault will be
detected immediately and causes tests to fail. Forbid running them
in asynchronous mode.
Signed-off-by: Andrey Konovalov
---
lib/test_kasan.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/te
Architectures supported by KASAN_HW_TAGS can provide a sync or async mode
of execution. On an MTE enabled arm64 hw for example this can be identified
with the synchronous or asynchronous tagging mode of execution.
In synchronous mode, an exception is triggered if a tag check fault occurs.
In asynch
MTE provides an asynchronous mode for detecting tag exceptions. In
particular instead of triggering a fault the arm64 core updates a
register which is checked by the kernel after the asynchronous tag
check fault has occurred.
Add support for MTE asynchronous mode.
The exception handling mechanism
When MTE async mode is enabled TFSR_EL1 contains the accumulative
asynchronous tag check faults for EL1 and EL0.
During the suspend/resume operations the firmware might perform some
operations that could change the state of the register resulting in
a spurious tag check fault report.
Save/restore
On Mon, Feb 8, 2021 at 5:44 PM Bartosz Golaszewski
wrote:
>
> On Fri, Feb 5, 2021 at 2:25 PM Sakari Ailus
> wrote:
> >
> > In certain use cases (where the chip is part of a camera module, and the
> > camera module is wired together with a camera privacy LED), powering on
> > the device during pro
KASAN provides an asynchronous mode of execution.
Add reporting functionality for this mode.
Cc: Dmitry Vyukov
Cc: Andrey Ryabinin
Cc: Alexander Potapenko
Cc: Andrey Konovalov
Reviewed-by: Andrey Konovalov
Signed-off-by: Vincenzo Frascino
Signed-off-by: Andrey Konovalov
---
include/linux/
This patchset implements the asynchronous mode support for ARMv8.5-A
Memory Tagging Extension (MTE), which is a debugging feature that allows
to detect with the help of the architecture the C and C++ programmatic
memory errors like buffer overflow, use-after-free, use-after-return, etc.
MTE is bui
load_unaligned_zeropad() and __get/put_kernel_nofault() functions can
read passed some buffer limits which may include some MTE granule with a
different tag.
When MTE async mode is enable, the load operation crosses the boundaries
and the next granule has a different tag the PE sets the TFSR_EL1.T
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