The following series of patches
- Add support for GPIO subsystem in main and wakeup domains.
- Add voltage regulator device tree nodes and their corresponding pinmux
to support power cycle and voltage switch required for UHS-I modes
- sets respective tags in sdhci0 node to support higher speeds
On 10/03/2021 15:50, Doug Anderson wrote:
Hi,
On Wed, Mar 10, 2021 at 2:37 AM Srinivas Kandagatla
wrote:
On 06/03/2021 00:26, Douglas Anderson wrote:
Sometimes the clients of nvmem just want to get a number out of
nvmem. They don't want to think about exactly how many bytes the nvmem
On Wed, Mar 10, 2021 at 09:44:07AM -0600, Pierre-Louis Bossart wrote:
> On 3/10/21 7:35 AM, Mark Brown wrote:
> > Just change it to a system level check for ACPI, checking for OF would
> > leave problems for board files or any other alternative firmware
> > interfaces.
> did you mean if
Hi,
On Tue, Mar 09, 2021 at 08:55:10AM +, claudiu.bez...@microchip.com wrote:
> Hi Andreas,
>
> On 08.03.2021 21:30, Andreas Schwab wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > One of the changes to the macb driver
Pages containing buffer_heads that are in one of the per-CPU
buffer_head LRU caches will be pinned and thus cannot be migrated.
This can prevent CMA allocations from succeeding, which are often used
on platforms with co-processors (such as a DSP) that can only use
physically contiguous memory. It
Currently, migrate_prep is merely a wrapper of lru_cache_add_all.
There is not much to gain from having additional abstraction.
Use lru_add_drain_all instead of migrate_prep, which would be more
descriptive.
note: migrate_prep_local in compaction.c changed into lru_add_drain
to avoid CPU
LRU pagevec holds refcount of pages until the pagevec are drained.
It could prevent migration since the refcount of the page is greater
than the expection in migration logic. To mitigate the issue,
callers of migrate_pages drains LRU pagevec via migrate_prep or
lru_add_drain_all before
On 3/9/2021 11:23 PM, Alexander Sverdlin wrote:
> Hi!
>
> On 09/03/2021 18:42, Qais Yousef wrote:
I tried on 5.12-rc2 and 5.11 but couldn't reproduce the problem using your
>> I still can't reproduce on 5.12-rc2.
>>
>> I do have CONFIG_ARM_MODULE_PLTS=y. Do you need to do something else
Add a function to set the dynamic queue limit minimum value.
This function is to be used by network drivers which are able to
prove, at least through empirical tests on several environment (with
other applications, heavy context switching, virtualization...), that
they constantly reach better
Abstract: would like to directly set dql.min_limit value inside a
driver to improve BQL performances of a CAN USB driver.
CAN packets have a small PDU: for classical CAN maximum size is
roughly 16 bytes (8 for payload and 8 for arbitration, CRC and
others).
I am writing an CAN driver for an USB
Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).
Signed-off-by: Kishon Vijay Abraham I
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
From: Nicolas Ferre
Arnd, Olof,
Here are some fixes for 5.12. It's not regression vs. previous revision, this
is why I send them early in the cycle.
I based my branch on top of 5.12-rc2 because I noticed that your "master"
branch was pointing to it (and of course the "-dontuse" suffix from
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 207 --
drivers/pci/controller/cadence/pcie-cadence.h |
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 44 +++---
Add binding to specify virtual function (associated with each physical
function) in endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-ep.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git
Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.
Signed-off-by: Kishon Vijay Abraham I
---
Patch series
*) Adds support to add virtual functions to enable endpoint controller
which supports SR-IOV capability
*) Add support in Cadence endpoint driver to configure virtual functions
*) Enable pci_endpoint_test driver to create pci_device for virtual
functions
v1 of the patch series
From: Mickaël Salaün
Being able to easily change root directories enable to ease some
development workflow and can be used as a tool to strengthen
unprivileged security sandboxes. chroot(2) is not an access-control
mechanism per se, but it can be used to limit the absolute view of the
Hi,
The chroot system call is currently limited to be used by processes with
the CAP_SYS_CHROOT capability. This protects against malicious
procesess willing to trick SUID-like binaries. The following patch
allows unprivileged users to safely use chroot(2).
This patch is a follow-up of a
On Wed, Mar 10, 2021 at 05:08:46PM +0100, Greg KH wrote:
> On Sun, Feb 28, 2021 at 08:39:29PM +0200, Mihai Carabas wrote:
> > Hello,
> >
> > Any feedback on this last series?
>
> Other than the "this breaks the build according to the kernel test
> robot"?
>
> I think that needs to be fixed
On Wed, Mar 10, 2021 at 03:47:10PM +0100, Rafael J. Wysocki wrote:
> On Fri, Mar 5, 2021 at 7:29 PM Rafael J. Wysocki wrote:
> >
> > From: Rafael J. Wysocki
> >
> > The ACPI_MODULE_NAME() definition is only used by the message
> > printing macros from ACPICA that are not used by the code in
> >
On Sun, Feb 28, 2021 at 08:39:29PM +0200, Mihai Carabas wrote:
> Hello,
>
> Any feedback on this last series?
Other than the "this breaks the build according to the kernel test
robot"?
I think that needs to be fixed before we can do anything here...
thnaks,
greg k-h
On Wed, Mar 10, 2021, Joerg Roedel wrote:
> From: Joerg Roedel
>
> The 32-bit #VC handler has no GHCB and can only handle CPUID exit codes.
> It is needed by the early boot code to handle #VC exceptions raised in
> verify_cpu() and to get the position of the C bit.
>
> But the CPUID information
On 08.03.21 17:45, David Hildenbrand wrote:
I. Background: Sparse Memory Mappings
When we manage sparse memory mappings dynamically in user space - also
sometimes involving MAP_NORESERVE - we want to dynamically populate/
discard memory inside such a sparse memory region. Example users are
Hi Claire,
On Tue, Feb 09, 2021 at 02:21:30PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
>
>
On Wed, Mar 10, 2021 at 02:07:05PM +0100, Michal Hocko wrote:
> On Tue 09-03-21 23:42:46, Minchan Kim wrote:
> > On Tue, Mar 09, 2021 at 08:15:41AM -0800, Minchan Kim wrote:
> >
> > < snip >
> >
> > > > [...]
> > > > > +void dump_migrate_failure_pages(struct list_head *page_list)
> > > > > +{
>
This fixes below build warning.
../drivers/virt/acrn/vm.c:105: warning: expecting prototype for
acrn_inject_msi(). Prototype was for acrn_msi_inject() instead
Fixes: c7cf8d27244f ("virt: acrn: Introduce interrupt injection interfaces")
Signed-off-by: Shuo Liu
---
drivers/virt/acrn/vm.c | 2 +-
Hello,
syzbot found the following issue on:
HEAD commit:144c79ef Merge tag 'perf-tools-fixes-for-v5.12-2020-03-07'..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1572d952d0
kernel config: https://syzkaller.appspot.com/x/.config?x=ccdd84f79f45b23d
On Wed, Mar 10, 2021 at 07:48:08AM -0800, Alexei Starovoitov wrote:
> Ack for bpf bits.
Thanks!
> I think the cleanup is good from the point of having one way to do things.
Right, that was the motivation. Currently x86 is the sole architecture
(and thus weird and more complicated) where NOPs
On Mon, Feb 22, 2021 at 05:14:09AM +0530, Mahak Gupta wrote:
> This patches fixes the checks- 'Alignment should match open parenthesis'
> of 'checkpatch.pl'.
>
> Signed-off-by: Mahak Gupta
> ---
> drivers/staging/octeon-usb/octeon-hcd.c | 32 +
> 1 file changed, 17
Am 10.03.21 um 16:58 schrieb Jiaxun Yang:
>
>
> 在 2021/3/10 21:26, Oleksij Rempel 写道:
> [...]
>> I would like to understand, why it is impossible. Do fw_arg0 provide memory
>> address or some kind of
>> count/size? Can it be negative?
>>
>> We already had same situation with ARM and it was fixed.
This patch fixes the max register address of MAX 10 BMC. The range
0x2000 ~ 0x20fc are for control registers of the QSPI flash
controller, which are not accessible to host.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-for-MFD-by: Lee Jones
---
v2: no change.
v3: no change,
This patchset is some improvements for intel-m10-bmc and its subdevs.
Main changes from v1:
- Add a patch (#2) to simplify the definition of the legacy version reg.
- Add a patch (#4), add entry in MAINTAINERS for intel-m10-bmc mfd driver
and the subdev drivers.
Main changes from v2:
- Add Tom
The version register is the only one in the legacy I/O space to be
accessed, so it is not necessary to define the legacy base & version
register offset. A direct definition of the legacy version register
address would be fine.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
---
v3: no change,
From: Matthew Gerlach
This patch adds access tables to the MAX 10 BMC regmap. This prevents
the host from accessing the unwanted I/O space. It also filters out the
invalid outputs when reading the regmap debugfs interface.
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
Reviewed-by:
This patch adds maintainer info for Intel MAX 10 mfd driver.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-for-MFD-by: Lee Jones
---
v3: Add Tom Rix as the reviewer.
v4: Add Lee's Acked-by, no other change.
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 3/10/21 12:52 AM, John Garry wrote:
On 09/03/2021 19:21, Bart Van Assche wrote:
Regarding this patch series, I have shared the feedback I wanted to
share so I would appreciate it if someone else could also take a look.
So I can incorporate any changes and suggestions so far and send a
On Wed, Mar 10, 2021 at 02:04:55PM +0100, Michal Hocko wrote:
< snip >
> > > Also are all those CONFIG_DYNAMIC_DEBUG* ifdefs necessary? Can we
> > > simply enable DYNAMIC_DEBUG for page_alloc as I've suggested above?
> >
> > They are different usecases.
> >
> > With DYNAMIC_DEBUG_MODULE with
On Mon, Mar 08, 2021 at 04:18:52PM -0800, Mike Kravetz wrote:
> The concurrent use of multiple hugetlb page sizes on a single system
> is becoming more common. One of the reasons is better TLB support for
> gigantic page sizes on x86 hardware. In addition, hugetlb pages are
> being used to back
On Wed, Mar 10, 2021 at 09:16:25AM +, Lee Jones wrote:
> On Mon, 01 Mar 2021, Xu Yilun wrote:
>
> > The version register is the only one in the legacy I/O space to be
> > accessed, so it is not necessary to define the legacy base & version
> > register offset. A direct definition of the
On 3/5/21 7:14 AM, John Garry wrote:
diff --git a/block/blk.h b/block/blk.h
index 3b53e44b967e..1a948bfd91e4 100644
--- a/block/blk.h
+++ b/block/blk.h
@@ -201,10 +201,29 @@ void elv_unregister_queue(struct request_queue *q);
static inline void elevator_exit(struct request_queue *q,
On 3/10/21 5:37 AM, Filippo Sironi wrote:
> We've seen a number of crashes with the following signature:
>
> BUG: kernel NULL pointer dereference, address:
> #PF: supervisor read access in kernel mode
> #PF: error_code(0x) - not-present page
> ...
> Oops:
Hi Dave,
Thanks for the comprehensive comments!
On Wed. 10 Mar 2021 at 04:44, Dave Taht wrote:
>
> I note that "proof" is very much in the developer's opinion and
> limited testing base.
>
> Actual operational experience, as in a real deployment, with other
> applications,
> heavy context
On 3/10/2021 23:50, Greg Kroah-Hartman wrote:
> On Wed, Mar 10, 2021 at 11:37:51PM +0800, shuo.a@intel.com wrote:
>> From: Shuo Liu
>>
>> This fixes below sparse warning.
>>
>> ../drivers/virt/acrn/vm.c:105: warning: expecting prototype for
>> acrn_inject_msi(). Prototype was for
On 3/10/21 7:11 AM, Jarkko Sakkinen wrote:
>>> - section = _epc_sections[epc_page->section];
>>> - spin_lock(>lock);
>>> - list_add_tail(_page->list, >page_list);
>>> - section->free_cnt++;
>>> - spin_unlock(>lock);
>>> +
Do not configure torrent SERDES if it's already configured.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 32 ---
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 84 ++-
1 file
Hi Josh and Daniel,
On Wed, 10 Mar 2021 09:08:45 -0600
Josh Poimboeuf wrote:
> On Wed, Mar 10, 2021 at 06:57:34PM +0900, Masami Hiramatsu wrote:
> > > If I understand correctly, for #1 you need an unwind hint which treats
> > > the instruction *after* the "pushq %rsp" as the beginning of the
>
No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Faiz Abbas
Serdes lanes might be shared between multiple cores in some usecases
and its not possible to lock PLLs for both the lanes independently
by the two cores. This requires a bootloader to configure both the
lanes at early boot time.
To handle this case, skip all configuration if
Add support to skip SERDES configuration if it's already configured in
bootloader.
The wiz part was initially sent in [1] but that was sent more in the
context of Sierra but this is in context of Torrent. The Sierra part
would be sent later.
[1] ->
On 3/4/21 4:12 PM, Shuah Khan wrote:
On 3/3/21 9:35 PM, Lucas Stankus wrote:
On Wed, Mar 03, 2021 at 12:56:05PM -0800, Brendan Higgins wrote:
Did you change anything other than fixing the Signed-off-by that Shuah
requested?
No, I only fixed the Signed-off-by warning.
Generally when you
On 10/03/2021 16:47, Krzysztof Kozlowski wrote:
> On 10/03/2021 16:39, Arnd Bergmann wrote:
>> On Wed, Mar 10, 2021 at 4:06 PM Krzysztof Kozlowski
>> wrote:
>>> On 10/03/2021 15:45, Tom Rix wrote:
On 3/10/21 1:45 AM, Lee Jones wrote:
>>>
>>> Many other architectures do not have vendor prefix
On Wed, Mar 10, 2021 at 04:37:21PM +0100, Fabio Aiuto wrote:
> fix the following checkpatch warnings:
>
> WARNING: Block comments use * on subsequent lines
> + /*
> + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
> --
> WARNING: Block comments use * on subsequent
> static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
> u8 *data)
> {
> struct mvpp2_port *port = netdev_priv(netdev);
> int i, q;
>
> - if (sset != ETH_SS_STATS)
> - return;
> + switch (sset) {
> +
Hi,
On Wed, Mar 10, 2021 at 2:37 AM Srinivas Kandagatla
wrote:
>
>
>
> On 06/03/2021 00:26, Douglas Anderson wrote:
> > Sometimes the clients of nvmem just want to get a number out of
> > nvmem. They don't want to think about exactly how many bytes the nvmem
> > cell took up. They just want the
On Wed, Mar 10, 2021 at 11:37:51PM +0800, shuo.a@intel.com wrote:
> From: Shuo Liu
>
> This fixes below sparse warning.
>
> ../drivers/virt/acrn/vm.c:105: warning: expecting prototype for
> acrn_inject_msi(). Prototype was for acrn_msi_inject() instead
That is not a warning from sparse :(
On Wed, Mar 10, 2021, Jarkko Sakkinen wrote:
> On Wed, Mar 03, 2021 at 08:56:52AM -0800, Dave Hansen wrote:
> > On 3/3/21 7:03 AM, Jarkko Sakkinen wrote:
> > > If sgx_page_cache_init() fails in the middle, a trivial return
> > > statement causes unused memory and virtual address space reserved for
On Wed, Mar 10, 2021 at 6:29 AM Peter Zijlstra wrote:
>
> On Wed, Mar 10, 2021 at 09:13:24AM -0500, Steven Rostedt wrote:
> > On Wed, 10 Mar 2021 11:22:48 +0100
> > Peter Zijlstra wrote:
> >
> > > After this FEATURE_NOPL is unused except for required-features for
> > > x86_64. FEATURE_K8 is only
On 10/03/2021 16:39, Arnd Bergmann wrote:
> On Wed, Mar 10, 2021 at 4:06 PM Krzysztof Kozlowski
> wrote:
>> On 10/03/2021 15:45, Tom Rix wrote:
>>> On 3/10/21 1:45 AM, Lee Jones wrote:
>>
>> Many other architectures do not have vendor prefix (TEGRA, EXYNOS,
>> ZYNQMP etc). I would call it the
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/phy/phy-cadence-sierra.yaml| 17 -
include/dt-bindings/phy/phy-cadence.h
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Kishon
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 40 ++--
1 file changed, 37
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
---
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().
Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11
Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which
"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Fixes:
Patch series adds support in Sierra driver to use external clock.
v1 of the patch series can be found @ [1]
v2 of the patch series can be found @ [2]
v3 of the patch series can be found @ [3]
v5 of the patch series can be found @ [5]
v6 of the patch series can be found @ [6]
Changes from v5:
1)
On 3/9/21 8:15 AM, Srinivas Kandagatla wrote:
currently the internal bitmask used for allocating ports starts with offset 0.
This is bit confusing as data port numbers on Qualcomm controller are valid
from 1 to 14. So adjust this bit mask accordingly, this will also help while
adding static
On Wed, Mar 10, 2021 at 09:20:40AM +0100, David Hildenbrand wrote:
> On 10.03.21 08:42, Minchan Kim wrote:
> > On Tue, Mar 09, 2021 at 08:15:41AM -0800, Minchan Kim wrote:
> >
> > < snip >
> >
> > > > [...]
> > > > > +void dump_migrate_failure_pages(struct list_head *page_list)
> > > > > +{
> >
list_for_each_entry(m_rt, >m_rt_list, bus_node) {
@@ -473,8 +475,13 @@ static int qcom_swrm_compute_params(struct sdw_bus *bus)
}
list_for_each_entry(s_rt, _rt->slave_rt_list, m_rt_node) {
+ slave = s_rt->slave;
>>> + * node.
>>> + */
>>> +static struct sgx_numa_node *sgx_numa_nodes;
>>> +
>>> +/*
>>> + * sgx_free_epc_page() uses this to find out the correct struct
>>> sgx_numa_node,
>>> + * to put the page in.
>>> + */
>>> +static int sgx_section_to_numa_node_id[SGX_MAX_EPC_SECTIONS];
>>
>> If this is
On 3/10/21 7:35 AM, Mark Brown wrote:
On Tue, Mar 09, 2021 at 01:41:45PM -0600, Pierre-Louis Bossart wrote:
The problem is that the cards are platform devices created by the parent
(which itself may be a PCI or ACPI device) and have nothing to do with ACPI.
Could we flip the logic and
On Mon 08-03-21 18:28:07, Muchun Song wrote:
> When the "struct page size" crosses page boundaries we cannot
> make use of this feature. Let free_vmemmap_pages_per_hpage()
> return zero if that is the case, most of the functions can be
> optimized away.
I am confused. Don't you check for this in
On 3/9/21 6:51 PM, Moritz Fischer wrote:
> Hi Tom,
> On Tue, Mar 09, 2021 at 08:03:09AM -0800, Tom Rix wrote:
>> Moritz,
>>
>> This and the next patchset apply to today's char-misc-next.
>>
>> However they conflicts with other in flight linux-fpga patchsets.
>>
>> Since I believe these patchsets
On Wed, 10 Mar 2021 15:21:01 +0100 (CET)
Miroslav Benes wrote:
> Hi Masami,
>
> > --- a/include/linux/kprobes.h
> > +++ b/include/linux/kprobes.h
> > @@ -205,15 +205,23 @@ extern void arch_prepare_kretprobe(struct
> > kretprobe_instance *ri,
> >struct pt_regs
On Mon 08-03-21 18:28:06, Muchun Song wrote:
> For HugeTLB page, there are more metadata to save in the struct page.
> But the head struct page cannot meet our needs, so we have to abuse
> other tail struct page to store the metadata. In order to avoid
> conflicts caused by subsequent use of more
On Wed, Mar 10, 2021 at 4:06 PM Krzysztof Kozlowski
wrote:
> On 10/03/2021 15:45, Tom Rix wrote:
> > On 3/10/21 1:45 AM, Lee Jones wrote:
>
> Many other architectures do not have vendor prefix (TEGRA, EXYNOS,
> ZYNQMP etc). I would call it the same as in ARMv7 - ARCH_SOCFPGA - but
> the Altera
From: Shuo Liu
hsm.c:336:50: warning: incorrect type in argument 2 (different address spaces)
hsm.c:336:50:expected void const [noderef] __user *from
hsm.c:336:50:got void *
This patch fixes above sparse warning.
Fixes: 3d679d5aec64 ("virt: acrn: Introduce interfaces to query C-states
From: Shuo Liu
This fixes below sparse warning.
../drivers/virt/acrn/vm.c:105: warning: expecting prototype for
acrn_inject_msi(). Prototype was for acrn_msi_inject() instead
Fixes: c7cf8d27244f ("virt: acrn: Introduce interrupt injection interfaces")
Reported-by: kernel test robot
On Wed, 10 Mar 2021 at 06:53, Srikar Dronamraju
wrote:
>
> * Vincent Guittot [2021-03-08 14:52:39]:
>
> > On Fri, 26 Feb 2021 at 17:41, Srikar Dronamraju
> > wrote:
> > >
>
> Thanks Vincent for your review comments.
>
> > > +static int prefer_idler_llc(int this_cpu, int prev_cpu, int sync)
> >
On Fri, Mar 05, 2021 at 03:59:49PM -0500, Stefan Berger wrote:
> From: Saulo Alessandre
>
> Add the parameters for the NIST P384 curve and define a new curve ID
> for it. Make the curve available in ecc_get_curve.
>
> Summary of changes:
>
> * crypto/ecc_curve_defs.h
> - add nist_p384 params
On Mon 08-03-21 18:28:04, Muchun Song wrote:
> Add a kernel parameter hugetlb_free_vmemmap to enable the feature of
> freeing unused vmemmap pages associated with each hugetlb page on boot.
>
> We disables PMD mapping of vmemmap pages for x86-64 arch when this
> feature is enabled. Because
fix the following checkpatch warnings:
WARNING: Block comments use * on subsequent lines
+ /*
+ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
--
WARNING: Block comments use * on subsequent lines
+/*
+op_mode
Signed-off-by: Fabio Aiuto
---
On Wed, Mar 10, 2021 at 7:24 AM Andi Kleen wrote:
>
> The pebs_no_isolation optimization check is inverted. We want to disable
> PEBS isolation when the microcode is at least the revision in the table,
> not for older microcode. So remove the extra !.
The original code was correct because of the
From: Zi Yan
We do not have a direct user interface of splitting the compound page
backing a THP and there is no need unless we want to expose the THP
implementation details to users. Adding an interface for debugging.
By writing ",," to
/split_huge_pages_in_range_pid, THPs within the given
On Fri, Mar 05, 2021 at 03:59:47PM -0500, Stefan Berger wrote:
> From: Stefan Berger
>
> Add OIDs for ECDSA with sha224/256/384/512.
Nit: SHA224/256/384/512 (sorry cannot help myself with these, have been
doing this way too much, consider me as a bot :-) )
>
> Signed-off-by: Stefan Berger
Update the driver to use a function for referencing the UFS version.
This replaces the UFSHCI_VERSION_xy macros, and supports comparisons
where they did not.
Suggested-by: Christoph Hellwig
Signed-off-by: Caleb Connolly
Reviewed-by: Christoph Hellwig
---
drivers/scsi/ufs/ufshcd.c | 64
Replace the UFSHCI_VERSION_xy macros.
Signed-off-by: Caleb Connolly
---
drivers/scsi/ufs/ufs-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index f97d7b0ae3b6..2d54dce0eeda 100644
---
This check is redundant as all UFS versions are currently supported.
Signed-off-by: Nitin Rawat
Signed-off-by: Caleb Connolly
---
drivers/scsi/ufs/ufshcd.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index
When using a device with UFS > 2.1 the error "invalid UFS version" is
misleadingly printed. There was a patch for this almost a year
ago to which this solution was suggested.
This series replaces the use of the growing UFSHCI_VERSION_xy macros with
an inline function to encode a major and minor
On Fri, Mar 05, 2021 at 06:29:57PM +0100, Borislav Petkov wrote:
> On Mon, Mar 01, 2021 at 10:45:02PM +1300, Kai Huang wrote:
> > From: Sean Christopherson
> >
> > The kernel will currently disable all SGX support if the hardware does
> > not support launch control. Make it more permissive to
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