Re: [PATCH v3 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board

>> + { >> + vcc-pb-supply = <_dcdc1>; >> + vcc-pc-supply = <_eldo1>; >> + vcc-pd-supply = <_dcdc1>; >> + vcc-pe-supply = <_dldo2>; >> + vcc-pf-supply = <_dcdc1>; >> + vcc-pg-supply = <_dldo1>; >> + vcc-ph-supply = <_dcdc1>; >> +}; >There's something off here. The PC supply is set to eldo1, but

Re: [PATCH v3 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file

>Hi, > >Thanks for sending a new series > >On Wed, Jul 08, 2020 at 04:25:05PM +0800, Frank Lee wrote: >> + thermal-zones { >> + cpu_thermal_zone { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + thermal-sensors = < 0>; >> + }; >> + >> + gpu_thermal_zone { >> +

回复：[PATCH 2/4] pinctrl: sunxi: add support for the Allwinner A100 pin controller

>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), >> + SUNXI_FUNCTION(0x0, "gpio_in"), >> + SUNXI_FUNCTION(0x1, "gpio_out"), >> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ >> + SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */ >> + SUNXI_FUNCTION(0x4, "jtag"), /* MS_GPU */ > >We should use another name here, since

回复：[PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU

>> + /* Enable the lock bits on all PLLs */ >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { >> + val = readl(reg + pll_regs[i]); >> + val |= BIT(29); > >Having a define for that would be nice here > >> + writel(val, reg + pll_regs[i]); >> + } >> + >> + /* >> + * In order to pass the EMI