Hi Mathieu,
> > > > > > > > > > This is an initial patchset for allowing to turn on and off
> > > > > > > > > > the remote processor.
> > > > > > > > > > The FW is already loaded before the Corstone-1000 SoC is
> > > > > > > > > > powered on and this
> > > > > > > > > > is done through the FPGA
Hi Mathieu,
> > > > > > > > This is an initial patchset for allowing to turn on and off the
> > > > > > > > remote processor.
> > > > > > > > The FW is already loaded before the Corstone-1000 SoC is
> > > > > > > > powered on and this
> > > > > > > > is done through the FPGA board bootloader in
Hi Sudeep,
On Thu, Mar 14, 2024 at 03:19:13PM +, Sudeep Holla wrote:
> > The plan for the driver is as follows:
> >
> > Step 1: provide a foundation driver capable of turning the core on/off
> > Step 2: provide mailbox support for comms
> > Step 3: provide FW reload capability
> >
Hi Krzysztof,
On Thu, Mar 14, 2024 at 02:56:53PM +0100, Krzysztof Kozlowski wrote:
> On 14/03/2024 14:49, Abdellatif El Khlifi wrote:
> >> Frankly at the moment I'd be inclined to say it isn't even a remoteproc
> >> binding (or driver) at all, it's a reset
Hi Sudeep,
On Thu, Mar 14, 2024 at 02:59:20PM +, Sudeep Holla wrote:
> On Thu, Mar 14, 2024 at 08:52:59AM -0600, Mathieu Poirier wrote:
> > On Wed, Mar 13, 2024 at 05:17:56PM +, Abdellatif El Khlifi wrote:
> > > Hi Mathieu,
> > >
> > > On Wed, Mar 1
Hi Robin,
> > + firmware-name:
> > +description: |
> > + Default name of the firmware to load to the remote processor.
>
> So... is loading the firmware image achieved by somehow bitbanging it
> through the one reset register, maybe? I find it hard to believe this is a
> complete and
Hi Mathieu,
On Wed, Mar 13, 2024 at 10:25:32AM -0600, Mathieu Poirier wrote:
> On Tue, Mar 12, 2024 at 05:32:52PM +0000, Abdellatif El Khlifi wrote:
> > Hi Mathieu,
> >
> > On Tue, Mar 12, 2024 at 10:29:52AM -0600, Mathieu Poirier wrote:
> > > > This is an init
Hi Mathieu,
On Tue, Mar 12, 2024 at 10:29:52AM -0600, Mathieu Poirier wrote:
> > This is an initial patchset for allowing to turn on and off the remote
> > processor.
> > The FW is already loaded before the Corstone-1000 SoC is powered on and this
> > is done through the FPGA board bootloader in
Hi Mathieu,
On Fri, Mar 08, 2024 at 09:44:26AM -0700, Mathieu Poirier wrote:
> On Thu, 7 Mar 2024 at 12:40, Abdellatif El Khlifi
> wrote:
> >
> > Hi Mathieu,
> >
> > > > + do {
> > > > + state_reg = readl(priv->
Hi Sudeep,
> > + extsys0: remoteproc@1a010310 {
> > + compatible = "arm,corstone1000-extsys";
> > + reg = <0x1a010310 0x4>,
> > + <0x1a010314 0X4>;
>
>
> As per [1], this is just a few registers within the 64kB block.
> Not
Hi Krzysztof, Sudeep,
> > > diff --git a/Documentation/devicetree/bindings/remoteproc/arm,rproc.yaml
> > > b/Documentation/devicetree/bindings/remoteproc/arm,rproc.yaml
> > > new file mode 100644
> > > index ..322197158059
> > > --- /dev/null
> > > +++
Hi Mathieu,
> > + do {
> > + state_reg = readl(priv->reset_cfg.state_reg);
> > + *rst_ack = EXTSYS_RST_ST_RST_ACK(state_reg);
> > +
> > + if (*rst_ack == EXTSYS_RST_ACK_RESERVED) {
> > + dev_err(dev, "unexpected RST_ACK value: 0x%x\n",
> > +
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