On Wed, 23 Dec 2020 10:48:10 +0100 Helge Deller wrote:
> > static int proc_pid_wchan(struct seq_file *m, struct pid_namespace *ns,
> > struct pid *pid, struct task_struct *task)
> > {
> > - unsigned long wchan;
> > -
> > if (ptrace_may_access(task,
Look at the commit message wording:
The patch adds a new
capability so that macb_set_tx_clock() to not be called for IPs having
this capability
So MACB_CAPS_CLK_HW_CHG disables something, not enables it. So i
suspect this if statement is wrong and needs fixing.
Andrew
he byte offsets are:
0-1 prio
2-7 sa
8-9 port_role
10-11 state
12-13 transition
With packed you get
14-17 timestamp
which is not 32 bit aligned.
Do you mean the whole structure must be 32 bit aligned? We need to add
two reserved bytes to the end of the structure?
Andrew
On Wed, Dec 23, 2020 at 03:31:24PM +0100, Steen Hegelund wrote:
> On 19.12.2020 21:24, Andrew Lunn wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > > + port13: port@13 {
> &g
ence on error exit path")
Reviewed-by: Andrew Lunn
Andrew
On Mon, 21 Dec 2020 09:05:51 -0800 Roman Gushchin wrote:
> Subject: [PATCH v3 1/2] mm: cma: allocate cma areas bottom-up
i386 allmodconfig:
In file included from ./include/vdso/const.h:5,
from ./include/linux/const.h:4,
from ./include/linux/bits.h:5,
On Thu, 17 Dec 2020 17:54:13 +0100 Helge Deller wrote:
> To resolve the symbol fuction name for wchan, use the printk format
> specifier %ps instead of manually looking up the symbol function name
> via lookup_symbol_name().
>
> Signed-off-by: Helge Deller
>
Please don't forget the "^---$"
On Sun, 20 Dec 2020 16:27:49 +0800 Baoquan He wrote:
> VMware reported the performance regression during memmap_init() invocation.
> And they bisected to commit 73a6e474cb376 ("mm: memmap_init: iterate over
> memblock regions rather that check each PFN") causing it.
>
>
On Sun, 20 Dec 2020 11:02:15 -0800 Joe Perches wrote:
> On Mon, 2020-12-14 at 11:23 +0100, Nicolai Fischer wrote:
> > All '---help---' lines have been replaced by just 'help'.
> > Therefore it is no longer necessary to include '---' in the regex.
> >
> > Signed-off-by: Nicolai Fischer
> >
On Sun, 20 Dec 2020 13:10:51 -0800 Randy Dunlap wrote:
> Add a test to detect if the input ra request size has its high order
> bit set (is negative when tested as a signed long). This would be a
> really Huge readahead.
>
> If so, WARN() with the value and a stack trace so that we can see
>
= PHY_POLL_CABLE_TEST,
> + /* PHY_GBIT_FEATURES */
> + .probe = qca807x_probe,
> + .config_init= qca807x_config,
> + .read_status= qca807x_read_status,
> + .config_intr= qca807x_config_intr,
> + .ack_interrupt = qca807x_ack_intr,
> + .soft_reset = genphy_soft_reset,
> + .get_tunable= qca807x_get_tunable,
> + .set_tunable= qca807x_set_tunable,
> + .cable_test_start = qca807x_cable_test_start,
> + .cable_test_get_status = qca807x_cable_test_get_status,
> + },
> + {
> + PHY_ID_MATCH_EXACT(PHY_ID_QCA807X_PSGMII),
> + .name = "Qualcomm QCA807x PSGMII",
> + .probe = qca807x_psgmii_config,
This looks odd.
Andrew
he
value poked into the register. So the property would be
qcom,tx-driver-strength-mv and it would have the value 220 for
example.
> +
> + qcom,control-dac:
> +description: Analog MDI driver amplitude and bias current.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [0, 1, 2, 3, 4, 5, 6, 7]
Make here.
Andrew
On Tue, 22 Dec 2020 20:40:00 + Matthew Wilcox wrote:
> On Tue, Dec 22, 2020 at 07:49:52PM +0530, Souptick Joarder wrote:
> > Otherwise it cause gcc warning:
> > ^~~
>
> That line is just confusing.
I cleaned up the changelog. It is presently
: Subject:
TS first. Eventually, I think, the code
> here will read the same MAC address from chip registers as uboot did before.
Do we need to worry about, the chip contains random junk, which passes
the validitiy test? Before this patch the value from DT would be used,
and the random junk is ignored. Is this change possibly going to cause
a regression?
Andrew
een
> speeds 1G/2G5.
So it continues to use the SGMII inband signalling?
There is a lot of confusion in this area, but SGMII inband signalling
overclocked does not make much sense. So it is more likely to be using
2500BaseX.
Andrew
, SYS_RST_PROT_VCORE);
> > > +
> > > + regmap_write(gcb_ctrl, spx5_offset(GCB_SOFT_RST),
> > > + GCB_SOFT_RST_SOFT_SWC_RST_SET(1));
> > > +
> > > + return readx_poll_timeout(sparx5_read_gcb_soft_rst, gcb_ctrl,
> > > val,
> > > + GCB_SOFT_RST_SOFT_SWC_RST_GET(val)
> > > == 0,
> > > + 1, 100);
> > > +}
> > > +postcore_initcall(sparx5_switch_reset);
> >
> > That is pretty unusual. Why cannot this be done at probe time?
>
> The problem is that the switch core reset also affects (reset) the
> SGPIO controller.
>
> We tried to put this in the reset driver, but it was rejected. If the
> reset is done at probe time, the SGPIO driver may already have
> initialized state.
>
> The switch core reset will then reset all SGPIO registers.
Ah, O.K. Dumb question. Why is the SGPIO driver a separate driver? It
sounds like it should be embedded inside this driver if it is sharing
hardware.
Another option would be to look at the reset subsystem, and have this
driver export a reset controller, which the SGPIO driver can bind to.
Given that the GPIO driver has been merged, if this will work, it is
probably a better solution.
Andrew
On Tue, Dec 22, 2020 at 10:46:12AM +0100, Steen Hegelund wrote:
> Hi Andrew,
>
> On Sat, 2020-12-19 at 20:51 +0100, Andrew Lunn wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > > + /* Create
On Tue, Dec 22, 2020 at 11:09:41AM +0100, Lars Povlsen wrote:
>
> Andrew Lunn writes:
>
> > On Fri, Nov 13, 2020 at 03:51:51PM +0100, Lars Povlsen wrote:
> >> + led@8 {
> >> + label = "eth12:green";
> >> +
On Tue, Dec 22, 2020 at 12:59:08AM +0900, Masahiro Yamada wrote:
> On Tue, Dec 22, 2020 at 12:26 AM Andrew Lunn wrote:
> >
> > On Mon, Dec 21, 2020 at 02:43:23PM +0900, Masahiro Yamada wrote:
> > > The declaration of request_irq() in is marked as
> > >
On Tue, Dec 22, 2020 at 12:59:08AM +0900, Masahiro Yamada wrote:
> On Tue, Dec 22, 2020 at 12:26 AM Andrew Lunn wrote:
> >
> > On Mon, Dec 21, 2020 at 02:43:23PM +0900, Masahiro Yamada wrote:
> > > The declaration of request_irq() in is marked as
> > >
; ch->dma.desc = 0;
> - request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
> + ret = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx",
> priv);
> + if (ret) {
> + netdev_err(dev, "failed to request irq\n");
> + return ret;
And here you need to cleanup ltq_dma_alloc_rx().
Andrew
_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));
> + spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));
> + } else {
> + spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port));
> + spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port));
> + spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port));
> + }
Humm, interesting. This seems to control what other ports a port can
send to. That is one of the basic features you need for supporting
multiple bridges. So i assume your problems is you cannot partition
the MAC table?
Andrew
E_PORT_ENA |
> + QFWD_SWITCH_PORT_MODE_FWD_URGENCY,
> + sparx5,
> + QFWD_SWITCH_PORT_MODE(port->portno));
What does it mean by port forwarding? By default, packets should only
go to the CPU, until the port is added to a bridge. I've not thought
much about L3, since DSA so far only has L2 switches, but i guess you
don't need to enable L3 forwarding until a route out the port has been
added?
> +/* Initialize port config to default */
> +int sparx5_port_init(struct sparx5 *sparx5,
> + struct sparx5_port *port,
> + struct sparx5_port_config *conf)
> +{
> + /* Discard pause frame 01-80-C2-00-00-01 */
> + spx5_wr(0xC, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno));
The comment is about pause frames, but the macro contain BPDU?
Andrew
but i've been looking at the
switch driver patches recently, so went digging.
Can the Ethernet switch itself control these LEDs for indicating
things like packet receive/transmit, link state, and link speed? Or
are they purely software controlled?
Thanks
Andrew
go read the thread. The aim was
to allow sleeping, but i don't know if that as been achieved yet.
Andrew
; + reg = <56>;
> + max-speed = <10000>;
Why limit a 25G SFP to 10G?
Andrew
parx5, QS_INJ_WR(grp));
> +
> + /* Write words, round up */
> + count = ((skb->len + 3) / 4);
> + buf = skb->data;
> + for (w = 0; w < count; w++, buf += 4) {
> + val = get_unaligned((const u32 *)buf);
> + spx5_wr(val, sparx5, QS_INJ_WR(grp));
> + }
No DMA? What sort of performance do you get? Enough for the odd BPDU,
IGMP frame etc, but i guess you don't want any real bulk data to be
sent this way?
> +irqreturn_t sparx5_xtr_handler(int irq, void *_sparx5)
> +{
> + struct sparx5 *sparx5 = _sparx5;
> +
> + /* Check data in queue */
> + while (spx5_rd(sparx5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE))
> + sparx5_xtr_grp(sparx5, XTR_QUEUE, false);
> +
> + return IRQ_HANDLED;
> +}
Is there any sort of limit how many times this will loop? If somebody
is blasting 10Gbps at the CPU, will it ever get out of this loop?
Andrew
t; + if (IS_ERR(gcb_ctrl)) {
> + pr_err("No '%s' syscon map\n", syscon_gcb);
> + return PTR_ERR(gcb_ctrl);
> + }
> +
> + /* Make sure the core is PROTECTED from reset */
> + regmap_update_bits(cpu_ctrl, RESET_PROT_STAT,
> +SYS_RST_PROT_VCORE, SYS_RST_PROT_VCORE);
> +
> + regmap_write(gcb_ctrl, spx5_offset(GCB_SOFT_RST),
> + GCB_SOFT_RST_SOFT_SWC_RST_SET(1));
> +
> + return readx_poll_timeout(sparx5_read_gcb_soft_rst, gcb_ctrl, val,
> + GCB_SOFT_RST_SOFT_SWC_RST_GET(val) == 0,
> + 1, 100);
> +}
> +postcore_initcall(sparx5_switch_reset);
That is pretty unusual. Why cannot this be done at probe time?
> +/* Clock period in picoseconds */
> +static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
> +{
> + switch (cclock) {
> + case SPX5_CORE_CLOCK_250MHZ:
> + return 4000;
> + case SPX5_CORE_CLOCK_500MHZ:
> + return 2000;
> + case SPX5_CORE_CLOCK_625MHZ:
> + default:
> + return 1600;
> + }
> +}
Is this something which is used in the hot path?
> --- /dev/null
> +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
> @@ -0,0 +1,3922 @@
> +/* SPDX-License-Identifier: GPL-2.0+
> + * Microchip Sparx5 Switch driver
> + *
> + * Copyright (c) 2020 Microchip Technology Inc.
> + */
> +
> +/* This file is autogenerated by cml-utils 2020-11-19 10:41:34 +0100.
> + * Commit ID: f34790e69dc252103e2cc3e85b1a5e4d9e3aa190
> + */
How reproducible this is generation process? If you have to run it
again, will it keep the same order of lines?
Andrew
On Thu, Dec 17, 2020 at 08:51:27AM +0100, Steen Hegelund wrote:
> Document the Sparx5 switch device driver bindings
>
> Signed-off-by: Steen Hegelund
> Signed-off-by: Lars Povlsen
Reviewed-by: Andrew Lunn
Andrew
On Fri, 18 Dec 2020 09:39:30 +0530 Souptick Joarder
wrote:
> On Thu, Dec 17, 2020 at 7:53 AM Matthew Wilcox wrote:
> >
> > On Thu, Dec 17, 2020 at 10:03:11AM +0800, Xiangyang Yu wrote:
> > > Fixed the warning when building with warnings enabled (W=1),
> > > This function is only used in
Determined by scope measurements at speed.
Signed-off-by: Andrew Jeffery
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
Add myself as the maintainer.
Signed-off-by: Andrew Jeffery
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e451dcce054f..eae4322aae67 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2826,6 +2826,15 @@ F:
Documentation
the extracted values to hardware as required.
Signed-off-by: Andrew Jeffery
---
drivers/mmc/core/host.c | 44
include/linux/mmc/host.h | 13
2 files changed, 57 insertions(+)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index
-by: Andrew Jeffery
---
drivers/mmc/host/sdhci-of-aspeed.c | 216 +++--
1 file changed, 208 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c
b/drivers/mmc/host/sdhci-of-aspeed.c
index 4f008ba3280e..b1a14e7dda82 100644
--- a/drivers/mmc/host/sdhci
The AST2600 can achieve HS200 speeds with a change to the bus clock
divisor behaviour. The divisor can also be more accurate with respect
to the requested clock rate, but keep the one-hot behaviour for
backwards compatibility with the AST2400 and AST2500.
Signed-off-by: Andrew Jeffery
Converting degrees of phase to logic delays is irritating to test on
hardware, so lets exercise the function using KUnit.
Signed-off-by: Andrew Jeffery
---
drivers/mmc/host/Kconfig| 14
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-aspeed
of a struct containing the
phase array.
I've just done a quick build test of v6 given the small change and more
extensive testing done with v5.
v5 can be found here:
https://lore.kernel.org/linux-mmc/20201208012615.2717412-1-and...@aj.id.au/
Please review!
Cheers,
Andrew
Andrew Jeffery (6
On Thu, 17 Dec 2020, at 13:19, Billy Tsai wrote:
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
>
> Signed-off-by: Billy Tsai
Reviewed-by: Andrew Jeffery
Thanks Billy.
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +-
On 16/12/2020 08:21, Jürgen Groß wrote:
> On 15.12.20 21:59, Andrew Cooper wrote:
>> On 15/12/2020 11:10, Juergen Gross wrote:
>>> In case a process waits for any Xenstore action in the xenbus driver
>>> it should be interruptible by signals.
>>>
>>>
_mmd() and
phy_write_mmd()? If i'm wrong and these will not work, please say
so. Don't just ignore comments.
Andrew
On Thu, Dec 17, 2020 at 06:11:19PM +0530, Divya Koppera wrote:
> This patch add supports for Link up and Link down interrupts
> to LAN8814 phy.
>
> Signed-off-by: Divya Koppera
Reviewed-by: Andrew Lunn
Andrew
David and
Jakub handle stable patches directly.
Andrew
CU414, 8));
> -SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8));
> +SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8),
Good catch, looks like a copy/paste fail on my part :)
> +SIG_DESC_CLEAR(SCU414, 8));
As above, this should be unnecessary.
Can
> Ah, I thought it will be picked up automatically after the merge
> window is closed, no?
Nope. With netdev, if it is not merged in about 3 days, it needs to be
reposted. And it might need a rebased after the merge window closes
and net-next reopens.
Andrew
On Wed, Dec 16, 2020 at 08:55:51PM +0530, Divya Koppera wrote:
> This patch add supports for 1588 Hardware Timestamping support
> to LAN8814 Quad Phy. It supports L2 and Ipv4 encapsulations.
>
> Signed-off-by: Divya Koppera
You need to Cc: the PTP maintainer:
Richard Cochran
Andrew
(irq_status & LAN8814_INTS_ALL)
> + phy_mac_interrupt(phydev);
This is a PHY driver, so it should not be using the MAC API
call. Please change to
phy_trigger_machine(phydev);
Andrew
dware switch.
>
> This patch addresses the issue by monitoring the addresses learnt by the
> software bridge on eno0, and adding/deleting them as static FDB entries
> on the CPU port accordingly.
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Andrew
On Sun, Dec 13, 2020 at 04:07:09PM +0200, Vladimir Oltean wrote:
> Some DSA switches (and not only) cannot learn source MAC addresses from
> packets injected from the CPU. They only perform hardware address
> learning from inbound traffic.
Reviewed-by: Andrew Lunn
Andrew
itchdev_work) is not called.
>
> We can avoid scheduling the worker for nothing and say NOTIFY_DONE.
> Because we don't call dsa_fdb_offload_notify, the static FDB entry will
> remain just in the software bridge.
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Andrew
the error message, and drop dev_close().
>
> Signed-off-by: Vladimir Oltean
Reviewed-by: Andrew Lunn
Andrew
the bridge's FDB.
Reviewed-by: Andrew Lunn
Andrew
On Tue, Dec 15, 2020 at 10:22:00PM +0100, Michael Walle wrote:
> Now that there aren't any more macros with parameters, move the macros
> above any functions.
>
> Signed-off-by: Michael Walle
Reviewed-by: Andrew Lunn
Andrew
On Tue, Dec 15, 2020 at 10:21:59PM +0100, Michael Walle wrote:
> value is u16, masking with 0x is a nop. Drop it.
>
> Signed-off-by: Michael Walle
Reviewed-by: Andrew Lunn
Andrew
> since it is used just once.
>
> Signed-off-by: Michael Walle
Reviewed-by: Andrew Lunn
Andrew
ead. Drop the macro
> indirections.
>
> Signed-off-by: Michael Walle
Reviewed-by: Andrew Lunn
Andrew
at
> can't be changed.
Is there pinmux support for these pins? Can you disconnect them from
the MAC? Often pins can be connected to different internal IP
blocks. Maybe you can flip the pin mux, perform the MAC reset, and
then put the pinmux back to connect the pins to the MAC IP again?
Andrew
using the MAC, not just the AST2600 EVB. Why is
this patch an appropriate course of action? Can we not add a quirk targeting the
specific board (e.g. a devicetree property)?
Andrew
er load). If xenstored isn't up, blocking isn't ok.
Therefore, I think we need to distinguish "not yet on the ring" from "on
the ring", as our distinction as to whether cancelling is safe, and
ensure we don't queue anything on the ring before we're sure xenstored
has started up.
Does this make sense?
~Andrew
estion is, is that under software control, or is the hardware
synthesised so that the GPIO controller is reset as part of the MAC
reset?
>From what you are saying, it sounds like from software you cannot
independently control the GPIO controller reset?
This is something i would be asking the hardware people. Look at the
VHDL, etc.
Andrew
On Mon, 14 Dec 2020 18:16:34 -0800 (PST) Hugh Dickins wrote:
> On Mon, 14 Dec 2020, Andrew Morton wrote:
> > On Thu, 5 Nov 2020 16:55:30 +0800 Alex Shi
> > wrote:
> >
> > > This version rebase on next/master 20201104, with much of Johannes's
> > > Acks
On Mon, 14 Dec 2020 18:06:29 -0800 Jakub Kicinski wrote:
> On Mon, 14 Dec 2020 17:40:21 -0800 Andrew Morton wrote:
> > On Mon, 14 Dec 2020 17:29:43 -0800 Roman Gushchin wrote:
> > > On Tue, Dec 15, 2020 at 07:21:56AM +1100, Stephen Rothwell wrote:
> > > > On
m-current tree.
> > >
> ...
> >
> > Just a reminder that this conflict still exists. Commit bcfe06bf2622
> > is now in the net-next tree.
>
> Thanks, Stephen!
>
> I wonder if it's better to update these 2 commits in the mm tree to avoid
> conflicts?
>
&
On Thu, 5 Nov 2020 16:55:30 +0800 Alex Shi wrote:
> This version rebase on next/master 20201104, with much of Johannes's
> Acks and some changes according to Johannes comments. And add a new patch
> v21-0006-mm-rmap-stop-store-reordering-issue-on-page-mapp.patch to support
> v21-0007.
I assume
Hi Chiawei,
On Mon, 14 Dec 2020, at 13:14, ChiaWei Wang wrote:
> Hi Andrew & Rob,
>
> Do you have any suggestion on this patch?
Rob hasn't responded, but I think it will be easier to get an Ack out of him if
we do a v2 of the binding so we're not breaking backwards-
On Tue, 15 Dec 2020, at 02:18, Ulf Hansson wrote:
> On Tue, 8 Dec 2020 at 02:26, Andrew Jeffery wrote:
> >
> > Drivers for MMC hosts that accept phase corrections can take advantage
> > of the helper by embedding a mmc_clk_phase_map_t object in their
> >
On Mon, 14 Dec 2020 22:58:34 +0800 kernel test robot
wrote:
> Greeting,
>
> FYI, we noticed the following commit (built with gcc-9):
>
> commit: fb728736669f7805bcc0fa1c4d578faf991d62a8 ("epoll: wire up syscall
> epoll_pwait2")
>
On Mon, 14 Dec 2020 13:16:39 -0800 (PST) Hugh Dickins wrote:
> Andrew, please don't rush
>
> mmthpshmem-limit-shmem-thp-alloc-gfp_mask.patch
> mmthpshm-limit-gfp-mask-to-no-more-than-specified.patch
> mmthpshmem-make-khugepaged-obey-tmpfs-mount-flags.patch
>
> to Lin
phys have a kszphy_priv. Yet in
kszphy_config_reset() you seem to assume it is a lan8814_priv. This is
dangerous.
It would be much better to define a kszphy_ptp_priv structure, and put
a pointer to it in kszphy_priv. Allocate this structure in
lan8814_probe() and leave it NULL otherwise.
Andrew
en add the PTP support, for
example.
Andrew
KSZ_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
> + if (val != 0) {
> + phydev_err(phydev, "Error: phy_write_mmd has returned error
> %d\n",
> +val);
> + return val;
> + }
> + return 0;
> +}
I think you can just use phy_read_mmd() and phy_write_mmd().
Andrew
HY reset, what neither
> the STTMAC driver nor the PHY subsystem expect at all.
Is the reset of the GPIO sub block under software control? When you
have a GPIO controller implemented, you would want to disable this.
Once you have a GPIO controller, you can make use of the standard PHY
DT properties to allow the PHY driver to make use of the interrupt,
and to control the reset of the PHY.
Andrew
borate about an issue, because this seems to be a hack?
Yep - Troy please provide more information. What was the warning you saw? How
were the GPIOs allocated on the system that triggered the warning? What did you
do to trigger the warning?
Andrew
On Fri, Dec 11, 2020 at 10:05:41AM +0100, Steen Hegelund wrote:
> Add Sparx5 serdes driver node, and enable it generally for all
> reference boards.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Andrew
On Fri, Dec 11, 2020 at 10:05:40AM +0100, Steen Hegelund wrote:
> Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G
> interfaces available in the Sparx5 SoC.
>
> Signed-off-by: Bjarni Jonasson
> Signed-off-by: Steen Hegelund
Reviewed-by: Andrew Lunn
Andrew
egelund
Reviewed-by: Andrew Lunn
Andrew
On Fri, Dec 11, 2020 at 10:05:38AM +0100, Steen Hegelund wrote:
> Document the Sparx5 ethernet serdes phy driver bindings.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> Reviewed-by: Rob Herring
Reviewed-by: Andrew Lunn
Andrew
spect to any remaining state needing initialisation.
Beyond this, there is nothing magic I'm aware of.
We have seen soft lockups before in certain scenarios, simply due to the
quantity of events hitting vCPU0 before irqbalance gets around to
spreading the load. This is why there is an attempt to round-robin the
userspace event channel affinities by default, but I still don't see why
this would need custom affinity logic itself.
Thanks,
~Andrew
On Thu, Dec 10, 2020 at 4:31 PM Shuah Khan wrote:
>
> On 12/10/20 5:10 PM, Andrew Delgadillo wrote:
> > On Thu, Dec 10, 2020 at 3:08 PM Nick Desaulniers
> > wrote:
> >>
> >> On Thu, Dec 3, 2020 at 2:10 PM Andrew Delgadillo wrote:
> >>>
>
On Fri, 11 Dec 2020 13:43:39 + Chris Down wrote:
> Hi folks,
>
> Andrew Morton writes:
> >@@ -188,6 +190,10 @@ void quarantine_put(struct kasan_free_me
> > local_irq_save(flags);
> >
> > q = this_cpu_ptr(_quarantine);
> >+if (q->offline)
>
> Signed-off-by: Marcin Wojtas
Acked-by: Andrew Lunn
Andrew
On Thu, 10 Dec 2020 17:25:30 +0100 Marco Elver wrote:
> On Thu, 10 Dec 2020 at 14:29, Miguel Ojeda
> wrote:
> > On Thu, Dec 10, 2020 at 11:35 AM Marco Elver wrote:
> > >
> > > It looks like there's no clear MAINTAINER for this. :-/
> > > It'd still be good to fix this for 5.11.
> >
> > Richard
On Thu, Dec 10, 2020 at 3:08 PM Nick Desaulniers
wrote:
>
> On Thu, Dec 3, 2020 at 2:10 PM Andrew Delgadillo wrote:
> >
> > lib.mk defaults to gcc when CC is not set. When building selftests
> > as part of a kernel compilation, MAKEFLAGS is cleared to allow implicit
&g
n guess you have a protocol misconfiguration.
What exactly does link at this level mean? And thinking of the wider
uses of the PHY subsystem, what would link mean at this level for
SATA, PCIe, USB? Don't these all have some protocol level above
similar to Ethernet PCS which is the real determiner of link?
Andrew
l name. After fixing this typo the
errinjct tool functions again as expected.
[root@ltcalpine2-lp5 linux]# errinjct open
RTAS error injection facility open, token = 1
fixes: bd59380c5ba4 ("powerpc/rtas: Restrict RTAS requests from userspace")
Signed-off-by: Tyrel Datwyler
Thanks for ca
On Tue, 8 Dec 2020 08:24:02 + Anton Altaparmakov wrote:
> Can you please apply this?
>
> ...
>
> > --- a/fs/ntfs/logfile.c
> > +++ b/fs/ntfs/logfile.c
> > @@ -507,7 +507,7 @@ bool ntfs_check_logfile(struct inode *log_vi,
> > RESTART_PAGE_HEADER **rp)
> > * optimize log_page_size and
On Wed, Dec 09, 2020 at 03:03:35PM +0200, Claudiu Beznea wrote:
> Unprepare clocks in case of any failure in fu540_c000_clk_init().
>
> Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000")
> Signed-off-by: Claudiu Beznea
Reviewed-by: Andrew Lunn
Andrew
On Wed, Dec 09, 2020 at 03:03:34PM +0200, Claudiu Beznea wrote:
> Add function to disable all macb clocks.
>
> Signed-off-by: Claudiu Beznea
> Suggested-by: Andrew Lunn
Reviewed-by: Andrew Lunn
Andrew
e
* handled by the phy. Implementations are free to tune the
* parameters passed as arguments if needed by some
* implementation detail or constraints. It must not change
* any actual configuration of the PHY, so calling it as many
* times as deemed fit by the consumer must have no side
* effect.
*
* Returns: 0 if the configuration can be applied, an negative
* error code otherwise
*/
So why are returning link up information?
Andrew
don't split
patches like this, it makes review very difficult.
Andrew
t; the CPU port supports an MTU of 1500+the tagging overhead.
>
> Fixes: bfcb813203e6 ("net: dsa: configure the MTU for switch ports")
> Cc: Vladimir Oltean
> Signed-off-by: Rasmus Villemoes
Reviewed-by: Andrew Lunn
Andrew
On Thu, Dec 10, 2020 at 06:47:00AM +0800, Wong Vee Khee wrote:
> Assign stmmac's mdio_bus probe capabilities to MDIOBUS_C22_C45.
> This extended the probing of C45 PHY devices on the MDIO bus.
>
> Signed-off-by: Wong Vee Khee
Reviewed-by: Andrew Lunn
Andrew
rn err;
> +}
> +
> +irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int
> port,
> + int lane)
Maybe here as well?
> +int mv88e6393x_setup_errata(struct mv88e6xxx_chip *chip)
It should have _serdes_ in the name to follow the naming convention.
Andrew
Signed-off-by: Pavana Sharma
I see here you did actually act on my comment. Thanks.
But i also said:
> Other than that:
>
> Reviewed-by: Andrew Lunn
Please add such tags to new versions of the patches. It then makes it
easier for everybody to know the review state of the patches, which
On Wed, 9 Dec 2020 19:51:05 +0100 Marco Elver wrote:
> > This is no logner the case: in-kernel MTE is never enabled unless the
> > CONFIG_KASAN_HW_TAGS is enabled, so there are no more conflicts with
> > CONFIG_KASAN_SW_TAGS.
> >
> > Allow CONFIG_KASAN_SW_TAGS to be enabled even when
omment? 10GBASE-R has a comment
> because it is different from the rest, XFI and SFI caused a of
> discussion, and it was used wrong. But there does not seem to be
> anything special for 5GBASE-R.
Please don't ignore comments. If you don't understand, please ask. If
you think the comments are wrong, please explain why, so we can
discuss it.
Andrew
eplying. Why is 5gbase-r special and it needs a
comment, saying the same thing in CAPS LETTERS? What value is there in
the CAPS LETTERS string?
Thanks
Andrew
register values into LED mode
> select and behavior.
There was been some work done allowing PHY LEDs to be controlled just
like other LEDs in Linux. That is how this should be done. Please go
look back in the netdev and LED mailing list archives, and join that
work.
Andrew
obe_capabilities = MDIOBUS_C22_C45;
It looks like this needs to be conditional on the version. xgmax2
supports C45. And gmac4. But other versions don't.
Andrew
On Wed, Dec 09, 2020 at 09:39:38PM +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
Reviewed-by: Andrew Lunn
Andrew
the start of the buffer. If that happens before the DMA operation, and
you don't invalidate the cache correctly, you get hard to find
corruption.
Andrew
801 - 900 of 40832 matches
Mail list logo
