This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross
---
.../devicetree
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch
On Thu, Jan 22, 2015 at 12:34:26PM +0530, Archit Taneja wrote:
> Add register offset table entry for the newer (v1.7.0) version of the BAM IP
> found on MSM8916. Update the DT bindings documentation.
>
> Signed-off-by: Archit Taneja
> ---
Looks good.
Reviewed-by: Andy Gross
On Wed, Jan 21, 2015 at 08:46:45PM -0800, Joe Perches wrote:
> > +L: linux-...@vger.kernel.org
> > S: Maintained
> > F: arch/arm/mach-qcom/
> > +F: drivers/soc/qcom
>
> Please add a terminating /
>
> F:drivers/soc/qcom/
Noted, will fix.
--
Qualcomm Innovation Center, Inc.
The Qualcomm In
On Thu, Jan 22, 2015 at 10:59:14AM -0800, Jack Pham wrote:
> Hi Andy,
>
> On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
> > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
> > some
> > Qualcomm platforms. This driver uses the gen
Added myself as a co-maintainer. Updated the files to include the Qualcomm SoC
directory. Added linux-soc mailing list.
Signed-off-by: Andy Gross
---
MAINTAINERS |3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93409ad..2af6e23 100644
--- a/MAINTAINERS
On Wed, Oct 15, 2014 at 10:18:30AM +0200, Kumar Gala wrote:
>
> On Oct 1, 2014, at 4:41 PM, Arnd Bergmann wrote:
>
> > On Monday 22 September 2014, Kumar Gala wrote:
> >> The following changes since commit
> >> 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9:
> >>
> >> Linux 3.17-rc1 (2014-08-16 10:
On Fri, Jan 09, 2015 at 01:06:56AM +0100, Arnd Bergmann wrote:
> On Thursday 08 January 2015 16:52:56 Andy Gross wrote:
> > This patch adds support for the TCSR (Top Control and Status Register) IP
> > block
> > that is present in the Qualcomm IPQ8064, APQ8064, and some later
On Thu, Jan 08, 2015 at 03:39:44PM -0800, Stephen Boyd wrote:
> On 01/08/2015 02:52 PM, Andy Gross wrote:
> > +
> > +static struct platform_driver qcom_tcsr_driver = {
> > + .driver = {
> > + .name = "tcsr",
> > + .owner
On Fri, Jan 09, 2015 at 10:08:20AM +0530, Archit Taneja wrote:
> Hi,
>
> On 01/08/2015 08:56 AM, Andy Gross wrote:
> >Signed-off-by: Andy Gross
>
>
> >+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan
> >*chan,
> >+struc
controller.
Signed-off-by: Andy Gross
---
drivers/soc/qcom/Kconfig |7
drivers/soc/qcom/Makefile|1 +
drivers/soc/qcom/qcom_tcsr.c | 83 ++
include/soc/qcom/qcom_tcsr.h | 21 +++
4 files changed, 112 insertions(+)
create mode
configuration settings for the USB
PHY selection and ADM DMA CRCI muxing.
Andy Gross (2):
soc: qcom: Add TCSR driver
soc: qcom: Add device tree binding for TCSR
.../devicetree/bindings/soc/qcom/qcom,tcsr.txt | 33
drivers/soc/qcom/Kconfig |7
Add device tree binding support for the QCOM TCSR driver.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/soc/qcom/qcom,tcsr.txt | 33 +++
include/dt-bindings/soc/qcom,tcsr.h| 34
2 files changed, 67 insertions(+)
create mode
On Thu, Jan 08, 2015 at 11:26:30AM -0500, Christopher Covington wrote:
> > +DMA clients must use the format descripted in the dma.txt file, using a two
> > cell specifier for each channel.
> >
> > Each dmas request consists of 3 cells:
>
> Now 2 cells?
Good catch. I'll fix in next rev. T
On Wed, Jan 07, 2015 at 09:26:11PM -0600, Andy Gross wrote:
I somehow managed to lose my commit message. I'll fix that in the next set.
The rest of the patch is fine.
> Signed-off-by: Andy Gross
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel"
via other means.
Signed-off-by: Andy Gross
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt
b/Documentation/devicetree/bindings/dma/qcom_adm.txt
index
sub burst length transactions.
Selection of single or box descriptors depends on the sg length and burst
size.
- Removed use of crci in the dmas property. CRCI is now designated via the
slave_config structure and will be stored in slave_id.
Andy Gross (2):
dmaengine: Add ADM driveri
Signed-off-by: Andy Gross
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile |1 +
drivers/dma/qcom_adm.c | 899
3 files changed, 910 insertions(+)
create mode 100644 drivers/dma/qcom_adm.c
diff --git a/drivers/dma/Kconfig b
On Fri, Dec 05, 2014 at 12:53:33PM -0800, Stephen Boyd wrote:
> The interrupt is 16, not 32 (which it would be if we include PPIs
> in the count of interrupts).
>
> Cc: Andy Gross
> Signed-off-by: Stephen Boyd
This fixed my issue!
Reviewed-by: Andy Gross
Tested-by: Andy Gross
st
read/write the fifo until you hit the full or empty. You can't do that with
block. you have to read in block size transfers (4x32B read/writes).
>
> On Tue, 2014-09-30 at 16:21 -0500, Andy Gross wrote:
> > This patch fixes a number of errors with the QUP block transfer mode
On Wed, Oct 01, 2014 at 01:52:31PM +0530, Pramod Gurav wrote:
> Andy,
> With your change "dmaengine: qcom_bam_dma: Add v1.3.0 driver support"
> and enabling qcom_bam_dma driver i was seeing some crashes in the kernel
> on IFC6410. But after reverting you change and applying these changes
> from Vin
ed in additional completion check so that transaction done is not
prematurely signaled.
- Fixed various review comments.
Changes from v1:
- Split out read/write block function.
- Removed extraneous checks for transfer length
Signed-off-by: Andy Gross
---
drivers/spi/spi-qup.c |
On Mon, Sep 29, 2014 at 06:53:24PM -0700, Bjorn Andersson wrote:
> On Mon 29 Sep 15:00 PDT 2014, Andy Gross wrote:
>
> > The runtime pm calls need to be done before populating the children via the
> > i2c_add_adapter call. If this is not done, a child can run into issues
&g
On Tue, Sep 30, 2014 at 03:28:00PM +0300, Ivan T. Ivanov wrote:
>
> Hi Andy, just few comments.
>
> On Wed, 2014-09-24 at 16:04 -0500, Andy Gross wrote:
>
>
>
> > +static void spi_qup_fifo_read(struct spi_qup *controller,
> > +
On Mon, Sep 29, 2014 at 10:03:07AM +0530, Archit Taneja wrote:
> The BAM DMA IP comes in different versions. The register offset layout varies
> among these versions. The layouts depend on which generation/family of SoCs
> they
> belong to.
>
> The current SoCs(like 8084, 8074) have a layout wher
The runtime pm calls need to be done before populating the children via the
i2c_add_adapter call. If this is not done, a child can run into issues trying
to do i2c read/writes due to the pm_runtime_sync failing.
Signed-off-by: Andy Gross
---
drivers/i2c/busses/i2c-qup.c | 12
1
d-off-by: Andy Gross
---
drivers/spi/spi-qup.c | 198 -
1 file changed, 146 insertions(+), 52 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 9f83d29..e08cc26 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-
> > + break;
> > + default:
> > + achan->slave.src_maxburst = 0;
> > + achan->slave.dst_maxburst = 0;
> Why clear these for error cases
With the return I shouldn't need to. I'll fix this.
> > + ret = -EINVAL;
> >
On Tue, Sep 23, 2014 at 12:24:27PM +0300, Ivan T. Ivanov wrote:
>
> Hi Andy,
>
> On Sun, 2014-09-21 at 23:27 -0500, Andy Gross wrote:
> > This patch fixes a number of errors with the QUP block transfer mode.
> > Errors
> > manifested themselves as input underru
transfer. Imbalanced acks result in
early return from complete transactions with pending interrupts that still have
to be ack'd. The next transaction can be affected by these interrupts.
Signed-off-by: Andy Gross
---
drivers/spi/spi-qup.c | 194 +++
This patch adds the PLL0 that is required for the USB clocks to work properly.
Changes in v2: Correct table to only use pll0_vote
Signed-off-by: Andy Gross
---
drivers/clk/qcom/gcc-ipq806x.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a
On Tue, Sep 16, 2014 at 11:27:52AM -0700, Jack Pham wrote:
> Hi Andy,
>
> On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
> > +static int qcom_dwc3_hs_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
> > +{
> > + u32 val;
> > +
> > + /*
>
On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
> It also adds necessary DT support for i2c eeprom which is present on
> IFC6410.
>
> Tested on IFC6410 board.
Looks fine
>
> Signed-off-by: Kiran Padwal
> ---
> Ch
This patch adds the PLL0 that is required for the USB clocks to work properly.
Signed-off-by: Andy Gross
---
drivers/clk/qcom/gcc-ipq806x.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
omments for device bindings description
* Fix typo in 'gdsc' requlator name.
Andy Gross (1):
phy: Add Qualcomm DWC3 HS/SS PHY driver
Ivan T. Ivanov (2):
usb: dwc3: qcom: Add device tree binding
usb: dwc3: Add Qualcomm DWC3 glue layer driver
.../devicetree/bindings/phy/qcom-dwc3-u
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile|1
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
On Fri, Sep 12, 2014 at 12:50:23PM -0500, Josh Cartwright wrote:
> Hey Andy-
>
> Mostly cosmetic things below:
>
> On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
> > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
> > some
&g
On Fri, Sep 12, 2014 at 12:47:04PM -0500, Felipe Balbi wrote:
> Hi,
>
> On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
> > From: "Ivan T. Ivanov"
> >
> > DWC3 glue layer is hardware layer around Synopsys DesignWare
> > USB3 core. Its pur
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
ges since v2:
* Several improvements in devicetree bindings description
* Disable regulators in glue layer if there is error during
ioremap.
Changes since first version:
* Split devicetree bindings description file to separate patch
* Address comments for device bindings description
* Fix typo in
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile|1
transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile |1 +
drivers
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 62
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
diff --git a
only support slave DMA operations
between system memory and peripherals. Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM
On Tue, Aug 26, 2014 at 03:45:55PM +0300, Georgi Djakov wrote:
> Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin
> controller inside the APQ8084.
>
> Signed-off-by: Georgi Djakov
Looks fine.
Reviewed-by: Andy Gross
--
sent by an employee of the Qualcom
On Tue, Aug 26, 2014 at 03:45:54PM +0300, Georgi Djakov wrote:
> This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
>
> Signed-off-by: Georgi Djakov
Looks good. I'll try to test this tomorrow, but for now
Reviewed-by: Andy Gross
--
sent by an employee o
On Tue, Aug 19, 2014 at 08:22:14PM +0300, Georgi Djakov wrote:
> This patch adds support for the TLMM (Top-Level Mode Mux) block found
> in the APQ8084 platform.
Comment in-line
> + PINCTRL_PIN(134, "GPIO_134"),
> + PINCTRL_PIN(135, "GPIO_135"),
> + PINCTRL_PIN(136, "GPIO_136"),
> +
On Tue, Aug 19, 2014 at 09:39:30PM -0700, Bjorn Andersson wrote:
> On Tue 19 Aug 10:22 PDT 2014, Georgi Djakov wrote:
>
> > This patch adds support for the TLMM (Top-Level Mode Mux) block found
> > in the APQ8084 platform.
> >
> [...]
> > +
> > +#define NUM_GPIO_PINGROUPS 143
> > +
>
> I think t
This patch adds a MAINTAINERS entry for the SOC Qualcomm drivers.
Signed-off-by: Andy Gross
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aefa948..3ad0a26 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8426,6 +8426,14 @@ F
On Mon, Jul 14, 2014 at 10:06:16PM +0530, Vinod Koul wrote:
> On Fri, May 30, 2014 at 03:49:50PM -0500, Andy Gross wrote:
> > This patch adds support for end of transaction (EOT) and notify when done
> > (NWD)
> > hardware descriptor flags.
> >
> > The EOT
On Thu, Jul 17, 2014 at 06:30:24AM -0400, kiran.pad...@smartplayin.com wrote:
> Hi,
>
> On Mon, Jun 30, 2014 at 9:33 PM, Andy Gross wrote:
> > From: "Ivan T. Ivanov"
> >
> > These drivers handles control and configuration of the HS
> > and SS USB PH
On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
> > +- clock-names: Should contain the following:
> > + "core" Master/Core clock, have to be >= 125 MHz for SS
> > + operation and >= 60MHz for HS operation
> > +
> > +Optional clocks:
> > +
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dw
From: "Ivan T. Ivanov"
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
This work was started by Ivan Ivanov and went through a number of iterations. I
picked these patches up and did a little rework to get them working.
Changes
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off
On Fri, Jun 27, 2014 at 05:24:11PM +0100, Russell King - ARM Linux wrote:
> > > It would be better to use the core DMA mapping code rather than open
> > > coding. This code won't work for vmalloc()ed addresses, or physically
> > > non-contiguous addresses unless there's an IOMMU fixing things u
On Fri, Jun 27, 2014 at 11:50:57AM +0100, Mark Brown wrote:
> On Thu, Jun 26, 2014 at 04:06:21PM -0500, Andy Gross wrote:
>
> > + if (xfer->rx_buf) {
> > + rx_dma = dma_map_single(controller->dev, xfer->rx_buf,
> > + xfer->len
This patch adds DMA capabilities to the spi-qup driver. If DMA channels are
present, the QUP will use DMA instead of block mode for transfers to/from SPI
peripherals for transactions larger than the length of a block.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/spi/qcom,spi-qup.txt
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 60
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
diff --git a
(client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM ADM DMA driver
dmaengine: qcom_adm: Add device tree binding
Documentation/devicetree/bindings/dma
transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile |1 +
drivers
On Sat, Jun 21, 2014 at 11:13:03AM +0100, Mark Brown wrote:
> On Thu, Jun 12, 2014 at 02:34:10PM -0500, Andy Gross wrote:
> > This patch removes the chip select function. Chip select should instead be
> > supported using GPIOs, defining the DT entry "cs-gpios", and lettin
This patch adds the BUS_HOLD (Keeper) bias option for pins.
Signed-off-by: Andy Gross
---
drivers/pinctrl/pinctrl-msm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index e43fbce..9aa2839 100644
--- a/drivers/pinctrl
On Tue, Jun 10, 2014 at 11:25:23AM -0700, Bjorn Andersson wrote:
In general, it all looks good. I only have 2 areas of concern. The first is a
nit and it has to do with alternate pins for functions. There really isn't a
need for a separate function name. That would only be required if the same
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross
Acked-by: Ivan T. Ivanov
---
drivers/spi/spi-qup.c | 11
s (APQ8064, IPQ8064, and MSM8960).
Andy Gross (3):
spi: qup: Remove chip select function
spi: qup: Fix order of spi_register_master
spi: qup: Add support for v1.1.1
.../devicetree/bindings/spi/qcom,spi-qup.txt | 12 ++-
drivers/spi/spi-qup.c
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++-
drivers/spi/spi-qup.c | 36
2 files changed, 27 insertions(+), 15 deletions(-)
diff
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry "cs-gpios", and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/spi/qcom,spi-qup.txt
On Mon, May 19, 2014 at 11:07:38AM +0300, Ivan T. Ivanov wrote:
> > +- num-cs: total number of chipselects
>
> My understanding is that "num-cs" have to be parsed by
> master driver, not by core SPI driver.
Right. I need to parse it and check vs the max cs and use that value to set the
maste
DMA_PREP_FENCE to enable this flag.
Signed-off-by: Andy Gross
---
drivers/dma/qcom_bam_dma.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index e01c2d106..4635224 100644
--- a/drivers/dma/qcom_bam_dma.c
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
> >
> >The EOT is not used for every transaction. It is part of a handshaking
> >protocol with the attached peripheral, much like the NWD (notify when done).
> > As
> >near as I can tell today, no peripheral depends on the EO
On Thu, May 22, 2014 at 11:40:49AM +0530, Vinod Koul wrote:
> > > I have 3 different IRQs that can be asserted based on the bit I set in the
> > > hardware descriptor. The normal IRQ is the INT bit. However, in some
> > > cases the
> > > peripheral protocol requires the use of the EOT or EOB
On Fri, May 02, 2014 at 01:08:27PM -0500, Andy Gross wrote:
> On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
> > On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
> > > This patch adds APIs that allow for BAM hardware flags to be set per
> > > d
On Tue, May 13, 2014 at 03:08:45PM -0700, Stephen Boyd wrote:
> On 05/13, Andy Gross wrote:
> > @@ -488,7 +491,7 @@ static int spi_qup_probe(struct platform_device *pdev)
> > struct resource *res;
> > struct device *dev;
> > void __iomem *base;
> &g
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross
---
drivers/spi/spi-qup.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index b518b51..abad630 100644
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross
---
drivers/spi/spi-qup.c | 11 +++
1 file changed, 7
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry "cs-gpios", and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/spi/qcom,spi-qup.txt
This patch fixes the calculation for determining whether to use FIFO or BLOCK
mode.
Signed-off-by: Andy Gross
---
drivers/spi/spi-qup.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index ea7017b..57b65e9 100644
--- a
eeds to be called after the runtime
pm is initialized.
The last patch adds support for V1.1.1 of the QUP. This version of the
controller is present in earlier devices (APQ8064, IPQ8064, and MSM8960).
Andy Gross (4):
spi: qup: Remove chip select function
spi: qup: Correct selection of FIFO/
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer,
cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins.
Signed-off-by: Andy Gross
---
.../bindings/pinctrl/qcom,msm8974
On Fri, May 09, 2014 at 01:08:25PM -0500, Kumar Gala wrote:
> Drop underscore in spdif_groups to match all other groups.
>
> Signed-off-by: Kumar Gala
Reviewed-by: Andy Gross
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross
---
.../bindings
On Fri, May 09, 2014 at 10:37:00AM +0200, Linus Walleij wrote:
> On Fri, May 2, 2014 at 6:44 AM, Andy Gross wrote:
>
> > This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
> > include:
> >
> > BLSP devices (I2C, UART, UART flow control, SPI, an
This patch corrects the error check on the call to pm_runtime_get_sync.
Signed-off-by: Andy Gross
---
drivers/i2c/busses/i2c-qup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 1b4cf14..2a5efb5 100644
--- a
On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
> On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
> > This patch adds APIs that allow for BAM hardware flags to be set per
> > descriptor. Each one of the new flags informs the attached peripheral of a
>
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross
---
.../bindings
Fix copy/paste error in pinctrl_pin_desc for pin 0.
Signed-off-by: Andy Gross
---
drivers/pinctrl/pinctrl-ipq8064.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c
b/drivers/pinctrl/pinctrl-ipq8064.c
index 1700b49..54aba9f 100644
--- a
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross
---
drivers/tty/serial/msm_serial.c | 48 ++-
drivers/tty/serial/msm_serial.h |5
2 files changed
mode setting for the ports and keep the children
from accessing the GSBI directly.
Changes from v1:
- Add dt-bindings file containing definitions for MUX values
- Fix code comments
- Removed unnecessary code
Andy Gross (4):
soc: Placeholder files for drivers/soc
soc: qcom
Add placeholder Kconfig and linkage for driver/soc.
The first patch set that implemented this was authored by Santosh Shilimkar:
https://lkml.org/lkml/2014/2/28/567
Signed-off-by: Andy Gross
---
drivers/Kconfig |2 ++
drivers/Makefile|4
drivers/soc/Kconfig |4
3
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
include/dt-bindings/soc/qcom,gsbi.h| 26 +++
2 files changed, 104 insertions(+)
create mode 100644
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross
---
drivers
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
> > +
> > +struct gsbi_dev {
> > + struct device *dev;
> > + void __iomem*base;
>
> You don't really need these.
Old habits die hard. I'll remove.
> > + if (of_property_read_u32(node, "qcom,mode", &mode)) {
> > +
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