Hi, Viresh
> On 09-07-19, 15:10, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > With property "opp-supported-hw" introduced, the OPP table in DT could
> > be a large OPP table and ONLY a subset of OPPs are available, based on
> > the version
n DT could be NOT
> > > supported according to speed garding and market segment fuse settings.
> > > So we can assign the cpufreq policy's suspend_freq with max
> > > available frequency provided by cpufreq driver.
> > >
> > > Signed-off-by: Anson Huang
>
From: Anson Huang
With property "opp-supported-hw" introduced, the OPP table
in DT could be a large OPP table and ONLY a subset of OPPs
are available, based on the version of the hardware running
on. That introduces restriction of using "opp-suspend"
property to define th
From: Anson Huang
Add opp-suspend property to each OPP, the of opp core will
select the OPP HW supported and with highest rate to be
suspend opp, it will speed up the suspend/resume process.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 +++
1 file changed, 3
From: Anson Huang
Add opp-suspend property to each OPP, the of opp core will
select the OPP HW supported and with highest rate to be
suspend opp, it will speed up the suspend/resume process.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4
1 file changed, 4
Hi, Viresh
> On 08-07-19, 08:54, Anson Huang wrote:
> > Each OPP has "opp-supported-hw" property as below, the first value
> > needs to be checked with speed grading fuse, and the second one needs
> > to be checked with market segment fuse, ONLY both of them passed,
be NOT
> > supported according to speed garding and market segment fuse settings.
> > So we can assign the cpufreq policy's suspend_freq with max available
> > frequency provided by cpufreq driver.
> >
> > Signed-off-by: Anson Huang
>
> > diff --git a/d
Hi, Viresh
> On 08-07-19, 08:43, Anson Huang wrote:
> > Hi, Viresh
> >
> > > On 04-07-19, 07:49, Leonard Crestez wrote:
> > > > On 7/4/2019 9:23 AM, anson.hu...@nxp.com wrote:
> > > > > From: Anson Huang
> > > > >
&g
Hi, Viresh
> On 04-07-19, 07:49, Leonard Crestez wrote:
> > On 7/4/2019 9:23 AM, anson.hu...@nxp.com wrote:
> > > From: Anson Huang
> > >
> > > Assign highest OPP as suspend OPP to reduce suspend/resume latency
> > > on i.MX8MM.
> > >
&g
From: Anson Huang
To reduce the suspend/resume latency, CPU's max supported frequency
should be used during low level suspend/resume phase, "opp-suspend"
property is NOT feasible since OPP defined in DT could be NOT supported
according to speed garding and market segment fuse settings.
Hi, Leonard
> > On 7/4/2019 9:23 AM, anson.hu...@nxp.com wrote:
> > > From: Anson Huang
> > >
> > > Assign highest OPP as suspend OPP to reduce suspend/resume latency
> > > on i.MX8MM.
> > >
> > > Signed-off-by: Anson Huang
>
From: Anson Huang
i.MX8MN is a new SoC of i.MX8M series, it also uses speed
grading and market segment fuses for OPP definitions, add
support for this SoC.
Signed-off-by: Anson Huang
---
drivers/cpufreq/imx-cpufreq-dt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's src driver, add "fsl,imx8mq-src" as
src's fallback compatible to enable it.
Signed-off-by: Anson Huang
Reviewed-by: Philipp Zabel
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+),
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang
---
Changes since V3:
- Add comments to those reset indices to indicate which are NOT
supported on i.MX8MM.
---
.../devicetree
Hi, Philipp
> On Fri, 2019-07-05 at 00:26 +0000, Anson Huang wrote:
> > Hi, Philipp
> >
> > > On Thu, 2019-07-04 at 17:44 +0800, anson.hu...@nxp.com wrote:
> > > > From: Anson Huang
> > > >
> > > > i.MX8MM can reuse i.MX8MQ's reset dri
From: Anson Huang
Use devm_platform_ioremap_resource() instead of of_iomap() to
save the iounmap() call in error handle path;
Signed-off-by: Anson Huang
---
drivers/thermal/qoriq_thermal.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/thermal
From: Anson Huang
Use __maybe_unused for power management related functions
instead of #if CONFIG_PM_SLEEP to simply the code.
Signed-off-by: Anson Huang
---
drivers/thermal/qoriq_thermal.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal
From: Anson Huang
i.MX8MQ has clock gate for TMU module, add clock info to TMU
node for clock management.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot
From: Anson Huang
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
should manage this clock, so no need to have CLK_IS_CRITICAL flag
set.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk
From: Anson Huang
Some platforms like i.MX8MQ has clock control for this module,
need to add clock operations to make sure the driver is working
properly.
Signed-off-by: Anson Huang
---
drivers/thermal/qoriq_thermal.c | 24
1 file changed, 24 insertions(+)
diff --git
From: Anson Huang
Some platforms have clock control for TMU, add optional
clocks property to the binding doc.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
Hi, Philipp
> On Thu, 2019-07-04 at 17:44 +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
> > property and related info to support i.MX8MM.
> >
> > Signed-off-by: An
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's src driver, add "fsl,imx8mq-src" as
src's fallback compatible to enable it.
Signed-off-by: Anson Huang
Reviewed-by: Philipp Zabel
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+),
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang
---
Changes since V2:
- Add separate line for i.MX8MM in case anything different later for
i.MX8MM.
---
Documentation/devicetree
Hi, Philipp
> On Thu, 2019-07-04 at 17:25 +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
> > property and related info to support i.MX8MM.
> >
> > Signed-off
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang
---
New patch.
---
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's src driver, add "fsl,imx8mq-src" as
src's fallback compatible to enable it.
Signed-off-by: Anson Huang
Reviewed-by: Philipp Zabel
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+),
From: Anson Huang
Enable CONFIG_IMX8MM_THERMAL as module to support i.MX8MM
thermal driver.
Signed-off-by: Anson Huang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 126665f..eeedd3f 100644
From: Anson Huang
i.MX8MM has a thermal monitoring unit(TMU) inside, it ONLY has one
sensor for CPU, add support for reading immediate temperature of
this sensor.
Signed-off-by: Anson Huang
---
drivers/thermal/Kconfig | 10 +++
drivers/thermal/Makefile | 1 +
drivers
From: Anson Huang
Add thermal zone and tmu node to support i.MX8MM thermal
driver, ONLY cpu thermal zone is supported, and cpu cooling
is also added.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 43 +++
1 file changed, 43 insertions
From: Anson Huang
Add thermal binding doc for Freescale's i.MX8MM Thermal Monitoring Unit.
Signed-off-by: Anson Huang
---
.../devicetree/bindings/thermal/imx8mm-thermal.txt| 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings
From: Anson Huang
i.MX8MM has a thermal monitor unit (TMU) inside, it ONLY has one sensor
for CPU, add support for temperature reading for CPU, cpu cooling is
also added.
This patch series is based on below i.MX SCU thermal patch series:
https://patchwork.kernel.org/patch/11000821/
Anson Huang
Hi, Philipp
> On Mon, 2019-07-01 at 17:39 +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > i.MX8MM SoC has a subset of i.MX8MQ IP block variant, it can reuse the
> > i.MX8MQ reset controller driver and just skip those non-existing IP
> > blocks,
Hi, Leonard
> On 7/4/2019 9:23 AM, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Assign highest OPP as suspend OPP to reduce suspend/resume latency on
> > i.MX8MM.
> >
> > Signed-off-by: Anson Huang
> > ---
> > arch/arm64/boot/dts/
From: Anson Huang
Assign highest OPP as suspend OPP to reduce suspend/resume
latency on i.MX8MM.
Signed-off-by: Anson Huang
---
This patch is based on https://patchwork.kernel.org/patch/11023813/
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Anson Huang
Assign highest OPP as suspend OPP to reduce suspend/resume
latency on i.MX8MQ.
Signed-off-by: Anson Huang
---
This patch is based on https://patchwork.kernel.org/patch/11023815/
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi, Daniel
> On 02/07/2019 11:03, Anson Huang wrote:
> > Hi, Daniel
> >
> >> Hi Anson,
> >>
> >> why did you resend the series?
> >
> > Previous patch series has build warning and I did NOT notice, sorry
> > for that,
> &
y for mail storm...
Thanks,
Anson
>
>
> On 02/07/2019 09:55, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > More and more platforms use platform driver model for clock driver, so
> > the clock driver is NOT ready during timer initialization phase, it
&g
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always
From: Anson Huang
More and more platforms use platform driver model for clock driver,
so the clock driver is NOT ready during timer initialization phase,
it will cause timer initialization failed.
To support those platforms with upper scenario, introducing a new
flag TIMER_OF_CLOCK_FREQUENCY
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
From: Anson Huang
Systems which use platform driver model for clock driver require the
clock frequency to be supplied via device tree when system counter
driver is enabled.
This is necessary as in the platform driver model the of_clk operations
do not work correctly because system counter
From: Anson Huang
Add i.MX SCU SoC's UID(unique identifier) support, user
can read it from sysfs:
root@imx8qxpmek:~# cat /sys/devices/soc0/soc_uid
7B64280B57AC1898
Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
---
Change since V2:
- The SCU FW API for getting UID does
Hi, Marco
> > > + hdr->ver = IMX_SC_RPC_VERSION;
> > > + hdr->svc = IMX_SC_RPC_SVC_MISC;
> > > + hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID;
> > > + hdr->size = 1;
> > > +
> > > + /*
> > > + * SCU FW API always returns an error even the
> > > + * function is successfully executed, so skip
> > > +
Hi, Marco
> > + hdr->ver = IMX_SC_RPC_VERSION;
> > + hdr->svc = IMX_SC_RPC_SVC_MISC;
> > + hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID;
> > + hdr->size = 1;
> > +
> > + /*
> > +* SCU FW API always returns an error even the
> > +* function is successfully executed, so skip
> > +*
Hi, Marco
> Hi Anson,
>
> On 19-06-27 07:01, Anson Huang wrote:
> > Hi, Daniel
> >
> > > On Thu, Jun 27, 2019 at 3:48 AM Anson Huang
> > > wrote:
> > > >
> > > > Hi, Daniel
> > > >
> > > &g
From: Anson Huang
Add "gpio-ranges" property to establish connections between GPIOs
and PINs on i.MX8MQ pinctrl driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/i
From: Anson Huang
Add "gpio-ranges" property to establish connections between GPIOs
and PINs on i.MX8MM pinctrl driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/i
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's src driver, add "fsl,imx8mq-src" as
src's fallback compatible to enable it.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts
From: Anson Huang
i.MX8MM SoC has a subset of i.MX8MQ IP block variant, it can reuse
the i.MX8MQ reset controller driver and just skip those non-existing
IP blocks, add support for i.MX8MM SoC reset control.
Signed-off-by: Anson Huang
---
drivers/reset/reset-imx7.c | 20
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
From: Anson Huang
Systems which use platform driver model for clock driver require the
clock frequency to be supplied via device tree when system counter
driver is enabled.
This is necessary as in the platform driver model the of_clk operations
do not work correctly because system counter
From: Anson Huang
More and more platforms use platform driver model for clock driver,
so the clock driver is NOT ready during timer initialization phase,
it will cause timer initialization failed.
To support those platforms with upper scenario, introducing a new
flag TIMER_OF_CLOCK_FREQUENCY
Hi, Daniel
> Subject: Re: [PATCH V3 1/5] clocksource: timer-of: Support getting clock
> frequency from DT
>
>
> Hi Anson,
>
> thanks for taking care of adding the clock-frequency handling in the timer-of.
Sure.
>
> On 28/06/2019 05:30, anson.hu...@nxp.com w
From: Anson Huang
According to latest datasheet (Rev.0.2, 04/2019) from below links,
1.8GHz is ONLY available for consumer part, so the market segment
bits for 1.8GHz opp should ONLY available for consumer part accordingly.
https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
https
From: Anson Huang
According to latest datasheet (Rev.1, 10/2018) from below links,
in the consumer datasheet, 1.5GHz is mentioned as highest opp but
depends on speed grading fuse, and in the industrial datasheet,
1.3GHz is mentioned as highest opp but depends on speed grading
fuse. 1.5GHz
> -Original Message-
> From: Leonard Crestez
> Sent: Friday, June 28, 2019 2:45 PM
> To: Anson Huang ; Jacky Bai ;
> l.st...@pengutronix.de
> Cc: shawn...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> s.ha...@pengutronix.de; ker...@pengutronix.d
Hi, Leonard
> -Original Message-
> From: Leonard Crestez
> Sent: Friday, June 28, 2019 2:01 PM
> To: Anson Huang ; Jacky Bai ;
> l.st...@pengutronix.de
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.d
Hi, Leonard
> -Original Message-
> From: Leonard Crestez
> Sent: Friday, June 28, 2019 1:59 PM
> To: Anson Huang ; shawn...@kernel.org; Jacky
> Bai ; l.st...@pengutronix.de
> Cc: robh...@kernel.org; mark.rutl...@arm.com; s.ha...@pengutronix.de;
> ker...@pengutronix.d
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always
From: Anson Huang
More and more platforms use platform driver model for clock driver,
so the clock driver is NOT ready during timer initialization phase,
it will cause timer initialization failed.
To support those platforms with upper scenario, introducing a new
flag TIMER_OF_CLOCK_FREQUENCY
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
New patch:
- As i.MX8MM clock driver will be soon moved to using platform driver
model, so the patch
series I sent out for i.MX8MM system
From: Anson Huang
Systems which use platform driver model for clock driver require the
clock frequency to be supplied via device tree when system counter
driver is enabled.
This is necessary as in the platform driver model the of_clk operations
do not work correctly because system counter
From: Anson Huang
According to latest datasheet (Rev.1, 10/2018) from below links,
in the consumer datasheet, 1.5GHz is mentioned as highest opp but
depends on speed grading fuse, and in the industrial datasheet,
1.3GHz is mentioned as highest opp but depends on speed grading
fuse. 1.5GHz
From: Anson Huang
According to latest datasheet (Rev.0.2, 04/2019) from below links,
1.8GHz is ONLY available for consumer part, so the market segment
bits for 1.8GHz opp should ONLY available for consumer part accordingly.
https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
https
From: Anson Huang
Add i.MX SCU SoC's UID(unique identifier) support, user
can read it from sysfs:
root@imx8qxpmek:~# cat /sys/devices/soc0/soc_uid
7B64280B57AC1898
Signed-off-by: Anson Huang
---
Changes since V1:
- Improve the comment of skipping SCFW API return value check
Hi, Daniel
> On 23/06/2019 14:38, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Systems which use platform driver model for clock driver require the
> > clock frequency to be supplied via device tree when system counter
> > driver is e
Hi, Daniel
> On 23/06/2019 14:38, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > On some i.MX8M platforms, clock driver uses platform driver model and
> > it is NOT ready during timer initialization phase, the clock
> > operations will fail and sy
Hi, Daniel
> On 27/06/2019 02:43, Anson Huang wrote:
> > Hi, Daniel
> >
> >> On 26/06/2019 03:42, Anson Huang wrote:
> >>> Hi, Daniel
> >>>
> >>>> On 23/06/2019 14:38, anson.hu...@nxp.com wrote:
> >>>>> From: Anso
Hi, Daniel
> -Original Message-
> From: Daniel Baluta
> Sent: Thursday, June 27, 2019 2:44 PM
> To: Anson Huang
> Cc: Shawn Guo ; Sascha Hauer
> ; Pengutronix Kernel Team
> ; Fabio Estevam ; Aisheng
> Dong ; Abel Vesa ; linux-
> arm-kernel ; Linux Kernel Ma
Hi, Daniel
> -Original Message-
> From: Daniel Baluta
> Sent: Wednesday, June 26, 2019 8:42 PM
> To: Anson Huang
> Cc: Shawn Guo ; Sascha Hauer
> ; Pengutronix Kernel Team
> ; Fabio Estevam ; Aisheng
> Dong ; Abel Vesa ; linux-
> arm-kernel ; Linux Kernel Ma
Hi, Daniel
> On 26/06/2019 03:42, Anson Huang wrote:
> > Hi, Daniel
> >
> >> On 23/06/2019 14:38, anson.hu...@nxp.com wrote:
> >>> From: Anson Huang
> >>>
> >>> Systems which use platform driver model for clock driver require the
>
From: Anson Huang
Add i.MX8MM SoC UID(unique identifier) support, user
can read it from sysfs:
root@imx8mmevk:~# cat /sys/devices/soc0/soc_uid
B365FA0A5C85D6EE
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 23 +++
1 file changed, 23 insertions(+)
diff --git
From: Anson Huang
Add i.MX8MQ SoC UID(unique identifier) support, user
can read it from sysfs:
root@imx8mqevk:~# cat /sys/devices/soc0/soc_uid
D56911D6F060954B
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Anson Huang
Add i.MX SCU SoC's UID(unique identifier) support, user
can read it from sysfs:
root@imx8qxpmek:~# cat /sys/devices/soc0/soc_uid
7B64280B57AC1898
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx-scu.c | 35 +++
1 file changed, 35
Hi, Daniel
> On 23/06/2019 14:38, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Systems which use platform driver model for clock driver require the
> > clock frequency to be supplied via device tree when system counter
> > driver is e
Hi, Stephen
> Quoting anson.hu...@nxp.com (2019-06-25 00:06:02)
> > From: Anson Huang
> >
> > i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> > sys_pll1_800m, correct it.
> >
> > Signed-off-by: Anson Huang
>
> Any Fixes tags?
From: Anson Huang
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4
should be sys_pll3_out, sys3_pll2_out is a typo, fix it.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file
From: Anson Huang
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file changed, 1 insertion(+),
From: Anson Huang
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk
From: Anson Huang
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4
should be sys_pll3_out, sys3_pll2_out is a typo, fix it.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Monday, June 24, 2019 10:27 AM
> To: Anson Huang
> Cc: mark.rutl...@arm.com; Aisheng Dong ; Peng
> Fan ; feste...@gmail.com; Jacky Bai
> ; devicet...@vger.kernel.org; sb...@kernel.org;
> catal
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Monday, June 24, 2019 10:22 AM
> To: Anson Huang
> Cc: catalin.mari...@arm.com; w...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste.
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No change.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b
From: Anson Huang
Systems which use platform driver model for clock driver require the
clock frequency to be supplied via device tree when system counter
driver is enabled.
This is necessary as in the platform driver model the of_clk operations
do not work correctly because system counter
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always
Hi, Thomas
> On Sun, 23 Jun 2019, anson.hu...@nxp.com wrote:
>
> Again the short summary could be more informative. Instead of 'Add foo'
> you could say:
>
> .: Make timer work with platform driver model
>
> That sums up the real meat of the patch. 'Add some option' is pretty
>
gLvhW7QFFNAXrRqbcTi9%2BJcasgOv08%3Dreserved=0
>
Thanks for these info.
> On Sun, 23 Jun 2019, Anson Huang wrote:
>
> > Hi, Thomas
> > Thanks for the useful comment, I will resend the patch with
> improvement.
> >
> > Anson.
> >
> Also please fix your
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always
From: Anson Huang
Systems which use platform driver model for clock driver require the
clock frequency to be supplied via device tree when system counter
driver is enabled.
This is necessary as in the platform driver model the of_clk operations
do not work correctly because system counter
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No change.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b
Hi, Thomas
Thanks for the useful comment, I will resend the patch with improvement.
Anson.
> -Original Message-
> From: Thomas Gleixner
> Sent: Sunday, June 23, 2019 6:47 PM
> To: Anson Huang
> Cc: daniel.lezc...@linaro.org; robh...@kernel.org; mark.rutl...@a
> -Original Message-
> From: Martin Kepplinger
> Sent: Sunday, June 23, 2019 7:21 PM
> To: Anson Huang ; daniel.lezc...@linaro.org;
> t...@linutronix.de; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
&g
Hi, Martin
> -Original Message-
> From: Martin Kepplinger
> Sent: Saturday, June 22, 2019 10:16 PM
> To: Anson Huang ; daniel.lezc...@linaro.org;
> t...@linutronix.de; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengu
Hi, Martin
> -Original Message-
> From: Martin Kepplinger
> Sent: Saturday, June 22, 2019 8:10 PM
> To: Anson Huang ; catalin.mari...@arm.com;
> w...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengu
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64
801 - 900 of 2669 matches
Mail list logo
