is -e "hisi_mn_2/read_req/"
3. MN PMU doesnot support counter overflow IRQ in HiP05/06/07, So
use hrtimer to poll and avoid counter overflow.
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Dikshit N <dikshi...@huawei.com>
Signed-off-by: A
uot;
3. MN PMU doesnot support counter overflow IRQ in HiP05/06/07, So
use hrtimer to poll and avoid counter overflow.
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 87
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 87
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
6. L3C PMU in HiP05/06/07 does not support counter overflow IRQ. So hrtimer
is used to poll and avoid overflow.
Signed-off-by: Anurup M <an
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..4a95977 100644
--- a/MAINTAINERS
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
6. L3C PMU in HiP05/06/07 does not support counter overflow IRQ. So hrtimer
is used to poll and avoid overflow.
Signed-off-by: Anurup M
Signed
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 684
drivers/perf/hisilicon/djtag.h | 47 +++
4 files changed, 733 insertions(+)
create mode
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisi
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 9365190..248d730 100644
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 29 +++
.../devicetree
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (6):
arm64
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (6):
arm64
On Friday 31 March 2017 07:53 PM, Mark Rutland wrote:
On Fri, Mar 31, 2017 at 07:43:20PM +0530, Anurup M wrote:
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
+* We must NOT create groups containing mixed PMUs, although
+* software events are acceptable
On Friday 31 March 2017 07:53 PM, Mark Rutland wrote:
On Fri, Mar 31, 2017 at 07:43:20PM +0530, Anurup M wrote:
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
+* We must NOT create groups containing mixed PMUs, although
+* software events are acceptable
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
> >>>+ * We must NOT create groups containing mixed PMUs, although
> >>>+ * software events are acceptable
> >>>+ */
> >>>+ if (event->group_leader->pmu != event->pmu &&
> >>>+
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
> >>>+ * We must NOT create groups containing mixed PMUs, although
> >>>+ * software events are acceptable
> >>>+ */
> >>>+ if (event->group_leader->pmu != event->pmu &&
> >>>+
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
+static int hisi_hw_perf_event_init(struct perf_event *event)
>+{
>+ struct hw_perf_event *hwc = >hw;
>+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
>+ struct device *dev = hisi_pmu->dev;
+
>+ /*
>+* We must NOT
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
+static int hisi_hw_perf_event_init(struct perf_event *event)
>+{
>+ struct hw_perf_event *hwc = >hw;
>+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
>+ struct device *dev = hisi_pmu->dev;
+
>+ /*
>+* We must NOT
On Friday 24 March 2017 05:06 PM, Mark Rutland wrote:
+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value chosen?
> >
> >How likely is a timeout?
>
>As explained in PATCH 7,
>
>The djtag -EBUSY in hardware is a very rare scenario, and by design
>of
On Friday 24 March 2017 05:06 PM, Mark Rutland wrote:
+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value chosen?
> >
> >How likely is a timeout?
>
>As explained in PATCH 7,
>
>The djtag -EBUSY in hardware is a very rare scenario, and by design
>of
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
How do we ensure that we don't take the interrupt in the middle of a
> >sequence of accesses to the HW?
>
>The L3 cache and MN PMU does not use the overflow IRQ and it does
>not occur here
>as the interrupt Mask register is by default
On Friday 24 March 2017 05:27 PM, Mark Rutland wrote:
+/* hip05/06 chips L3C bank identifier */
>+static u32 l3c_bankid_map_v1[MAX_BANKS] = {
>+0x02, 0x04, 0x01, 0x08,
>+};
>+
>+/* hip07 chip L3C bank identifier */
>+static u32 l3c_bankid_map_v2[MAX_BANKS] = {
>+0x01, 0x02, 0x03, 0x04,
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
How do we ensure that we don't take the interrupt in the middle of a
> >sequence of accesses to the HW?
>
>The L3 cache and MN PMU does not use the overflow IRQ and it does
>not occur here
>as the interrupt Mask register is by default
On Friday 24 March 2017 05:27 PM, Mark Rutland wrote:
+/* hip05/06 chips L3C bank identifier */
>+static u32 l3c_bankid_map_v1[MAX_BANKS] = {
>+0x02, 0x04, 0x01, 0x08,
>+};
>+
>+/* hip07 chip L3C bank identifier */
>+static u32 l3c_bankid_map_v2[MAX_BANKS] = {
>+0x01, 0x02, 0x03, 0x04,
Thanks for the review.
On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
From: Tan Xiaojun <tanxiao...@huawei.com>
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Deb
Thanks for the review.
On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can
On Tuesday 21 March 2017 10:58 PM, Mark Rutland wrote:
On Tue, Mar 21, 2017 at 02:07:42PM +, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:27:27AM -0500, Anurup M wrote:
+HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
+is called as Super CPU cluster (SCCL
On Tuesday 21 March 2017 10:58 PM, Mark Rutland wrote:
On Tue, Mar 21, 2017 at 02:07:42PM +, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:27:27AM -0500, Anurup M wrote:
+HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
+is called as Super CPU cluster (SCCL
Thanks for the review.
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:31AM -0500, Anurup M wrote:
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
Nit: s/PMU's/PMUs/
Ok.
[...]
+struct hisi_l3c_hwcfg {
+ u32 module_id
Thanks for the review.
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:31AM -0500, Anurup M wrote:
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
Nit: s/PMU's/PMUs/
Ok.
[...]
+struct hisi_l3c_hwcfg {
+ u32 module_id
On Tuesday 21 March 2017 10:47 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:29:01AM -0500, Anurup M wrote:
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer
On Tuesday 21 March 2017 10:47 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:29:01AM -0500, Anurup M wrote:
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer
On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote:
Add hrtimer support which use poll method to avoid counter overflow
when overflow IRQ is not supported in hardware.
The L3 cache PMU use N-N SPI interrupt which has no support
On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote:
Add hrtimer support which use poll method to avoid counter overflow
when overflow IRQ is not supported in hardware.
The L3 cache PMU use N-N SPI interrupt which has no support
Thanks for the review.
On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
+HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
Ok. shall recheck and modify
Thanks for the review.
On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
+HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
Ok. shall recheck and modify
Please have a look at this patch series. Looking forward for any
feedback and comments.
Thanks,
Anurup
On Friday 10 March 2017 11:55 AM, Anurup M wrote:
Provide Support for Hisilicon SoC(HiP05/06/07) Hardware event counters.
The Hisilicon SoC HiP0x series has many uncore or non-CPU
Please have a look at this patch series. Looking forward for any
feedback and comments.
Thanks,
Anurup
On Friday 10 March 2017 11:55 AM, Anurup M wrote:
Provide Support for Hisilicon SoC(HiP05/06/07) Hardware event counters.
The Hisilicon SoC HiP0x series has many uncore or non-CPU
is -e "hisi_mn_2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files c
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch
.
An interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N <dikshi...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82 +
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
.
An interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Ga
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 42 +++
4 files changed, 817 insertions(+)
create mode
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 1e95d6a..f0aa818 100644
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisi
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Acked-by: Ro
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..c2f9806 100644
--- a/MAINTAINERS
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..c2f9806 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5958,6
counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting
counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting
On Friday 03 March 2017 12:20 PM, Rob Herring wrote:
On Thu, Mar 02, 2017 at 05:48:36AM -0500, Anurup M wrote:
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-
On Friday 03 March 2017 12:20 PM, Rob Herring wrote:
On Thu, Mar 02, 2017 at 05:48:36AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisi
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
is -e "hisi_mn_2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files c
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M <anuru...@huawei.com>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +++
.../devicetree
is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi
is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi
.
An interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N <dikshi...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82 +
.
An interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Ga
ed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 771
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 813 insertions(+)
create mode
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
From: Tan Xiaojun <tanxiao...@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
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