e populated via
DT. Now that we also support creating devices manually, we could end up
in a situation where a driver tries to create a device with a virtual
channel already taken by a device populated in DT.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 26 +++
device_new as a standalone way to create
a dsi device not available via DT.
The new device creation process tries to closely follow what's been done
in i2c_new_device in i2c-core.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 61 +--
pi) perform a non-DT match by comparing the
device name and entries in the driver's id_table. The id_table structs
for different buses are defined in "include/linux/mod_devicetable.h", I
didn't want to touch that for now.
Signed-off-by: Archit Taneja
list of all the hosts DSI that are currently registered.
This list will be used to find the mipi_dsi_host corresponding to the
device_node passed in of_find_mipi_dsi_host_by_node.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 30 ++
includ
be removed. This does leave
the possibility of the host removing the dsi device without the
peripheral driver being aware of it. I don't know a good way to solve
this. Some suggestions here would be of help too.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 7 +
peripheral driver might have an unregistered device pointer without
being aware of it.
Some comments on these would help.
[1]: https://lkml.org/lkml/2015/6/30/42
Archit Taneja (5):
drm/dsi: Refactor device creation
drm/dsi: Try to match non-DT dsi devices
drm/dsi: Check for used channels
dr
Hi Brian,
Thanks for the review.
On 10/02/2015 08:35 AM, Brian Norris wrote:
Hi Archit,
On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External
On 9/15/2015 3:07 PM, Xinwei Kong wrote:
This patch enables the adv7533 module which is connecting hisilicon SOC
by dsi module. while using DSI module and adv7533 module to implement the
encoder/connector interface of DRM\KMS.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off
Hi,
On 9/15/2015 3:07 PM, Xinwei Kong wrote:
This patch creates this driver itself and register all the sub-components
which is from DTS inode, this driver uses components framework mechanism
to bind all the sub-components.
This patch also introduces a memory manager for hisilison drm. As cma
f
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: David Airlie
Cc: Linus Torvalds
Cc: Peter Zijlstra
Cc: Sudip Mukherjee
Cc: Thomas Gleixner
Cc: dri-devel
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/mgag200/mgag200_fb.c | 31 +++
1 file changed, 23 insertions(+), 8
ng path.
Link: http://lkml.kernel.org/r/55f6e68d.8070...@codeaurora.org
Reported-by: Ingo Molnar
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: David Airlie
Cc: Linus Torvalds
Cc: Peter Zijlstra
Cc: Sudip Mukherjee
Cc: Thomas Gleixner
Cc: dri-devel
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/mgag200
On 9/17/2015 2:04 PM, Ingo Molnar wrote:
* Ingo Molnar wrote:
So this patch was whitespace damaged - I applied it by hand and made the commit
below. This has solved the crash, thanks Archit!
Spoke too soon - the attached (allyesconfig-ish) config still crashes, first
there
are a
On 9/15/2015 9:13 PM, Rob Herring wrote:
On 09/15/2015 05:32 AM, Archit Taneja wrote:
Hi Rob, Mark,
We've been trying to figure out the right way to represent a class
of display encoder devices in DT.
I've been meaning to reply on this.
These devices have registers that are
Hi,
On 09/16/2015 02:04 PM, Xinwei Kong wrote:
hi architt
On 2015/9/16 2:11, Rob Herring wrote:
On 09/15/2015 04:37 AM, Xinwei Kong wrote:
This adds documentation of device tree bindings for the
Graphics Processing Unit of hi6220 SOC.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
the problem. There
were some more nitty gritties discussed in this thread before.
Thierry, Andrzej, Lucas,
Please feel free to add your comments if I have missed out on
something.
Thanks,
Archit
On 09/10/2015 01:02 PM, Thierry Reding wrote:
On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja w
the problem. There
were some more nitty gritties discussed in this thread before.
Thierry, Andrzej, Lucas,
Please feel free to add your comments if I have missed out on
something.
Thanks,
Archit
On 09/10/2015 01:02 PM, Thierry Reding wrote:
On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja w
like it's failing at
register_framebuffer. Is it possible that we never tried running
this driver before with Big Endian set?
The patch below fixes the problem with the error path mentioned
above. Could we try this?
From: Archit Taneja
Date: Mon, 14 Sep 2015 20:11:43 +0530
On 8/27/2015 5:07 AM, Stephen Boyd wrote:
On 08/19, Archit Taneja wrote:
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
and QPIC (Qualcomm Parallel Interface Controller). These IPs
On 09/08/2015 03:57 PM, Andrzej Hajda wrote:
On 09/07/2015 01:46 PM, Archit Taneja wrote:
Thierry,
On 08/21/2015 11:39 AM, Archit Taneja wrote:
On 08/20/2015 05:18 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote:
Hi Thierry, Lucas,
On 08/19/2015
Thierry,
On 08/21/2015 11:39 AM, Archit Taneja wrote:
On 08/20/2015 05:18 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote:
Hi Thierry, Lucas,
On 08/19/2015 08:32 PM, Thierry Reding wrote:
On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote
Hi,
On 9/4/2015 12:00 AM, Hai Li wrote:
Lane swap configuration is based on the board design.
This change allows the DSI host to get this information
from device tree, instead of hardcoding in driver.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++
d
uch prints when the underlying regulator doesn't support DRMS.
Signed-off-by: Archit Taneja
---
drivers/regulator/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 3c3137a..f2262fa 100644
--- a/drivers/re
if (ret < 0) {
Looks good to me.
Reviewed-by: Archit Taneja
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majo
: Archit Taneja
Cc: Archit Taneja
Cc: Hai Li
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 91 +
drivers/clk/qcom/gcc-msm8916.c | 14 +--
drivers/clk/qcom/mmcc-apq8084.c | 18
On 08/20/2015 05:18 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote:
Hi Thierry, Lucas,
On 08/19/2015 08:32 PM, Thierry Reding wrote:
On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote:
Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I
Hi Thierry, Lucas,
On 08/19/2015 08:32 PM, Thierry Reding wrote:
On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote:
Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb Thierry Reding:
On Wed, Aug 19, 2015 at 04:17:08PM +0200, Lucas Stach wrote:
Hi Thierry, Archit,
[...]
Perhaps a b
Hi,
On 08/19/2015 01:40 PM, Andrzej Hajda wrote:
On 06/30/2015 07:24 AM, Archit Taneja wrote:
We can have devices where the data bus is MIPI DSI, but the control bus
is something else (i2c, spi etc). A typical example is i2c controlled
encoder bridge chips.
Such devices too require passing
Hi,
On 06/30/2015 10:54 AM, Archit Taneja wrote:
We are currently restricted when it comes to supporting DSI on devices
that have a non-DSI control bus. For example, DSI encoder chips are
available in the market that are configured via i2c. Configuring their
registers via DSI bus is either
Kconfig
- Misc fixes and clean ups
v2:
- Use new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
drivers/mtd/nand/Kconfig |7 +
drivers/mtd/nand
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicet...@vger.kernel.org
v4:
- No changes
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross
Signed-off-by
-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..648994c 100644
--- a/arch/arm/boot/dts/qcom
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicet...@vger.kernel.org
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --
dy Gross
Signed-off-by: Archit Taneja
---
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 6 +-
include/linux/mtd/bbm.h | 7 +++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca.
atch's changelog.
v3:
- Various fixes and clean ups suggested by Stephen Boyd.
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
v1:
- original series:
https://lkml.org/lkml/2015/1/16/
On 8/4/2015 2:28 AM, Stephen Boyd wrote:
On 08/03, Archit Taneja wrote:
@@ -93,5 +115,19 @@
sata@2900 {
status = "ok";
};
+
+ nand@1ac0 {
+ status = "ok";
+
+
On 8/4/2015 1:05 AM, Andy Gross wrote:
On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064-ap148
On 8/4/2015 5:08 AM, Stephen Boyd wrote:
On 08/03, Archit Taneja wrote:
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
There are some checker errors and le32 usage is not correct:
drivers/mtd/nand/qcom_nandc.c:383:13: warning: mixing different enum types
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicet...@vger.kernel.org
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicet...@vger.kernel.org
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross
Signed-off-by: Archit Taneja
---
.../devicetr
factor and clean ups because of above changes
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
drivers/mtd/nand/Kconfig |7 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/qcom_nandc.c | 1913 +
3 files changed, 1921 insert
dy Gross
Signed-off-by: Archit Taneja
---
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 6 +-
include/linux/mtd/bbm.h | 7 +++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca.
ested by Stephen Boyd.
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
v1:
- original series:
https://lkml.org/lkml/2015/1/16/317
Archit Taneja (5):
mtd: nand: Create a BBT flag to access b
On 7/30/2015 12:03 AM, Stephen Boyd wrote:
On 07/29, Archit Taneja wrote:
On 07/29/2015 07:18 AM, Stephen Boyd wrote:
On 07/27/2015 09:34 PM, Archit Taneja wrote:
Hi,
On 07/25/2015 06:21 AM, Stephen Boyd wrote:
On 07/21/2015 03:34 AM, Archit Taneja wrote:
+ int size
Hi Srini,
On 07/28/2015 06:24 PM, Srinivas Kandagatla wrote:
This patch adds LVDS panel for IFC6410.
Signed-off-by: Rob Clark
[Rob Clark: WIP patch]
Signed-off-by: Srinivas Kandagatla
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 66 ++
1 file changed, 66 ins
On 07/29/2015 07:18 AM, Stephen Boyd wrote:
On 07/27/2015 09:34 PM, Archit Taneja wrote:
Hi,
On 07/25/2015 06:21 AM, Stephen Boyd wrote:
On 07/21/2015 03:34 AM, Archit Taneja wrote:
+ int size)
+{Looks like a
+struct desc_info *desc;
+struct dma_async_tx_descriptor
Hi,
On 07/25/2015 06:21 AM, Stephen Boyd wrote:
On 07/21/2015 03:34 AM, Archit Taneja wrote:
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5b2806a..31951fc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -538,4 +538,11 @@ config MTD_NAND_HISI504
results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Signed-off-by: Archi
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qc
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts
e newly created flag NAND_BBT_ACCESS_BBM_RAW to
read the factory provided bad block markers.
Signed-off-by: Archit Taneja
---
drivers/mtd/nand/Kconfig |7 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/qcom_nandc.c | 2019 +
3 files chan
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree
g/lkml/2015/1/16/317
v2:
- Added a new BBT flag that allows us to read BBM in raw mode
- reduce memcpy-s in the driver
- some refactor and clean ups because of above changes
Archit Taneja (5):
mtd: nand: Create a BBT flag to access bad block markers in raw mode
mtd: nand: Qualcomm NAND contro
Hi,
On 07/14/2015 08:22 AM, Stephen Rothwell wrote:
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/virtio/virtgpu_drm_bus.c: In function
'virtio_pci_kick_out_firmware_fb':
drivers/gpu/drm/virtio/virtgpu_drm_bus.c:55:2
compilation flag and module param ?
I guess this won't be hard to do once we have a common fbdev emulation
config option. We could consider this as a drm top level module param.
I'll keep this in mind.
Thanks,
Archit
Benjamin
2015-06-30 9:56 GMT+02:00 Archit Taneja :
Hi,
On
I
should have something in a week or so. I agree it will help a lot (there
are already two new drivers since we started discussing this!)
Archit
-Daniel
On Wed, Mar 25, 2015 at 10:21 AM, Daniel Vetter wrote:
On Wed, Mar 25, 2015 at 01:47:54PM +0530, Archit Taneja wrote:
Hi,
On 03/13/201
list of all the hosts DSI that are currently registered.
This list will be used to find the mipi_dsi_host corresponding to the
device_node passed in of_find_mipi_dsi_host_by_node.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 30 ++
includ
ing a dummy dsi device. The driver
calling this needs to be aware of the mipi_dsi_host it wants to attach
to, and also the DSI virtual channel the DSI device intends to use.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 78 --
include/drm
I
params, which are passed on to the host via mipi_dsi_attach().
This method will require the device driver to get a phandle to the DSI
host since there is no parent-child relation between the two.
Is there a better way to do this? Please let me know!
Archit Taneja (2):
drm/dsi: Create dummy DS
On 06/26/2015 04:05 AM, Hai Li wrote:
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
Tested-by: Archit Taneja
Signed-off-by: Hai Li
---
drivers
On 06/22/2015 09:30 PM, Srinivas Kandagatla wrote:
On 22/06/15 15:54, Archit Taneja wrote:
Decrement device node refcount if of_get_child_by_name is successfully
called.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
diff
n with device graph usage info.
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 15 ++
drivers/gpu/drm/msm/dsi/dsi_host.c| 64 +--
2 files changed, 63 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetr
We currently get the output connected to LVDS by looking for a phandle
called 'qcom,lvds-panel' under the mdp DT node.
Use the more standard of_graph approach to create an lvds output port,
and retrieve the panel node from the port's endpoint data.
Signed-off-by: Archit Taneja
-
Decrement device node refcount if of_get_child_by_name is successfully
called.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index de04009
.
The usage of device graphs should also simplify management in dual dsi
mode. I haven't tried this out yet, though.
Archit Taneja (3):
drm/msm: dsi host: add missing of_node_put()
drm/msm: dsi host: Use device graph parsing to parse connected panel
drm/msm: mdp4 lvds: get panel node v
ed-by: Archit Taneja
Signed-off-by: Wentao Xu
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 13 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 33 +---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
On 05/22/2015 07:46 PM, Hai Li wrote:
DSI video mode engine can only take active-high sync signals. This
change prevents MDP5 sending active-low sync signals to DSI in any
case.
Signed-off-by: Hai Li
Tested-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 12
Hi,
On 03/17/2015 11:16 AM, Andy Gross wrote:
Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
controller found in the MSM8x60 and IPQ/APQ8064 platforms.
The ADM supports both memory to memory transactions and memory
to/from peripheral device transactions. The controller
Hi,
On 05/06/2015 07:58 PM, Rob Clark wrote:
On Wed, May 6, 2015 at 9:25 AM, Stephane Viau wrote:
When CONFIG_DRM_MSM_FBDEV is not defined,
CONFIG_DRM_KMS_FB_HELPER does not get selected and
drm_fb_helper_*() helper functions are thus not available.
This change fixes these link issues.
Hmm,
On 04/09/2015 02:13 PM, Thierry Reding wrote:
On Thu, Feb 12, 2015 at 02:01:34PM +0800, Liu Ying wrote:
[...]
diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c
b/drivers/gpu/drm/bridge/dw_mipi_dsi.c
[...]
+struct dw_mipi_dsi {
+ struct mipi_dsi_host dsi_host;
+ struct drm_connec
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
Create structs for these clocks so that they can be used by the NAND controller
driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Signed-off-by: Archit Taneja
---
v2:
- removed hwcg_reg
Hi,
On 03/13/2015 02:36 PM, Daniel Vetter wrote:
On Fri, Mar 13, 2015 at 11:55:07AM +0530, Archit Taneja wrote:
On 03/11/2015 08:47 PM, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 01:51:02PM +0530, Archit Taneja wrote:
On 03/10/2015 05:47 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015
On 03/24/2015 03:40 AM, "Stéphane Viau" wrote:
Hi Archit,
Hi Stephane,
On 03/14/2015 01:19 AM, Stephane Viau wrote:
Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of
Hi Hai,
On 03/19/2015 02:35 AM, h...@codeaurora.org wrote:
Hi Archit,
Thanks for your comments. Please see my response for some comments below.
Comments without response will be addressed in patch version 2. I will
wait for other comments if any to push patch V2.
+static int dsi_gpio_init(str
Hi Stephane,
On 03/14/2015 01:19 AM, Stephane Viau wrote:
Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of the pipeline
status (eg: whether pipeline registers are flushe
On 03/20/2015 10:58 AM, Stephen Boyd wrote:
On 03/04, Archit Taneja wrote:
Currently, a RCG's M/N counter (used for fraction division) is set to either
'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
the corresponding rcg struct has a
Hi,
On 03/14/2015 04:54 AM, Hai Li wrote:
This change adds the DSI connector support in msm drm driver.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 11 +
drivers/gpu/drm/msm/Makefile |4 +
drivers/gpu/drm/msm/dsi/dsi.c | 203
drivers/gpu/
On 03/14/2015 01:15 AM, "Stéphane Viau" wrote:
Hi,
Hi,
On 03/09/2015 06:41 PM, Stephane Viau wrote:
This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.
Note that only one external display interface is present in this
configuration (DSI) but has not been enabled y
On 03/13/2015 02:36 PM, Daniel Vetter wrote:
On Fri, Mar 13, 2015 at 11:55:07AM +0530, Archit Taneja wrote:
On 03/11/2015 08:47 PM, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 01:51:02PM +0530, Archit Taneja wrote:
On 03/10/2015 05:47 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at
On 03/11/2015 08:47 PM, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 01:51:02PM +0530, Archit Taneja wrote:
On 03/10/2015 05:47 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:52:41PM +0530, Archit Taneja wrote:
On 03/10/2015 03:35 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03
Hi,
On 03/09/2015 06:41 PM, Stephane Viau wrote:
This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.
Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI
On 03/10/2015 05:47 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:52:41PM +0530, Archit Taneja wrote:
On 03/10/2015 03:35 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:22:49PM +0530, Archit Taneja wrote:
On 03/10/2015 03:17 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11
On 03/10/2015 09:03 PM, Jani Nikula wrote:
On Tue, 10 Mar 2015, Archit Taneja wrote:
On 03/10/2015 03:35 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:22:49PM +0530, Archit Taneja wrote:
On 03/10/2015 03:17 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11:28PM +0530, Archit
On 03/10/2015 04:24 PM, Philipp Zabel wrote:
Hi Archit,
thanks for the cleanup!
Am Dienstag, den 10.03.2015, 15:11 +0530 schrieb Archit Taneja:
DRM_IMX_FB_HELPER config is currently used to enable/disable fbdev emulation for
the imx kms driver.
Remove this local config option and use the
On 03/10/2015 03:35 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:22:49PM +0530, Archit Taneja wrote:
On 03/10/2015 03:17 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11:28PM +0530, Archit Taneja wrote:
Legacy fbdev emulation support via DRM is achieved through KMS FB helpers
On 03/10/2015 03:31 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11:30PM +0530, Archit Taneja wrote:
DRM_I915_FBDEV config is currently used to enable/disable fbdev emulation for
the i915 kms driver.
Replace this with the top level DRM_FBDEV_EMULATION config option. Using this
config
On 03/10/2015 03:16 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11:28PM +0530, Archit Taneja wrote:
Legacy fbdev emulation support via DRM is achieved through KMS FB helpers.
Most modesetting drivers enable provide fbdev emulation by default by selecting
KMS FB helpers. A few provide
On 03/10/2015 03:17 PM, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 03:11:28PM +0530, Archit Taneja wrote:
Legacy fbdev emulation support via DRM is achieved through KMS FB helpers.
Most modesetting drivers enable provide fbdev emulation by default by selecting
KMS FB helpers. A few provide
-off-by: Archit Taneja
---
drivers/gpu/drm/msm/Kconfig | 14 --
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 4 ++--
3 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index bacbbb7
bably okay to get remove the #ifdef itself, but just left it here for now to
be safe. It can be removed after some testing.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/sti/Kconfig | 6 --
drivers/gpu/drm/sti/sti_drm_drv.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
tegra_drm struct that adds/removes the terga_fbdev member has been
removed completely. This helps in calling stub drm fb helper functions at not
much
cost.
We could clean up fb.c a bit further to reduce the number of #ifdefs, but that's
left for later.
Signed-off-by: Archit Taneja
---
driver
drm_i915_private struct adding/removing members intel_fbdev and
fbdev_suspend_work has been removed. This helps us use stub drm helper functions
at not much cost.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/i915/Kconfig | 15 ---
drivers/gpu/drm/i915/Makefile| 4
in certain places.
We replace the #ifdef in imx_drm_driver_load with CONFIG_DRM_FBDEV_EMULATION.
It's probably okay to get remove the #ifdef itself, but just left it here for
now to be safe. It can be removed after some testing.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/imx/Kc
drivers that provide fbdev emulation by default won't be impacted by
this. However, if we could make all drivers use DRM_FBDEV_EMULATION, it
would clean up individual Kconfigs, and have a centralized place where we
touch FB_* configs.
Archit Taneja (6):
drm: Add top level Kconfig option for DRM
distributions expect the fbdev interface in the kernel.
For now, this config selects both FB_SYS_* and FB_CFB_* configs as some
modesetting drivers use the former and other the later. This needs to be taken
care of in a better way.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/Kconfig | 18
On 03/09/2015 01:14 PM, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 11:27:06AM +0530, Archit Taneja wrote:
On 03/05/2015 09:14 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 07:10:44AM -0500, Rob Clark wrote:
On Thu, Mar 5, 2015 at 5:06 AM, Archit Taneja wrote:
On 02/23/2015 09:09 PM
On 03/05/2015 09:14 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 07:10:44AM -0500, Rob Clark wrote:
On Thu, Mar 5, 2015 at 5:06 AM, Archit Taneja wrote:
On 02/23/2015 09:09 PM, Daniel Vetter wrote:
On Mon, Feb 23, 2015 at 10:03:21AM -0500, Rob Clark wrote:
On Mon, Feb 23, 2015 at 9
On 02/23/2015 09:09 PM, Daniel Vetter wrote:
On Mon, Feb 23, 2015 at 10:03:21AM -0500, Rob Clark wrote:
On Mon, Feb 23, 2015 at 9:09 AM, Daniel Vetter wrote:
On Mon, Feb 23, 2015 at 08:33:36AM -0500, Rob Clark wrote:
On Mon, Feb 23, 2015 at 5:29 AM, Archit Taneja wrote:
The
On 03/04/2015 09:14 PM, "Stéphane Viau" wrote:
Hi,
Hi Archit,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
Si
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