[Patch v2 1/1] PCI: pciehp: Add support for handling MRL events

." This seems to suggest that the slot should be brought down as soon as MRL is opened. Signed-off-by: Ashok Raj Co-developed-by: Kuppuswamy Sathyanarayanan --- Changes since v1: - Changes suggested by Lucas Wunner https://lore.kernel.org/linux-pci/20201119223749.GA103783@otc-nc

[PATCH 1/1] pci: pciehp: Handle MRL interrupts to enable slot for hotplug.

. - If there is ATTN button, and an MRL event pending, ignore Presence Detect. Since we want ATTN button to drive the hotplug event. Signed-off-by: Ashok Raj Co-developed-by: Kuppuswamy Sathyanarayanan --- drivers/pci/hotplug/pciehp.h | 1 + drivers/pci/hotplug/pciehp_ctrl.c | 69

[PATCH 1/1] pci: pciehp: Handle MRL interrupts to enable slot for hotplug.

. - If there is ATTN button, and an MRL event pending, ignore Presence Detect. Since we want ATTN button to drive the hotplug event. Signed-off-by: Ashok Raj Co-developed-by: Kuppuswamy Sathyanarayanan --- drivers/pci/hotplug/pciehp.h | 1 + drivers/pci/hotplug/pciehp_ctrl.c | 69

[tip: x86/pasid] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)

The following commit has been merged into the x86/pasid branch of tip: Commit-ID: 4e7b11567d946ebe14a3d10b697b078971a9da89 Gitweb: https://git.kernel.org/tip/4e7b11567d946ebe14a3d10b697b078971a9da89 Author:Ashok Raj AuthorDate:Tue, 15 Sep 2020 09:30:07 -07:00 Committer

[tip: x86/urgent] x86/hotplug: Silence APIC only after all interrupts are migrated

The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 52d6b926aabc47643cd910c85edb262b7f44c168 Gitweb: https://git.kernel.org/tip/52d6b926aabc47643cd910c85edb262b7f44c168 Author:Ashok Raj AuthorDate:Wed, 26 Aug 2020 21:12:10 -07:00 Committer

[PATCH v3] x86/hotplug: Silence APIC only after all irq's are migrated

and then took that CPU offline. Fixes: 60dcaad5736f ("x86/hotplug: Silence APIC and NMI when CPU is dead") Link: https://lore.kernel.org/lkml/875zdarr4h@nanos.tec.linutronix.de/ Reported-by: Evan Green Tested-by: Mathias Nyman Tested-by: Evan Green Reviewed-by: Evan Green Signed-off-by:

[PATCH v2] x86/hotplug: Silence APIC only after all irq's are migrated

.de/ Reported-by: Evan Green Tested-by: Mathias Nyman Tested-by: Evan Green Reviewed-by: Evan Green Signed-off-by: Ashok Raj --- v2: - Typos and fixes suggested by Randy Dunlap To: linux-kernel@vger.kernel.org To: Thomas Gleixner Cc: Sukumar Ghorai Cc: Srikanth Nandamuri Cc: Evan Green Cc:

[PATCH] x86/hotplug: Silence APIC only after all irq's are migrated

e/ Signed-off-by: Ashok Raj To: linux-kernel@vger.kernel.org To: Thomas Gleixner Cc: Sukumar Ghorai Cc: Srikanth Nandamuri Cc: Evan Green Cc: Mathias Nyman Cc: Bjorn Helgaas Cc: sta...@vger.kernel.org --- arch/x86/kernel/smpboot.c | 11 +-- 1 file changed, 9 insertions(+), 2 delet

[PATCH v3 1/1] PCI/ATS: Check PRI supported on the PF device when SRIOV is enabled

("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS") Signed-off-by: Ashok Raj To: Bjorn Helgaas To: Joerg Roedel To: Lu Baolu Cc: sta...@vger.kernel.org Cc: linux-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Ashok Raj Cc: io...@lists.linux-foundation.org ---

[PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

To: Lu Baolu Cc: sta...@vger.kernel.org Cc: linux-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Ashok Raj Cc: io...@lists.linux-foundation.org --- drivers/iommu/intel/iommu.c | 2 +- drivers/pci/ats.c | 13 + include/linux/pci-ats.h | 4 3 files changed, 18

[PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

@vger.kernel.org Cc: Ashok Raj Cc: io...@lists.linux-foundation.org --- drivers/iommu/intel/iommu.c | 2 +- drivers/pci/ats.c | 14 ++ include/linux/pci-ats.h | 4 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers

[PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

Raj To: Bjorn Helgaas To: Joerg Roedel To: Lu Baolu Cc: sta...@vger.kernel.org Cc: linux-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Ashok Raj Cc: io...@lists.linux-foundation.org --- drivers/iommu/intel/iommu.c | 2 +- drivers/pci/ats.c | 14 ++ include

[PATCH] PCI: Relax ACS requirement for Intel RCiEP devices.

3 Network controller: Intel Corporation Device 9df0 (rev 30) Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 This permits assigning this device to a guest VM. Fixes: f096c061f552 ("iommu: Rework iommu_group_get_for_pci_dev()") Signed-off-by: Ashok Raj To: Joer

[PATCH] iommu: Relax ACS requirement for Intel RCiEP devices.

3 Network controller: Intel Corporation Device 9df0 (rev 30) Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 This permits assigning this device to a guest VM. Fixes: f096c061f552 ("iommu: Rework iommu_group_get_for_pci_dev()") Signed-off-by: Ashok Raj To: Joer

[PATCH] iommu: Relax ACS requirement for RCiEP devices.

ntegrated Endpoint, MSI 00 This permits assigning this device to a guest VM. Fixes: f096c061f552 ("iommu: Rework iommu_group_get_for_pci_dev()") Signed-off-by: Ashok Raj To: Joerg Roedel To: Bjorn Helgaas Cc: linux-kernel@vger.kernel.org Cc: io...@lists.linux-foundation.org Cc: Lu Baolu

[tip: x86/microcode] x86/microcode: Update late microcode in parallel

The following commit has been merged into the x86/microcode branch of tip: Commit-ID: 93946a33b5693a6bbcf917a170198ff4afaa7a31 Gitweb: https://git.kernel.org/tip/93946a33b5693a6bbcf917a170198ff4afaa7a31 Author:Ashok Raj AuthorDate:Thu, 22 Aug 2019 23:43:47 +03:00

[PATCH] x86/microcode: Add an option to reload microcode even if revision is unchanged

ort for AMD - add taint flag - removed global force_ucode_load and parameterized it. Signed-off-by: Ashok Raj Signed-off-by: Mihai Carabas cc: Boris Ostrovsky Cc: Mihai Carabas Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jon Grimm Cc: kanth.ghatr...@oracle.com

[4.15 & 4.14 stable 02/12] x86/CPU: Add a microcode loader callback

From: Borislav Petkov <b...@suse.de> commit 1008c52c09dcb23d93f8e0ea83a6246265d2cce0 upstream Add a callback function which the microcode loader calls when microcode has been updated to a newer revision. Do the callback only when no error was encountered during loading. Tested-by: Ash

[4.15 & 4.14 stable 02/12] x86/CPU: Add a microcode loader callback

From: Borislav Petkov commit 1008c52c09dcb23d93f8e0ea83a6246265d2cce0 upstream Add a callback function which the microcode loader calls when microcode has been updated to a newer revision. Do the callback only when no error was encountered during loading. Tested-by: Ashok Raj Signed-off

[4.15 & 4.14 stable 01/12] x86/microcode: Propagate return value from updating functions

From: Borislav Petkov <b...@suse.de> commit 3f1f576a195aa266813cbd4ca70291deb61e0129 upstream ... so that callers can know when microcode was updated and act accordingly. Tested-by: Ashok Raj <ashok@intel.com> Signed-off-by: Borislav Petkov <b...@suse.de> Reviewed-by

[4.15 & 4.14 stable 01/12] x86/microcode: Propagate return value from updating functions

From: Borislav Petkov commit 3f1f576a195aa266813cbd4ca70291deb61e0129 upstream ... so that callers can know when microcode was updated and act accordingly. Tested-by: Ashok Raj Signed-off-by: Borislav Petkov Reviewed-by: Ashok Raj Cc: Andy Lutomirski Cc: Arjan van de Ven Cc: Borislav

[4.15 & 4.14 stable 03/12] x86/CPU: Check CPU feature bits after microcode upgrade

ke use of the newly visible features. Originally-by: Ashok Raj <ashok@intel.com> Tested-by: Ashok Raj <ashok@intel.com> Signed-off-by: Borislav Petkov <b...@suse.de> Reviewed-by: Ashok Raj <ashok@intel.com> Cc: Andy Lutomirski <l...@kernel.org> Cc: Arjan v

[4.15 & 4.14 stable 03/12] x86/CPU: Check CPU feature bits after microcode upgrade

visible features. Originally-by: Ashok Raj Tested-by: Ashok Raj Signed-off-by: Borislav Petkov Reviewed-by: Ashok Raj Cc: Andy Lutomirski Cc: Arjan van de Ven Cc: Borislav Petkov Cc: Dan Williams Cc: Dave Hansen Cc: David Woodhouse Cc: Greg Kroah-Hartman Cc: Josh Poimboeuf Cc: Linus

[4.15 & 4.14 stable 11/12] x86/microcode: Attempt late loading only when new microcode is present

nmail.com> Signed-off-by: Borislav Petkov <b...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Emanuel Czirai <xftrox...@protonmail.com> Tested-by: Ashok Raj <ashok@intel.com> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Cc: Tom Len

[4.15 & 4.14 stable 11/12] x86/microcode: Attempt late loading only when new microcode is present

-by: Thomas Gleixner Tested-by: Emanuel Czirai Tested-by: Ashok Raj Tested-by: Tom Lendacky Cc: Tom Lendacky Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r/20180314183615.17629-1...@alien8.de --- arch/x86/include/asm/microcode.h | 1 + arch/x86/kernel/cpu

[4.15 & 4.14 stable 12/12] x86/microcode: Fix CPU synchronization routine

Also, as an optimization, do not do the exit sync if microcode wasn't updated. Reported-by: Emanuel Czirai <xftrox...@protonmail.com> Signed-off-by: Borislav Petkov <b...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Emanuel Czirai <xftrox...@protonmail.com&g

[4.15 & 4.14 stable 12/12] x86/microcode: Fix CPU synchronization routine

not do the exit sync if microcode wasn't updated. Reported-by: Emanuel Czirai Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Emanuel Czirai Tested-by: Ashok Raj Tested-by: Tom Lendacky Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r

[4.15 & 4.14 stable 00/12] Series to update microcode loading.

on a 4.9 backport, will send those once i get them to work. stop_machine differences seem big enough that i might choose a different approach for the 4.9 backport. Cheers, Ashok Ashok Raj (4): x86/microcode/intel: Check microcode revision before updating sibling threads x86/microcode/intel

[4.15 & 4.14 stable 00/12] Series to update microcode loading.

on a 4.9 backport, will send those once i get them to work. stop_machine differences seem big enough that i might choose a different approach for the 4.9 backport. Cheers, Ashok Ashok Raj (4): x86/microcode/intel: Check microcode revision before updating sibling threads x86/microcode/intel

[4.15 & 4.14 stable 10/12] x86/microcode: Synchronize late microcode loading

Petkov <b...@suse.de> Signed-off-by: Ashok Raj <ashok@intel.com> Signed-off-by: Borislav Petkov <b...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Tested-by: Ashok Raj <ashok@intel.com> Rev

[4.15 & 4.14 stable 10/12] x86/microcode: Synchronize late microcode loading

Petkov Signed-off-by: Ashok Raj Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Tom Lendacky Tested-by: Ashok Raj Reviewed-by: Tom Lendacky Cc: Arjan Van De Ven Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r/20180228102846.13447-8...@alien8

[4.15 & 4.14 stable 06/12] x86/microcode/intel: Writeback and invalidate caches before updating microcode

. [ Borislav: Massage it and use native_wbinvd() in both cases. ] Signed-off-by: Ashok Raj <ashok@intel.com> Signed-off-by: Borislav Petkov <b...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Tested-by: Ashok

[4.15 & 4.14 stable 06/12] x86/microcode/intel: Writeback and invalidate caches before updating microcode

. [ Borislav: Massage it and use native_wbinvd() in both cases. ] Signed-off-by: Ashok Raj Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Tom Lendacky Tested-by: Ashok Raj Cc: Arjan Van De Ven Cc: Tom Lendacky Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: http

[4.15 & 4.14 stable 05/12] x86/microcode/intel: Check microcode revision before updating sibling threads

on the CPU before performing a microcode update and thus save us the WRMSR 0x79 because it is a particularly expensive operation. [ Borislav: Massage changelog and coding style. ] Signed-off-by: Ashok Raj <ashok@intel.com> Signed-off-by: Borislav Petkov <b...@suse.de> Signed-off-by: Tho

[4.15 & 4.14 stable 05/12] x86/microcode/intel: Check microcode revision before updating sibling threads

on the CPU before performing a microcode update and thus save us the WRMSR 0x79 because it is a particularly expensive operation. [ Borislav: Massage changelog and coding style. ] Signed-off-by: Ashok Raj Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Tom Lendacky Tested

[4.15 & 4.14 stable 09/12] x86/microcode: Request microcode on the BSP

.@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Tested-by: Ashok Raj <ashok@intel.com> Reviewed-by: Tom Lendacky <thomas.lenda...@amd.com> Cc: Arjan Van De Ven <arjan.van.de@intel.com> Cc: Asit K

[4.15 & 4.14 stable 04/12] x86/microcode: Get rid of struct apply_microcode_ctx

.@linutronix.de> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Tested-by: Ashok Raj <ashok@intel.com> Cc: Arjan Van De Ven <arjan.van.de@intel.com> Cc: Tom Lendacky <thomas.lenda...@amd.com> Cc: Asit K Mallick <asit.k.mall...@intel.com> Cc: sta...

[4.15 & 4.14 stable 09/12] x86/microcode: Request microcode on the BSP

Tested-by: Tom Lendacky Tested-by: Ashok Raj Reviewed-by: Tom Lendacky Cc: Arjan Van De Ven Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r/20180228102846.13447-7...@alien8.de --- arch/x86/kernel/cpu/microcode/core.c | 11 +-- 1 file changed, 5 insertions

[4.15 & 4.14 stable 04/12] x86/microcode: Get rid of struct apply_microcode_ctx

From: Borislav Petkov commit 854857f5944c59a881ff607b37ed9ed41d031a3b upstream It is a useless remnant from earlier times. Use the ucode_state enum directly. No functional change. Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Tom Lendacky Tested-by: Ashok Raj Cc

[4.15 & 4.14 stable 08/12] x86/microcode/intel: Look into the patch cache first

kov <b...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Tom Lendacky <thomas.lenda...@amd.com> Tested-by: Ashok Raj <ashok@intel.com> Cc: Arjan Van De Ven <arjan.van.de@intel.com> Cc: Tom Lendacky <thomas.lenda...@amd.com> Cc: Asit K

[4.15 & 4.14 stable 08/12] x86/microcode/intel: Look into the patch cache first

Gleixner Tested-by: Tom Lendacky Tested-by: Ashok Raj Cc: Arjan Van De Ven Cc: Tom Lendacky Cc: Asit K Mallick Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r/20180228102846.13447-6...@alien8.de --- arch/x86/kernel/cpu/microcode/intel.c | 11 +-- 1 file changed, 5 insertions

[4.15 & 4.14 stable 07/12] x86/microcode: Do not upload microcode if CPUs are offline

commit 30ec26da9967d0d785abc24073129a34c3211777 upstream Avoid loading microcode if any of the CPUs are offline, and issue a warning. Having different microcode revisions on the system at any time is outright dangerous. [ Borislav: Massage changelog. ] Signed-off-by: Ashok Raj <as

[4.15 & 4.14 stable 07/12] x86/microcode: Do not upload microcode if CPUs are offline

commit 30ec26da9967d0d785abc24073129a34c3211777 upstream Avoid loading microcode if any of the CPUs are offline, and issue a warning. Having different microcode revisions on the system at any time is outright dangerous. [ Borislav: Massage changelog. ] Signed-off-by: Ashok Raj Signed-off

[tip:x86/pti] x86/microcode: Synchronize late microcode loading

Commit-ID: a5321aec6412b20b5ad15db2d6b916c05349dbff Gitweb: https://git.kernel.org/tip/a5321aec6412b20b5ad15db2d6b916c05349dbff Author: Ashok Raj <ashok@intel.com> AuthorDate: Wed, 28 Feb 2018 11:28:46 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu

[tip:x86/pti] x86/microcode: Synchronize late microcode loading

Commit-ID: a5321aec6412b20b5ad15db2d6b916c05349dbff Gitweb: https://git.kernel.org/tip/a5321aec6412b20b5ad15db2d6b916c05349dbff Author: Ashok Raj AuthorDate: Wed, 28 Feb 2018 11:28:46 +0100 Committer: Thomas Gleixner CommitDate: Thu, 8 Mar 2018 10:19:26 +0100 x86/microcode

[tip:x86/pti] x86/microcode: Do not upload microcode if CPUs are offline

Commit-ID: 30ec26da9967d0d785abc24073129a34c3211777 Gitweb: https://git.kernel.org/tip/30ec26da9967d0d785abc24073129a34c3211777 Author: Ashok Raj <ashok@intel.com> AuthorDate: Wed, 28 Feb 2018 11:28:43 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu

[tip:x86/pti] x86/microcode: Do not upload microcode if CPUs are offline

Commit-ID: 30ec26da9967d0d785abc24073129a34c3211777 Gitweb: https://git.kernel.org/tip/30ec26da9967d0d785abc24073129a34c3211777 Author: Ashok Raj AuthorDate: Wed, 28 Feb 2018 11:28:43 +0100 Committer: Thomas Gleixner CommitDate: Thu, 8 Mar 2018 10:19:26 +0100 x86/microcode: Do

[tip:x86/pti] x86/microcode/intel: Writeback and invalidate caches before updating microcode

Commit-ID: 91df9fdf51492aec9fed6b4cbd33160886740f47 Gitweb: https://git.kernel.org/tip/91df9fdf51492aec9fed6b4cbd33160886740f47 Author: Ashok Raj <ashok@intel.com> AuthorDate: Wed, 28 Feb 2018 11:28:42 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu

[tip:x86/pti] x86/microcode/intel: Writeback and invalidate caches before updating microcode

Commit-ID: 91df9fdf51492aec9fed6b4cbd33160886740f47 Gitweb: https://git.kernel.org/tip/91df9fdf51492aec9fed6b4cbd33160886740f47 Author: Ashok Raj AuthorDate: Wed, 28 Feb 2018 11:28:42 +0100 Committer: Thomas Gleixner CommitDate: Thu, 8 Mar 2018 10:19:25 +0100 x86/microcode/intel

[tip:x86/pti] x86/microcode/intel: Check microcode revision before updating sibling threads

Commit-ID: c182d2b7d0ca48e0d6ff16f7d883161238c447ed Gitweb: https://git.kernel.org/tip/c182d2b7d0ca48e0d6ff16f7d883161238c447ed Author: Ashok Raj <ashok@intel.com> AuthorDate: Wed, 28 Feb 2018 11:28:41 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu

[tip:x86/pti] x86/microcode/intel: Check microcode revision before updating sibling threads

Commit-ID: c182d2b7d0ca48e0d6ff16f7d883161238c447ed Gitweb: https://git.kernel.org/tip/c182d2b7d0ca48e0d6ff16f7d883161238c447ed Author: Ashok Raj AuthorDate: Wed, 28 Feb 2018 11:28:41 +0100 Committer: Thomas Gleixner CommitDate: Thu, 8 Mar 2018 10:19:25 +0100 x86/microcode/intel

[v2 0/3] Patches to address some limitations in OS microcode loading.

reload_store() per Boris's comments. What's not done from review: TBD: - Load microcode file only once. Added comments in source for future cleanup. - Removing ucd->errors. (Gives a count of failed loads) Ashok Raj (3): x86/microcode/intel: Check microcode revision before updating sibling thre

[v2 0/3] Patches to address some limitations in OS microcode loading.

reload_store() per Boris's comments. What's not done from review: TBD: - Load microcode file only once. Added comments in source for future cleanup. - Removing ucd->errors. (Gives a count of failed loads) Ashok Raj (3): x86/microcode/intel: Check microcode revision before updating sibling thre

[v2 2/3] x86/microcode/intel: Perform a cache flush before ucode update.

Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@kernel.org> Cc: LKML <linux-kernel@vger.kernel.org> Cc:

[v2 2/3] x86/microcode/intel: Perform a cache flush before ucode update.

Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Tony Luck Cc: Andi Kleen Cc: Boris Petkov Cc: Tom

[v2 3/3] x86/microcode: Quiesce all threads before a microcode update.

he sibling thread and subsequent sibling would already have the latest copy of the microcode. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@kernel.org> Cc: LKML <linux-kernel@vger.kernel.org> Cc: Tom Lendacky <thomas.lenda...@amd.com> Cc: Thomas Gleixner &l

[v2 3/3] x86/microcode: Quiesce all threads before a microcode update.

he sibling thread and subsequent sibling would already have the latest copy of the microcode. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Tom Lendacky Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Tony Luck Cc: Andi Kleen Cc: Boris Petkov Cc: Arjan Van De Ven Changes from V1: - Check for r

[v2 1/3] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the CPU before performing a ucode update. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@k

[v2 1/3] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the CPU before performing a ucode update. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Thomas Gleixner Cc

[PATCH 2/3] x86/microcode/intel: Perform a cache flush before ucode update.

Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@kernel.org> Cc: LKML <linux-kernel@vger.kernel.org> Cc:

[PATCH 2/3] x86/microcode/intel: Perform a cache flush before ucode update.

Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Tony Luck Cc: Andi Kleen Cc: Boris Petkov Cc: Tom

[PATCH 1/3] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the CPU before performing a ucode update. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@k

[PATCH 1/3] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the CPU before performing a ucode update. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Thomas Gleixner Cc

[PATCH 3/3] x86/microcode: Quiesce all threads before a microcode update.

uiet state during these updates. Such updates are rare events, so we use stop_machine() to ensure the whole system is quiet. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@kernel.org> Cc: LKML <linux-kernel@vger.kernel.org> Cc: Tom Lendacky <thomas.lenda...@

[PATCH 3/3] x86/microcode: Quiesce all threads before a microcode update.

uiet state during these updates. Such updates are rare events, so we use stop_machine() to ensure the whole system is quiet. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Tom Lendacky Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Tony Luck Cc: Andi Kleen Cc: Boris Petkov Cc: Arjan Van De Ven

[PATCH 0/3] Patch series to address some limitations in OS microcode loading.

The following set of patches address some limitations on microcode loading. First patch avoids a redundant microcode load on sibling thread if another HT sibling got updated. Ashok Raj (3): x86/microcode/intel: Check microcode revision before updating sibling threads x86/microcode/intel

[PATCH 0/3] Patch series to address some limitations in OS microcode loading.

The following set of patches address some limitations on microcode loading. First patch avoids a redundant microcode load on sibling thread if another HT sibling got updated. Ashok Raj (3): x86/microcode/intel: Check microcode revision before updating sibling threads x86/microcode/intel

[PATCH] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the cpu before performing a ucode update. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@k

[PATCH] x86/microcode/intel: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the cpu before performing a ucode update. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML --- arch/x86/kernel/cpu

[PATCH] x86/microcode: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the cpu before performing a ucode update. Signed-off-by: Ashok Raj <ashok@intel.com> Cc: X86 ML <x...@k

[PATCH] x86/microcode: Check microcode revision before updating sibling threads

After updating microcode on one of the threads in the core, the thread sibling automatically gets the update since the microcode resources are shared. Check the ucode revision on the cpu before performing a ucode update. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML --- arch/x86/kernel/cpu

[PATCH] x86/microcode: Check if any new features are present after a microcode reload.

in feature set and warns user to use early microcode load before using the new features. Suggested-by: Andi Kleen <andi.kl...@intel.com> Signed-off-by: Ashok Raj <ashok@intel.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: David Woodhouse <d...@amazon.co.uk>

[PATCH] x86/microcode: Check if any new features are present after a microcode reload.

in feature set and warns user to use early microcode load before using the new features. Suggested-by: Andi Kleen Signed-off-by: Ashok Raj Cc: Thomas Gleixner Cc: David Woodhouse Cc: Arjan van de Ven Cc: Dave Hansen Cc: Tony Luck Cc: Tim Chen Cc: Greg Kroah-Hartman Cc: Borislav Petkov

[tip:x86/pti] KVM/x86: Add IBPB support

Commit-ID: 15d45071523d89b3fb7372e2135fbd72f6af9506 Gitweb: https://git.kernel.org/tip/15d45071523d89b3fb7372e2135fbd72f6af9506 Author: Ashok Raj <ashok@intel.com> AuthorDate: Thu, 1 Feb 2018 22:59:43 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Sat

[tip:x86/pti] KVM/x86: Add IBPB support

Commit-ID: 15d45071523d89b3fb7372e2135fbd72f6af9506 Gitweb: https://git.kernel.org/tip/15d45071523d89b3fb7372e2135fbd72f6af9506 Author: Ashok Raj AuthorDate: Thu, 1 Feb 2018 22:59:43 +0100 Committer: Thomas Gleixner CommitDate: Sat, 3 Feb 2018 23:06:51 +0100 KVM/x86: Add IBPB support

[PATCH 2/5] x86/ibrs: Add new helper macros to save/restore MSR_IA32_SPEC_CTRL

- same as spec_ctrl_unprotected_begin spec_ctrl_restriction_on - same as spec_ctrl_unprotected_end Signed-off-by: Ashok Raj <ashok@intel.com> --- arch/x86/include/asm/spec_ctrl.h | 12 arch/x86/kernel/cpu/spec_ctrl.c | 11 +++ 2 files changed, 23 insertions(+) diff

[PATCH 2/5] x86/ibrs: Add new helper macros to save/restore MSR_IA32_SPEC_CTRL

- same as spec_ctrl_unprotected_begin spec_ctrl_restriction_on - same as spec_ctrl_unprotected_end Signed-off-by: Ashok Raj --- arch/x86/include/asm/spec_ctrl.h | 12 arch/x86/kernel/cpu/spec_ctrl.c | 11 +++ 2 files changed, 23 insertions(+) diff --git a/arch/x86/include

[PATCH 3/5] x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL

Add direct access to MSR_IA32_SPEC_CTRL from a guest. Also save/restore IBRS values during exits and guest resume path. Rebasing based on Tim's patch Signed-off-by: Ashok Raj <ashok@intel.com> --- arch/x86/kvm/cpuid.c | 3 ++- arch/x86/kvm/vmx.c

[PATCH 3/5] x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL

Add direct access to MSR_IA32_SPEC_CTRL from a guest. Also save/restore IBRS values during exits and guest resume path. Rebasing based on Tim's patch Signed-off-by: Ashok Raj --- arch/x86/kvm/cpuid.c | 3 ++- arch/x86/kvm/vmx.c | 41 + arch/x86/kvm

[PATCH 5/5] x86/feature: Detect the x86 feature Indirect Branch Prediction Barrier

this MSR is only writable and does not carry any state. Its a barrier so the code should perform a wrmsr when the barrier is needed. Signed-off-by: Ashok Raj <ashok@intel.com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kernel/cpu/spec_

[PATCH 5/5] x86/feature: Detect the x86 feature Indirect Branch Prediction Barrier

this MSR is only writable and does not carry any state. Its a barrier so the code should perform a wrmsr when the barrier is needed. Signed-off-by: Ashok Raj --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kernel/cpu/spec_ctrl.c| 7 +++ arch

[PATCH 1/5] x86/ibrs: Introduce native_rdmsrl, and native_wrmsrl

- Remove including microcode.h, and use native macros from asm/msr.h - added license header for spec_ctrl.c Signed-off-by: Ashok Raj <ashok@intel.com> --- arch/x86/include/asm/spec_ctrl.h | 17 - arch/x86/kernel/cpu/spec_ctrl.c | 1 + 2 files changed, 17 insertions

[PATCH 1/5] x86/ibrs: Introduce native_rdmsrl, and native_wrmsrl

- Remove including microcode.h, and use native macros from asm/msr.h - added license header for spec_ctrl.c Signed-off-by: Ashok Raj --- arch/x86/include/asm/spec_ctrl.h | 17 - arch/x86/kernel/cpu/spec_ctrl.c | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git

[PATCH 4/5] x86/svm: Direct access to MSR_IA32_SPEC_CTRL

eature is not emuerated by the CPU. [Ashok: Modified to reuse V3 spec-ctrl patches from Tim] Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Ashok Raj <ashok@intel.com> --- arch/x86/kvm/svm.c | 35 +++ 1 file changed, 35 insertions(+)

[PATCH 0/5] Add support for IBRS & IBPB KVM support.

longer for the rebase to be complete in tip/x86/pti. Ashok Raj (4): x86/ibrs: Introduce native_rdmsrl, and native_wrmsrl x86/ibrs: Add new helper macros to save/restore MSR_IA32_SPEC_CTRL x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL x86/feature: Detect the x86 feature Indirect

[PATCH 0/5] Add support for IBRS & IBPB KVM support.

longer for the rebase to be complete in tip/x86/pti. Ashok Raj (4): x86/ibrs: Introduce native_rdmsrl, and native_wrmsrl x86/ibrs: Add new helper macros to save/restore MSR_IA32_SPEC_CTRL x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL x86/feature: Detect the x86 feature Indirect

[PATCH 4/5] x86/svm: Direct access to MSR_IA32_SPEC_CTRL

by the CPU. [Ashok: Modified to reuse V3 spec-ctrl patches from Tim] Signed-off-by: Paolo Bonzini Signed-off-by: Ashok Raj --- arch/x86/kvm/svm.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 0e68f0b..7c14471a

Re: [PATCH 3/7] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest

Hi Paolo Do you assume that host isn't using IBRS and only guest uses it? On Mon, Jan 8, 2018 at 10:08 AM, Paolo Bonzini wrote: > Direct access to MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD is important > for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore

Re: [PATCH 3/7] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest

Hi Paolo Do you assume that host isn't using IBRS and only guest uses it? On Mon, Jan 8, 2018 at 10:08 AM, Paolo Bonzini wrote: > Direct access to MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD is important > for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore guest > IBRS on VM entry

[PATCH 1/4] iommu/vt-d: IOMMU Page Request needs to check if address is canonical.

kernel@vger.kernel.org> Cc: io...@lists.linux-foundation.org Cc: David Woodhouse <dw...@infradead.org> Cc: Jacob Pan <jacob.jun....@intel.com> Cc: Ashok Raj <ashok@intel.com> Signed-off-by: Ashok Raj <ashok@intel.com> Reported-by: Sudeep Dutt <sudeep.d...@intel.com&

[PATCH 1/4] iommu/vt-d: IOMMU Page Request needs to check if address is canonical.

io...@lists.linux-foundation.org Cc: David Woodhouse Cc: Jacob Pan Cc: Ashok Raj Signed-off-by: Ashok Raj Reported-by: Sudeep Dutt --- drivers/iommu/intel-svm.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index f167

[PATCH 2/4] iommu/vt-d: Avoid calling virt_to_phys() on null pointer

; Cc: Jacob Pan <jacob.jun....@intel.com> Cc: Ashok Raj <ashok@intel.com> Signed-off-by: Ashok Raj <ashok@intel.com> --- drivers/iommu/intel-iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iomm

[PATCH 2/4] iommu/vt-d: Avoid calling virt_to_phys() on null pointer

New kernels with debug show panic() from __phys_addr() checks. Avoid calling virt_to_phys() when pasid_state_tbl pointer is null To: Joerg Roedel To: linux-kernel@vger.kernel.org> Cc: io...@lists.linux-foundation.org Cc: David Woodhouse Cc: Jacob Pan Cc: Ashok Raj Signed-off-by: Ashok

[PATCH 0/4] Patches to support ring0 SVM and devtlb

Hi Sorry for resending.. iommu list email was mistyped :-( The first 2 patches in the series fix some simple bugs in Intel vt-d driver. The 3rd patch Adds support for kmem notify required to support ring0 SVM. 4th patch uses the hooks to perform device tlb invalidations. Ashok Raj (3): iommu

[PATCH 0/4] Patches to support ring0 SVM and devtlb

Hi Sorry for resending.. iommu list email was mistyped :-( The first 2 patches in the series fix some simple bugs in Intel vt-d driver. The 3rd patch Adds support for kmem notify required to support ring0 SVM. 4th patch uses the hooks to perform device tlb invalidations. Ashok Raj (3): iommu

[PATCH 4/4] iommu/vt-d: Hooks to invalidate iotlb/devtlb when using supervisor PASID's.

mmu_notifier_register() api's. To: linux-kernel@vger.kernel.org To: Joerg Roedel <j...@8bytes.org> Cc: Ashok Raj <ashok@intel.com> Cc: Dave Hansen <dave.han...@intel.com> Cc: Huang Ying <ying.hu...@intel.com> Cc: CQ Tang <cq.t...@intel.com> Cc: Thomas Gleixner <t...@l

[PATCH 4/4] iommu/vt-d: Hooks to invalidate iotlb/devtlb when using supervisor PASID's.

mmu_notifier_register() api's. To: linux-kernel@vger.kernel.org To: Joerg Roedel Cc: Ashok Raj Cc: Dave Hansen Cc: Huang Ying Cc: CQ Tang Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: Andy Lutomirski Cc: Rik van Riel Cc: Kees Cook Cc: Andrew Morton Cc: Michal Hocko Cc: "P

[PATCH 3/4] mm: Add kernel MMU notifier to manage remote TLB

gister on the notifier chain to flush the device TLBs when necessary. To: linux-kernel@vger.kernel.org To: Joerg Roedel <j...@8bytes.org> Cc: Ashok Raj <ashok@intel.com> Cc: Dave Hansen <dave.han...@intel.com> Cc: CQ Tang <cq.t...@intel.com> Cc: Thomas Gleixner <t...@l

[PATCH 3/4] mm: Add kernel MMU notifier to manage remote TLB

the device TLBs when necessary. To: linux-kernel@vger.kernel.org To: Joerg Roedel Cc: Ashok Raj Cc: Dave Hansen Cc: CQ Tang Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: Andy Lutomirski Cc: Rik van Riel Cc: Kees Cook Cc: Andrew Morton Cc: "Kirill A. Shutemov" Cc: Mi

[PATCH 2/4] iommu/vt-d: Avoid calling virt_to_phys() on null pointer

Pan <jacob.jun....@intel.com> Cc: Ashok Raj <ashok@intel.com> Signed-off-by: Ashok Raj <ashok@intel.com> --- drivers/iommu/intel-iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iomm

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