16 0 0 7583616 184816 723040 0 6300 6166 4 62 12 2 20
18 0 0 7583632 184480 722400 0 2814 1754 2 58 4 1 35
Signed-off-by: Bibo Mao
---
.../admin-guide/kernel-parameters.txt | 2 +-
arch/loongarch/Kconfig| 11 ++
arch/loongarch
the feature.
One cpu attr ioctl command KVM_LOONGARCH_VCPU_PVTIME_CTRL is added to
save and restore base address of steal time structure when VM is migrated.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 7 ++
arch/loongarch/include/asm/kvm_para.h | 10 ++
arch/loongarch/include
PARAVIRT_TIME_ACCOUNTING kconfig option in file
arch/loongarch/Kconfig
2. Function name change such as replace pv_register_steal_time with
pv_enable_steal_time etc
---
Bibo Mao (2):
LoongArch: KVM: Add steal time support in kvm side
LoongArch: Add steal time support in guest side
.../admin-guide
50
16 0 0 7583616 184816 723040 0 6300 6166 4 62 12 2 20
18 0 0 7583632 184480 722400 0 2814 1754 2 58 4 1 35
Signed-off-by: Bibo Mao
---
.../admin-guide/kernel-parameters.txt | 2 +-
arch/loongarch/Kconfig| 11 ++
arch
... v2:
1. Add PARAVIRT_TIME_ACCOUNTING kconfig option in file
arch/loongarch/Kconfig
2. Function name change such as replace pv_register_steal_time with
pv_enable_steal_time etc
---
Bibo Mao (2):
LoongArch: KVM: Add steal time support in kvm side
LoongArch: Add steal time support in guest
the feature.
One cpu attr ioctl command KVM_LOONGARCH_VCPU_PVTIME_CTRL is added to
save and restore base address of steal time structure when VM is migrated.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 7 ++
arch/loongarch/include/asm/kvm_para.h | 10 ++
arch/loongarch/include
-maob...@loongson.cn/
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 7 ++
arch/loongarch/include/asm/kvm_para.h | 10 +++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/include/uapi/asm/kvm.h | 4 +
arch/loongarch/kvm/exit.c | 29
50
16 0 0 7583616 184816 723040 0 6300 6166 4 62 12 2 20
18 0 0 7583632 184480 722400 0 2814 1754 2 58 4 1 35
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 11 +++
arch/loongarch/include/asm/paravirt.h | 5 +
arch/loongarch/kernel
. Add PARAVIRT_TIME_ACCOUNTING kconfig option in file
arch/loongarch/Kconfig
2. Function name change such as replace pv_register_steal_time with
pv_enable_steal_time etc
---
Bibo Mao (2):
LoongArch: KVM: Add steal time support in kvm side
LoongArch: Add steal time support in guest side
arch
interrupt
acknowledge. And IPI message is stored in DDR, no trap in get IPI message.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9 ++
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/paravirt.h | 27
.../include/asm
into hypervisor
greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 129 +
arch/loongarch/include/asm/kvm_vcpu.h | 10 ++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kvm/exit.c
PV features, and the area can be extended
for other hypervisors in future. This area will never be used for
real HW, it is only used by software.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/inst.h | 1 +
arch/loongarch/include/asm/loongarch.h | 10 +
arch/loongarch/kvm/exit.c
as 256 by KVM which comes from
extioi irqchip.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 93 ++-
arch/loongarch/kvm/vm.c | 11
4
with value
KVM_HCALL_INVALID_CODE, rather than inject EXCCODE_INE invalid
instruction exception. So VM can continue to executing the next code.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch/loongarch/include/asm/kvm_para.h | 26 ++
arch
2. Refine changelog description
3. Add hypercall statistic support for vcpu
4. Set percpu pv ipi message buffer aligned with cacheline
5. Refine pv ipi send logic, do not send ipi message with if there is
pending ipi message.
---
Bibo Mao (6):
LoongArch/smp: Refine some ipi functions on LoongArc
encoding, the ipi hw will convert it into bitmap in ipi message
buffer.
3. Add structure smp_ops on LoongArch platform so that pv ipi can be used
later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include
-maob...@loongson.cn/
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 7 ++
arch/loongarch/include/asm/kvm_para.h | 10 +++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/include/uapi/asm/kvm.h | 4 +
arch/loongarch/kvm/exit.c | 35
hypervisor to enable steal time. When vcpu is offline, physical address
is set as 0 and tells hypervisor to disable steal time.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/paravirt.h | 5 +
arch/loongarch/kernel/paravirt.c | 130 ++
arch/loongarch/kernel/time.c
-maob...@loongson.cn/
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 7 ++
arch/loongarch/include/asm/kvm_para.h | 10 +++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/include/uapi/asm/kvm.h | 4 +
arch/loongarch/kvm/exit.c | 35
hypervisor to enable steal time. When vcpu is offline, physical address
is set as 0 and tells hypervisor to disable steal time.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/paravirt.h | 5 +
arch/loongarch/kernel/paravirt.c | 130 ++
arch/loongarch/kernel/time.c
Para-virt feature steal time is added in both kvm and guest kernel side.
It is silimar with other architectures, steal time structure comes from
guest memory, also pseduo register is used to save/restore base address
of steal time structure, so that vm migration is supported also.
Bibo Mao (2
Add documentation topic for using pv_virt when running as a guest
on KVM hypervisor.
Signed-off-by: Bibo Mao
---
Documentation/virt/kvm/index.rst | 1 +
.../virt/kvm/loongarch/hypercalls.rst | 82 +++
Documentation/virt/kvm/loongarch/index.rst| 10
interrupt
acknowledge. And IPI message is stored in DDR, no trap in get IPI message.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9 ++
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/paravirt.h | 27
.../include/asm
into hypervisor
greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 129 +
arch/loongarch/include/asm/kvm_vcpu.h | 10 ++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kvm/exit.c
as 256 by KVM which comes from
extioi irqchip.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 93 ++-
arch/loongarch/kvm/vm.c | 11
4
PV features, and the area can be extended
for other hypervisors in future. This area will never be used for
real HW, it is only used by software.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/inst.h | 1 +
arch/loongarch/include/asm/loongarch.h | 10 +
arch/loongarch/kvm/exit.c
ending ipi message.
---
Bibo Mao (7):
LoongArch/smp: Refine some ipi functions on LoongArch platform
LoongArch: KVM: Add hypercall instruction emulation support
LoongArch: KVM: Add cpucfg area for kvm hypervisor
LoongArch: KVM: Add vcpu search support from physical cpuid
LoongArch: KVM: Add pv i
encoding, the ipi hw will convert it into bitmap in ipi message
buffer.
3. Add structure smp_ops on LoongArch platform so that pv ipi can be used
later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include
with value
KVM_HCALL_INVALID_CODE, rather than inject EXCCODE_INE invalid
instruction exception. So VM can continue to executing the next code.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch/loongarch/include/asm/kvm_para.h | 26 ++
arch
Add documentation topic for using pv_virt when running as a guest
on KVM hypervisor.
Signed-off-by: Bibo Mao
---
Documentation/virt/kvm/index.rst | 1 +
.../virt/kvm/loongarch/hypercalls.rst | 79 +++
Documentation/virt/kvm/loongarch/index.rst| 10
into hypervisor greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 130 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kvm/exit.c | 76 ++-
arch/loongarch
interrupt
acknowledge. And IPI message is stored in DDR, no trap in get IPI message.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9 ++
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/paravirt.h | 27
.../include/asm
as 256 by KVM which comes from
extioi irqchip.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 93 ++-
arch/loongarch/kvm/vm.c | 11
4
encoding, the ipi hw will convert it into bitmap in ipi message
buffer.
3. Add structure smp_ops on LoongArch platform so that pv ipi can be used
later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include
PV features, and the area can be extended
for other hypervisors in future. This area will never be used for
real HW, it is only used by software.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/inst.h | 1 +
arch/loongarch/include/asm/loongarch.h | 10 +
arch/loongarch/kvm/exit.c
age buffer aligned with cacheline
5. Refine pv ipi send logic, do not send ipi message with if there is
pending ipi message.
---
Bibo Mao (7):
LoongArch/smp: Refine some ipi functions on LoongArch platform
LoongArch: KVM: Add hypercall instruction emulation support
LoongArch: KVM: Add c
with value
KVM_HCALL_INVALID_CODE, rather than inject EXCCODE_INE invalid
instruction exception. So VM can continue to executing the next code.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch/loongarch/include/asm/kvm_para.h | 26 ++
arch
into hypervisor greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 123 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kernel/irq.c
as 256 by KVM which comes from
extioi irqchip.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 93 ++-
arch/loongarch/kvm/vm.c | 11
4
is KVM hypervisor, since there is only KVM hypervisor
supported on LoongArch now.
There is not effective with pv_ipi_init() now, it is dummy function.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9
arch/loongarch/include/asm/kvm_para.h | 7
with value
KVM_HCALL_INVALID_CODE, rather than inject EXCCODE_INE invalid
instruction exception. So VM can continue to executing the next code.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch/loongarch/include/asm/kvm_para.h | 26 ++
arch
PV features, and the area can be extended
for other hypervisors in future. This area will never be used for
real HW, it is only used by software.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/inst.h | 1 +
arch/loongarch/include/asm/loongarch.h | 10 ++
arch/loongarch/kvm/exit.c
cpu pv ipi message buffer aligned with cacheline
5. Refine pv ipi send logic, do not send ipi message with if there is
pending ipi message.
---
Bibo Mao (6):
LoongArch/smp: Refine some ipi functions on LoongArch platform
LoongArch: KVM: Add hypercall instruction emulation support
LoongArch
encoding, the ipi hw will convert it into bitmap in ipi message
buffer.
3. Add structure smp_ops on LoongArch platform so that pv ipi can be used
later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include
trap times into hypervisor greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 124 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch
different size declaration about physical cpuid,
KVM uses the smallest cpuid from extioi irqchip, and the max cpuid size
is defines as 256.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c
is KVM hypervisor, since there is only KVM hypervisor
supported on LoongArch now.
This patch only adds paravirt interface for guest kernel, however there
is not effective pv functions added here.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9
arch/loongarch
with if there is
pending ipi message.
---
Bibo Mao (6):
LoongArch/smp: Refine ipi ops on LoongArch platform
LoongArch: KVM: Add hypercall instruction emulation support
LoongArch: KVM: Add cpucfg area for kvm hypervisor
LoongArch: Add paravirt interface for guest kernel
LoongArch: KVM: Add vcpu search
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
instruction exception.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch
VM will trap into hypervisor when executing cpucfg instruction. And
hardware only uses the area 0 - 20 for actual usage now, here one
specified area 0x4000 -- 0x40ff is used for KVM hypervisor,
and the area can be extended to use for other hypervisors in future.
Signed-off-by: Bibo Mao
structure smp_ops on LoongArch platform so that pv ipi can be used
later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include/asm/smp.h | 31 +++
arch/loongarch/kernel/irq.c | 22
that pv ipi can be used later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include/asm/smp.h | 31 +++
arch/loongarch/kernel/irq.c | 22 +--
arch/loongarch/kernel/perf_event.c
the smallest cpuid from extioi, and
the max cpuid size is defines as 256.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 93 ++-
arch/loongarch/kvm/vm.c
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
instruction exception.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch
into hypervisor greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 124 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kernel/irq.c
is KVM hypervisor, since there is only KVM hypervisor
supported on LoongArch now.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9
arch/loongarch/include/asm/kvm_para.h | 7
arch/loongarch/include/asm/paravirt.h | 27
.../include
System will trap into hypervisor when executing cpucfg instruction.
And now hardware only uses the area 0 - 20 for actual usage, here
one specified area 0x1000 -- 0x10ff is used for KVM hypervisor,
and the area can be extended for other hypervisors in future.
Signed-off-by: Bibo Mao
changelog description
3. Add hypercall statistic support for vcpu
4. Set percpu pv ipi message buffer aligned with cacheline
5. Refine pv ipi send logic, do not send ipi message with if there is
pending ipi message.
---
Bibo Mao (6):
LoongArch/smp: Refine ipi ops on LoongArch platform
the smallest cpuid from extioi, and
the max cpuid size is defines as 256.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/kvm_host.h | 26
arch/loongarch/include/asm/kvm_vcpu.h | 1 +
arch/loongarch/kvm/vcpu.c | 61 ++-
arch/loongarch/kvm/vm.c
into hypervisor greatly.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/kvm_host.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 124 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kernel/irq.c
is KVM hypervisor, and there is only KVM hypervisor
supported on LoongArch now.
Signed-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 9
arch/loongarch/include/asm/kvm_para.h | 7
arch/loongarch/include/asm/paravirt.h | 27
.../include/asm
that pv ipi can be used later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include/asm/smp.h | 31 +++
arch/loongarch/kernel/irq.c | 22 +--
arch/loongarch/kernel/perf_event.c
routing uses hw cpuid
2. Refine changelog description
3. Add hypercall statistic support for vcpu
4. Set percpu pv ipi message buffer aligned with cacheline
5. Refine pv ipi send logic, do not send ipi message with if there is
pending ipi message.
---
Bibo Mao (6):
LoongArch: KVM: Add
System will trap into hypervisor when executing cpucfg instruction.
And now hardware only uses the area 0 - 20 for actual usage, here
one specified area 0x1000 -- 0x10ff is used for KVM hypervisor,
and the area can be extended for other hypervisors in future.
Signed-off-by: Bibo Mao
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
instruction exception.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch
that pv ipi can be used later.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 4 ++
arch/loongarch/include/asm/irq.h | 10 -
arch/loongarch/include/asm/smp.h | 31 +++
arch/loongarch/kernel/irq.c | 22 +--
arch/loongarch/kernel/perf_event.c
-by: Bibo Mao
---
arch/loongarch/include/asm/hardirq.h | 1 +
arch/loongarch/include/asm/kvm_para.h | 124 +
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kernel/irq.c| 2 +-
arch/loongarch/kernel/paravirt.c | 103
System will trap into hypervisor when executing cpucfg instruction.
And now hardware only uses the area 0 - 20 for actual usage, here
one specified area 0x1000 -- 0x10ff is used for KVM hypervisor,
and the area can be extended for other hypervisors in future.
Signed-off-by: Bibo Mao
-off-by: Bibo Mao
---
arch/loongarch/Kconfig| 8
arch/loongarch/include/asm/kvm_para.h | 7
arch/loongarch/include/asm/paravirt.h | 27
.../include/asm/paravirt_api_clock.h | 1 +
arch/loongarch/kernel/Makefile
) 42.4 56665.3 13364.4
Shell Scripts (8 concurrent) 6.0 7412.1 12353.4
System Call Overhead 15000.06962239.6 4641.5
System Benchmarks Index Score7205.8
Bibo Mao (5):
LoongArch: KVM: Add hypercall
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
instruction exception.
Signed-off-by: Bibo Mao
---
arch/loongarch/include/asm/Kbuild | 1 -
arch
From: Bibo Mao
If multiple threads are accessing the same huge page at the same
time, hugetlb_cow will be called if one thread write the COW huge
page. And function huge_ptep_clear_flush is called to notify other
threads to clear the huge pte tlb entry. The other threads clear
the huge pte tlb
From: Bibo Mao
On mips platform huge pte pointers to invalid_pte_table if
huge_pte_none return true. TLB entry with normal page size is
added if huge pte entry is none. When updating huge pte entry,
older tlb entry with normal page needs to be invalid.
This patch uses lightweight tlb flush
degrade such as wrprotect is set on the pmd entry
2. pmd entry is cleared
3. there is exception if set_pmd_at is issued by dup_mmap, since
flush_tlb_mm is called for parent process, it is not necessary
to flush tlb in function copy_huge_pmd.
Signed-off-by: Bibo Mao
---
arch/mips/mm/pgtable-32.c | 1
platforms except arc/mips
system.
Signed-off-by: Bibo Mao
---
mm/huge_memory.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 0f9187b..8b4ccf7 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -643,6 +643,7 @@ static vm_fault_t
to be invalidated.
Here page fault address is passed to function update_mmu_cache_pmd,
rather than pmd huge page start address. The page fault address
can be used for invalidating older tlb entry.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 9 +
mm/huge_memory.c
degrade such as wrprotect is set on the pmd entry
2. pmd entry is cleared
3. there is exception if set_pmd_at is issued by dup_mmap, since
flush_tlb_mm is called for parent process, it is not necessary
to flush tlb in function copy_huge_pmd.
Signed-off-by: Bibo Mao
---
v2:
- add the same operation
are declared with
SYSCALL_DEFINEx, metadata of the system call symbol name begins with
sys_. Here mips specific function arch_syscall_match_sym_name is used to
compare function name between sys_call_table[] and metadata of syscall
symbol.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/ftrace.h
is not necessary in slow
page fault path. This patch removes pte_sw_mkyoung function which
is defined as empty function except MIPS system.
Signed-off-by: Bibo Mao
Acked-by: Andrew Morton
---
v2:
- refine commit log title
---
arch/mips/include/asm/pgtable.h | 10 --
arch/mips/mm/cache.c
On Linux system, writable applies readable privilege in most
architectures, this patch adds this policy on MIPS platform
where hardware rixi is supported.
Signed-off-by: Bibo Mao
---
arch/mips/mm/cache.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm
On Linux system, writable applies readable privilege in most
architectures, this patch adds this policy on MIPS platform
where hardware rixi is supported.
Signed-off-by: Bibo Mao
---
arch/mips/mm/cache.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm
is not necessary in slow
page fault path. This patch removes pte_sw_mkyoung function which
is defined as empty function except MIPS system.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 11 +--
arch/mips/mm/cache.c| 34 +-
include/asm
Function set_pmd_at is to set pmd entry, if tlb entry need to
be flushed, there exists pmdp_huge_clear_flush alike function
before set_pmd_at is called. So it is not necessary to call
flush_tlb_all in this function.
Signed-off-by: Bibo Mao
---
arch/mips/mm/pgtable-64.c | 1 -
1 file changed, 1
handling the fault. Instead of
triggering another fault, let's directly update the local TLB of the
second thread. Function update_mmu_tlb is used here to update local
TLB on the second thread, and it is defined as empty on other arches.
Signed-off-by: Bibo Mao
Acked-by: Andrew Morton
---
arch
It is not necessary to flush tlb page on all CPUs if suitable PTE
entry exists already during page fault handling, just updating
TLB is fine.
Here redefine flush_tlb_fix_spurious_fault as empty on MIPS system.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 5 +
1 file
.
Signed-off-by: Bibo Mao
Acked-by: Andrew Morton
---
arch/mips/include/asm/pgtable.h | 2 ++
include/asm-generic/pgtable.h | 16
mm/memory.c | 3 +++
3 files changed, 21 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm
If original PTE has _PAGE_ACCESSED bit set, and new pte has no
_PAGE_NO_READ bit set, we can add _PAGE_SILENT_READ bit to enable
page valid bit.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips
flush_tlb_fix_spurious_fault and tlb update into two patches
- comments typo modification
- separate tlb update and add pte readable privilege into two patches
Bibo Mao (4):
MIPS: Do not flush tlb page when updating PTE entry
mm/memory.c: Update local TLB if PTE entry exists
mm/memory.c: Add
.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
include/asm-generic/pgtable.h | 16
mm/memory.c | 3 +++
3 files changed, 21 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d2004b5
If original PTE has _PAGE_ACCESSED bit set, and new pte has no
_PAGE_NO_READ bit set, we can add _PAGE_SILENT_READ bit to enable
page valid bit.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips
-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 9b01d2d..0d625c2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -478,6 +478,8
handling the fault. Instead of
triggering another fault, let's directly update the local TLB of the
second thread. Function update_mmu_tlb is used here to update local
TLB on the second thread, and it is defined as empty on other arches.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h
.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
include/asm-generic/pgtable.h | 16
mm/memory.c | 3 +++
3 files changed, 21 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 5f610ec
and tlb update into two patches
- comments typo modification
- separate tlb update and add pte readable privilege into two patches
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include
multiple threads access the same
page at the same time, so the negative effect is limited on other arches.
With specjvm2008 workload, smp-race pgfault counts is about 3% to 4%
of the total pgfault counts by watching /proc/vmstats information
Signed-off-by: Bibo Mao
---
arch/mips/include/asm
If original PTE has _PAGE_ACCESSED bit set, and new pte has no
_PAGE_NO_READ bit set, we can add _PAGE_SILENT_READ bit to enable
page valid bit.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips
.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
include/asm-generic/pgtable.h | 15 +++
mm/memory.c | 3 +++
3 files changed, 20 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 0d625c2..755d534
multiple threads access the same
page at the same time, so the negative effect is limited on other arches.
Signed-off-by: Bibo Mao
---
mm/memory.c | 44 +++-
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/mm/memory.c b/mm/memory.c
index
privilege into two patches
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 9b01d2d..0d625c2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm
If original PTE has _PAGE_ACCESSED bit set, and new pte has no
_PAGE_NO_READ bit set, we can add _PAGE_SILENT_READ bit to enable
page valid bit.
Signed-off-by: Bibo Mao
---
arch/mips/include/asm/pgtable.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips
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