Hi, Stu:
I've some inline comments.
On Mon, 2018-05-14 at 17:59 +0800, Stu Hsieh wrote:
> This patch add support for the Mediatek MT2712 DISP subsystem.
> There are two OVL engine and three disp output in MT2712.
>
> Signed-off-by: Stu Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c
iver
> failed to get the clocks. Omit this error on the defered probe path.
>
> Signed-off-by: Matthias Brugger
It's better to use 'drm/mediatek:' for title to align drm commits.
For the modification,
Acked-by: CK Hu
Regards,
CK
> ---
> drivers/gpu/drm/m
Hi, Matthias:
On Fri, 2018-04-27 at 11:23 +0200, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> With the mtk-mmsys MFD device in place, we switch the probing for
> mt2701 from device-tree to mfd.
>
> Signed-off-by: Matthias Brugger
Reviewed-by: C
Hi, Satendra:
I've applied this patch to my branch mediatek-drm-next-4.18,
and I've added below modification in this patch to prevent build error,
diff --git a/drivers/gpu/drm/mediatek/Kconfig
b/drivers/gpu/drm/mediatek/Kconfig
index 294de45..119ec0a 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
Hi, Vasyl:
Sorry for the late reply.
I've applied this to my branch mediatek-drm-next-4.18
Regards,
CK
On Thu, 2017-11-23 at 17:31 +0800, Philipp Zabel wrote:
> On Tue, 2017-11-21 at 23:31 +0100, Vasyl Gomonovych wrote:
> > Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...)).
> >
> >
Hi, Houlong:
I've one more inline comment.
On Wed, 2018-01-31 at 15:28 +0800, houlong@mediatek.com wrote:
> From: "hs.l...@mediatek.com"
>
> Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code.
>
> Signed-off-by: Houlong Wei
> Signed-off-by: HS Liao
> ---
> drivers/s
ements.
>
> Signed-off-by: Houlong Wei
> Signed-off-by: HS Liao
> Signed-off-by: CK Hu
> ---
> drivers/mailbox/Kconfig | 10 +
> drivers/mailbox/Makefile |2 +
> drivers/mailbox/mtk-cmdq-mailbox.c | 594
> +++
Hi, Houlong:
I've some inline comment.
On Wed, 2018-01-31 at 15:28 +0800, houlong@mediatek.com wrote:
> From: "hs.l...@mediatek.com"
>
> Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code.
>
> Signed-off-by: Houlong Wei
> Signed-off-by: HS Liao
> ---
> drivers/soc/m
Hi, Matthias:
On Tue, 2017-11-14 at 22:41 +0100, Matthias Brugger wrote:
> The MMSYS subsystem includes clocks and drm components.
> This patch adds a MFD device to probe both drivers from the same
> device tree compatible.
>
> Signed-off-by: Matthias Brugger
> ---
> drivers/mfd/Kconfig |
Hi, Matthias:
On Tue, 2017-11-14 at 22:41 +0100, Matthias Brugger wrote:
> Use the MFD device for SoC mt8173. Probing via devicetree
> is no longer needed for any SoC, so delete it.
>
> Signed-off-by: Matthias Brugger
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/
Hi, Matthias:
On Thu, 2017-11-23 at 09:30 +0100, Matthias Brugger wrote:
>
> On 11/23/2017 06:48 AM, CK Hu wrote:
> > Hi, Matthias:
> >
> > On Tue, 2017-11-14 at 22:41 +0100, Matthias Brugger wrote:
> >> With the mtk-mmsys MFD device in place, we switch the pr
Hi, Matthias:
On Tue, 2017-11-14 at 22:41 +0100, Matthias Brugger wrote:
> With the mtk-mmsys MFD device in place, we switch the probing for
> mt2701 from device-tree to mfd.
>
> Signed-off-by: Matthias Brugger
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 32 +---
Hi, Matthias:
On Tue, 2017-11-14 at 22:41 +0100, Matthias Brugger wrote:
> The mmsys memory space is shared between the drm and the
> clk driver. Use regmap to access it.
>
> Signed-off-by: Matthias Brugger
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c |
Hi,
On Thu, 2017-10-19 at 16:54 +0200, Philipp Zabel wrote:
> Hi Laurent,
>
> On Thu, 2017-10-19 at 16:39 +0300, Laurent Pinchart wrote:
> > Hi Philipp,
> >
> > On Thursday, 19 October 2017 16:01:54 EEST Philipp Zabel wrote:
> > > On Thu, 2017-10-19 at 13:26 +0200, Matthias Brugger wrote:
> > >
Hi, Matthias:
On Thu, 2017-10-19 at 13:26 +0200, Matthias Brugger wrote:
> DRM subysystem and clock driver shared the same compatible mmsys.
> This stopped does not work, as only the first driver for a compatible
> gets probed. We change the comaptible to the new DRM identifier to fix
> this.
>
>
Hi, Matthias:
On Mon, 2017-10-16 at 09:49 +0200, Matthias Brugger wrote:
>
> On 10/15/2017 10:26 AM, CK Hu wrote:
> > Hi, Chaotian:
> >
> > On Wed, 2017-10-11 at 10:41 +0800, Chaotian Jing wrote:
> >> mt2701/mt2712 has 12bit clock div, which is not compatible w
Hi, Chaotian:
On Wed, 2017-10-11 at 10:41 +0800, Chaotian Jing wrote:
> mt2701/mt2712 has 12bit clock div, which is not compatible with
> mt8135/mt8173. and, some additional features will be added in
> mt2701/mt2712, so that need distinguish it by comatibale name.
>
> Signed-off-by: Chaotian Jing
Hi, Ryder:
Mode comment inline.
On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:
> This patch adds the device nodes for the display function block.
> Also, we add some missing pin macros in mt7623-pinfunc.h.
>
> Signed-off-by: Ryder Lee
> CC: Linus Walleij
> Acked-by: Linus Walleij
> ---
>
Hi, Ryder:
Some comment inline.
On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:
> This patch adds the device nodes for the display function block.
> Also, we add some missing pin macros in mt7623-pinfunc.h.
>
> Signed-off-by: Ryder Lee
> CC: Linus Walleij
> Acked-by: Linus Walleij
> ---
>
On Thu, 2017-06-22 at 10:43 +0800, Bibby Hsieh wrote:
> For some greater resolution, the rdma threshold
> variable will overflow.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drive
On Fri, 2017-06-16 at 22:02 +0800, YT Shen wrote:
> Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
> hardware settings) calls devm_kfree() and then devm_kzalloc() to
> reallocate color module data structure. But this reallocation cannnot
> guarantee the new address is unch
On Mon, 2017-06-12 at 15:15 +0800, YT Shen wrote:
> Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
> hardware settings) calls devm_kfree() and then devm_kzalloc() to
> reallocate color module data structure. But this reallocation cannnot
> guarantee the new address is unch
Hi, Christophe:
Applied to my branch mediatek-drm-next-4.13, thanks.
Regards,
CK
On Fri, 2017-06-09 at 21:27 +0200, Christophe JAILLET wrote:
> If 'devm_kmalloc_array' returns NULL, we should return -ENOMEM as already
> done a few lines above instead of deferencing a NULL pointer a few lines
> b
On Wed, 2017-05-24 at 14:24 +0200, Daniel Vetter wrote:
> On Wed, May 24, 2017 at 05:20:45PM +0800, CK Hu wrote:
> > On Tue, 2017-05-23 at 15:12 +0200, Daniel Vetter wrote:
> > > On Tue, May 23, 2017 at 05:28:15PM +0800, CK Hu wrote:
> > > > Hi, Bibby:
> > >
On Tue, 2017-05-23 at 15:12 +0200, Daniel Vetter wrote:
> On Tue, May 23, 2017 at 05:28:15PM +0800, CK Hu wrote:
> > Hi, Bibby:
> >
> > I've applied this patch to my branch mediatek-drm-fixes-4.12-rc1,
> > thanks.
> >
> > Regards,
> > CK
>
Hi, Bibby:
I've applied this patch to my branch mediatek-drm-next-4.13, thanks.
Regards,
CK
On Tue, 2017-01-24 at 12:40 +0800, Bibby Hsieh wrote:
> MT8173 overlay can support UYVY and YUYV format,
> we add the format in DRM driver.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: Daniel Kurtz
>
Hi, Bibby:
I've applied this patch to my branch mediatek-drm-fixes-4.12-rc1,
thanks.
Regards,
CK
On Tue, 2017-01-24 at 13:10 +0800, Bibby Hsieh wrote:
> Current Mediatek DRM driver does not support interlaced mode, and
> will hang if such resolution is used: Filter those to prevent
> kernel hang
Hi, Colin:
Sorry for my late reply. I've applied this patch to my branch
mediatek-drm-next-4.13, thanks.
Regards,
CK
On Tue, 2017-04-11 at 14:44 +0100, Colin King wrote:
> From: Colin Ian King
>
> The current message contains a spelling mistake and is not easily
> parsable. Re-phrase it to be
Hi, Nickey:
Sorry for the late reply. I've applied this patch to my branch
mediatek-drm-fixes-4.12-rc1.
Regards,
CK
On Tue, 2017-03-21 at 16:27 +0800, Nickey Yang wrote:
> mtk_hdmi_setup_vendor_specific_infoframe will return before handle
> mtk_hdmi_hw_send_info_frame.Because hdmi_vendor_infofra
Hi, Bibby:
One comment inline.
On Fri, 2017-05-19 at 17:57 +0800, Bibby Hsieh wrote:
> For some greater resolution, the rdma threshold
> variable will overflow.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 ---
> 1 file changed, 4 insertions(+), 3 del
sieh
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 0e8c4d9..e33678d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_
Hi, Bibby:
On Tue, 2017-01-24 at 12:40 +0800, Bibby Hsieh wrote:
> MT8173 overlay can support UYVY and YUYV format,
> we add the format in DRM driver.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: Daniel Kurtz
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediate
itialize DSI first so that we can send commands to panel.
>
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 266
> ++---
> 1 file changed, 161 insertions(+), 105 dele
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 +
Hi, YT:
one comment inline.
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module.
> Original flow works on there is a bridge chip: DSI -> bridge -> panel.
> In this case: DSI -> panel, the DSI sub driver flow should be updated.
> We need to initi
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b3c7fd8..85f22
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 168
> +++
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92
> ++
> 1
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> cleaning up unused define and refine function name and variable
>
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
> 1 file changed, 25 insertions(+)
>
>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> Add BLS component for PWM + GAMMA function
>
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 -
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> We need to acquire mutex before using the resources,
> and need to release it after finished.
> So we don't need to write registers in the blanking period.
>
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
>
changed.
> And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.
>
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 -
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 18 +++-
>
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl'
> define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma'
>
> Signed-off-by: YT Shen
Acked-by CK Hu
&g
Hi, YT:
On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote:
> modify dsi enter ultra low power mode method
>
This looks like a power-saving patch. I think without this, MT2701 could
still work correctly. The commit message is too simple, please describe
why this patch is related to MT2701. If it i
Hi, YT:
On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote:
> modify data rate limitation (>lGbps/lane) for mipitx
>
I think MT2701 DRM can work correctly without this patch.
Why do you put this patch in MT2701 series?
Maybe you can send this patch independently.
Regards,
CK
> Signed-off-by: sh
Hi, YT:
On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote:
> add non-continuous clock mode and EOT packet control for dsi
>
I think commit title should be 'drm/mediatek: add non-continuous clock
mode and EOT packet control for dsi', and commit message should describe
more information about this m
Hi, YT:
On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote:
> This is MT2701 DRM support PATCH v10, based on 4.9-rc1.
> We add DSI interrupt control, transfer function for MIPI DSI panel support.
> Most codes are the same, except some register changed.
>
> For example:
> - DISP_OVL address offset
Hi, YT:
some comments inline.
On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module.
> Original flow works on there is a bridge chip: DSI -> bridge -> panel.
> In this case: DSI -> panel, the DSI sub driver flow should be updated.
> We need to ini
Hi, Daniel:
On Fri, 2016-11-18 at 11:22 +0800, Daniel Kurtz wrote:
> Hi CK,
>
> On Thu, Nov 17, 2016 at 1:36 PM, CK Hu wrote:
> > Hi, Jitao:
> >
> >
> > On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
> >> Tune dsi frame rate by pixel clock, dsi
Hi, Arnd:
I've made a mistake that I've tried to build these patches on v4.9-rc1,
but I does not set CONFIG_DRM_MEDIATEK=y, therefore I didn't find out
these build fails. Now I fix the config problem, and I think I should
build these patches on latest kernel version even though patch's owner
test
Hi, Jitao:
On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
> Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
> mode, those signals will cause h-time larger than normal and reduce FPS.
> So need to mu
DSI
> RDMA -> DPI
> And we have shadow register support in MT2701.
>
> We remove dts patch from the patch series, which depends on MT2701 CCF and
> scpsys.
For this series, it looks good to me.
Acked-by: CK Hu
>
> Changes since v8:
> - enable 3 DSI interrupts only
&
Hi, Matthias:
Even though OVL HW would not be enabled before component_add() in
current design, your patch would be safe for any situation.
Acked-by CK Hu
Regards,
CK
On Wed, 2016-10-26 at 16:09 +0200, Matthias Brugger wrote:
> The probe function requests the interrupt before initializ
Hi, Jitao:
On Wed, 2016-10-26 at 16:59 +0800, Jitao Shi wrote:
> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
> Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
> signal will cause h-time larger than normal and reduce FPS.
> Need to multiply
Hi, Jitao:
On Tue, 2016-10-25 at 13:40 +0800, Jitao Shi wrote:
> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
> Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
> signal will cause h-time larger than normal and reduce FPS.
> Need to multiply
Acked-by: CK Hu
On Tue, 2016-10-18 at 16:23 +0800, Bibby Hsieh wrote:
> If we want to set the hardware OD to relay mode,
> we have to set OD_CFG register rather than
> OD_RELAYMODE; otherwise, the system will access
> the wrong address.
>
> Fixes: 7216436420414144646f5d8343d0
e the HDMI driving current to improve performance.
> 3) Make sure that pixel clock is 297MHz when resolution is 4K.
>
For this series,
Acked-by: CK Hu
> Changes since v4:
> - Update commit message and patch title.
>
> Changes since v3:
> - Rebase to 4.8-rc1.
> - The va
Hi, HS:
One comment inline
On Fri, 2016-09-30 at 16:56 +0800, Horng-Shyang Liao wrote:
> Hi CK,
>
> Please see my inline reply.
>
> On Fri, 2016-09-30 at 11:06 +0800, CK Hu wrote:
> > Hi, HS:
> >
> > On Mon, 2016-09-05 at 09:44 +0800, HS Liao wrote:
>
mmand Engine (GCE) hardware to achieve this requirement.
> Currently, CMDQ only supports display related hardwares, but we expect
> it can be extended to other hardwares for future requirements.
>
> Signed-off-by: HS Liao
> Signed-off-by: CK Hu
> ---
[snip...]
> +
> +st
Hi, Jitao:
Sorry for late reply.
Some comments inline.
On Fri, 2016-08-26 at 14:10 +0800, Jitao Shi wrote:
> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx,
> Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this
> signal will cause h-time larger t
Acked-by: CK Hu
On Thu, 2016-09-29 at 11:29 +0800, Bibby Hsieh wrote:
> To make sure that the first vblank IRQ after enabling
> vblank isn't too short or immediate, we have to clear
> the IRQ status before enable OVL interrupt.
>
> Signed-off-by: Bibby Hsieh
> ---
>
Acked-by: CK Hu
On Thu, 2016-09-29 at 11:29 +0800, Bibby Hsieh wrote:
> MTK DRM driver didn't set the vblank_disable_allowed to
> true, it cause that the irq_handler is called every
> 16.6 ms (every vblank) when the display didn't be updated.
>
> Signed-off-by: Bibby Hs
Acked-by: CK Hu
On Thu, 2016-09-29 at 11:22 +0800, Bibby Hsieh wrote:
> Fix the typo: OD_RELAYMODE->OD_CFG
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++
> drivers/gpu/drm/mediatek/mtk_disp_rd
Hi, YT:
On Wed, 2016-09-14 at 15:22 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-14 at 14:39 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote:
> > > Hi CK,
> > >
> > > On Tue,
Hi, YT:
On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote:
> Hi CK,
>
> On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> > > Hi CK,
> > >
> > > On Wed,
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module and MIPI TX module.
> Original flow works on there is a bridge chip: DSI -> bridge -> panel.
> In this case: DSI -> panel, the DSI sub driver flow should be updated.
> We need to initial
Hi, YT:
On Mon, 2016-09-12 at 18:15 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 12:58 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > This patch update enable/disable flow of DSI module and MIPI
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen
> ---
[snip...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 53065c7..0850aa4 100644
> --- a/
Hi, YT:
On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > From: shaoming chen
> > >
> >
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 78
> ++
> 1 file changed, 78 insertions(+)
>
[snip...]
>
> +st
Hi, YT:
On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 13:37 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > This patch add support for the Mediatek MT2701 DISP subsystem.
&
Hi, Bibby:
Sorry for the late reply.
On Wed, 2016-08-17 at 14:58 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
>
>From the code you modified, I think title should be: "Enlarge pll_rate
range from (, ) to (, )"
In description, you can ex
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
[snip...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module and MIPI TX module
>
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
> ---
I think the description is too simple. Please briefly describe WHY of
this patch. The original enab
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 188
> +
> 1 file changed, 188 insertions(+)
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 76
> ++
> 1 file changed, 76 insertions(+)
>
[snip...]
>
> +st
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
> 1 file changed, 25 insertions(+)
>
[snip...]
> @@ -111,6 +119,9 @@ static unsigne
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll setting changed.
> And add pr
Hi, YT:
On Wed, 2016-08-10 at 15:24 +0800, YT Shen wrote:
> Hi CK,
>
> On Fri, 2016-08-05 at 18:08 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> > > From: shaoming chen
> > >
> >
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 76
>
> 1 file changed, 76 insertions(+)
>
> diff --git a/driver
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 261
>
> 1 file changed, 261 insertions(+)
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6 ++
> drivers/gpu/drm/mediatek/mtk_disp_
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> This patch adds the device nodes for the DISP function blocks for MT2701
>
> Signed-off-by: YT Shen
> ---
> arch/arm/boot/dts/mt2701.dtsi | 86
> +
> 1 file changed, 86 insertions(+)
>
> diff
Hi, YT:
On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 286
>
> 1 file changed, 286 insertions(+)
Hi, YT:
On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92
>
> 1 file changed, 92 insertions(+)
>
> diff --git a/driver
Hi, Bibby:
On Fri, 2016-07-29 at 17:04 +0800, Bibby Hsieh wrote:
> From: Daniel Kurtz
>
> It is not actually useful to a mtk plane to know its zpos/index, so just
> remove this field.
>
> This let's us completely remove struct mtk_drm_plane in a follow up patch.
'let's us'? My English is not a
Hi, YT:
On Thu, 2016-07-28 at 15:17 +0800, YT Shen wrote:
> Hi Philipp, CK,
>
> On Thu, 2016-07-28 at 10:07 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote:
> > > Am Dienstag, den 26.07.2016, 18:42
Hi, YT:
On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote:
> Am Dienstag, den 26.07.2016, 18:42 +0800 schrieb YT Shen:
> > Hi CK,
> >
> > On Wed, 2016-07-20 at 14:53 +0800, CK Hu wrote:
> > > Hi, YT:
> > >
> > > Some comments inline.
> &g
Hi, Bibby:
On Wed, 2016-07-27 at 16:25 +0800, Bibby Hsieh wrote:
> If MT8173 can support HDMI 4K resoultion, the
> VENCPLL should be configured to 800MHZ.
> We didn't set VENCPLL directly, we set the
> mm_sel to 400MHz statically in the board device tree.
You may rewrite the description as below:
Hi, Bibby:
On Mon, 2016-07-25 at 14:24 +0800, Bibby Hsieh wrote:
> Hi, CK,
>
> Thanks for your comments.
>
> On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote:
> > Hi, Bibby:
> >
> > Some comments inline.
> >
> > On Wed, 2016-07-20 at 12:03 +080
Hi, Bibby:
On Thu, 2016-07-21 at 11:21 +0800, Bibby Hsieh wrote:
> Hi, CK
>
> I'm appreciate your comments.
>
>
[snip...]
> > >
> > > @@ -469,7 +484,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct
> > > mtk_ddp_comp *ovl)
> > > if (state->pending_config) {
> > > mtk_dd
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
>
> Signed-off-by: Junzhi Zhao
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 184
> +++
Hi, Bibby:
One comment inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> In order to improve 4K resolution performance,
> we have to enhance the HDMI driving currend
> when clock rate is greater than 165MHz.
>
> Signed-off-by: Junzhi Zhao
> Signed-off-by: B
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6
> drivers/gpu/d
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi and mipi tx driver for mipi panel support
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 169
> ++--
> drivers/gp
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 322
>
> 1 file cha
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 130
>
> 1 file changed, 130 insertions(+)
Hi, YT:
One comment inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6
> drivers/gpu/drm
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