Hi Vignesh,
Thanks for your information.
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Wednesday, November 11, 2020 1:44 PM
> To: Chin-Ting Kuo ; Boris Brezillon
>
> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
> driver
>
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Friday, November 6, 2020 7:30 PM
> To: Chin-Ting Kuo
> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
> driver
>
> +Tudor and Vignesh
>
> On Fri, 6 Nov 2020 10:21:0
Hi Boris,
Thanks for your comments and suggestions.
> -Original Message-
> From: Boris Brezillon
> Sent: Friday, November 6, 2020 5:06 PM
> To: Chin-Ting Kuo
> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
> driver
>
> On Fri, 6 Nov 20
Hi Rob,
> -Original Message-
> From: Rob Herring
> Sent: Friday, November 6, 2020 6:40 AM
> To: Chin-Ting Kuo
> Cc: broo...@kernel.org; j...@jms.id.au; and...@aj.id.au; c...@kaod.org;
> bbrezil...@kernel.org; devicet...@vger.kernel.org;
> linux-kernel@vger.
Hi Rob,
> -Original Message-
> From: Rob Herring
> Sent: Friday, November 6, 2020 2:41 AM
> To: Chin-Ting Kuo
> Cc: broo...@kernel.org; j...@jms.id.au; and...@aj.id.au; c...@kaod.org;
> bbrezil...@kernel.org; devicet...@vger.kernel.org;
> linux-kernel@vger.
Hi Mark,
> -Original Message-
> From: Mark Brown
> Sent: Friday, November 6, 2020 12:43 AM
> To: Boris Brezillon
> Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller
> driver
>
> On Thu, Nov 05, 2020 at 04:11:32PM +0100, Boris Brezillon wrote:
> > Cédric Le Goater
Hi Boris,
Thanks for your quick reply.
> -Original Message-
> From: Boris Brezillon
> Sent: Thursday, November 5, 2020 11:12 PM
> To: Cédric Le Goater ; robh...@kernel.org
> Cc: Chin-Ting Kuo ; broo...@kernel.org;
> j...@jms.id.au; and...@aj.id.au; bbrezil...@ker
Hi C,
Thanks for your reply.
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, November 5, 2020 10:09 PM
> To: Chin-Ting Kuo ; broo...@kernel.org;
> robh...@kernel.org; j...@jms.id.au; and...@aj.id.au; bbrezil...@kernel.org;
> devicet...@vger.kernel
- Enable FMC CS1 and SPI2 CS0 SPI NOR flashes since both of
these two flashes are mounted on AST2600 EVB by default.
- Remove spi-max-frequency setting: 50MHz is usual SPI bus
frequency adopted on AST2600 EVB which has already been
configured in aspeed-g6.dtsi.
Signed-off-by: Chin-Ting Kuo
the controller.
Signed-off-by: Chin-Ting Kuo
---
arch/arm/boot/dts/aspeed-g6.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..8a5c798db54e 100644
--- a/arch/arm/boot
-by: Chin-Ting Kuo
---
v2: Fix sparse warnings reported by kernel test robot .
v3: Fix build warnings with x86 allmodconfig.
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-aspeed.c | 969 +++
3 files changed, 980 insertions
Create binding file with YAML syntax for ASPEED FMC/SPI memory controller.
Signed-off-by: Chin-Ting Kuo
---
.../bindings/spi/aspeed,spi-aspeed.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
reported by kernel test robot .
v3: Fix build warnings with x86 allmodconfig.
Chin-Ting Kuo (4):
dt-bindings: spi: Add binding file for ASPEED FMC/SPI memory
controller
ARM: dts: aspeed: ast2600: Update FMC/SPI controller setting for
spi-aspeed.c
ARM: dts: aspeed: ast2600-evb: Adjust SPI
Hi Mark,
Thanks for your comment.
> -Original Message-
> From: Mark Brown
> Sent: Thursday, November 5, 2020 4:40 AM
> To: Chin-Ting Kuo
> Cc: robh...@kernel.org; j...@jms.id.au; and...@aj.id.au; c...@kaod.org;
> bbrezil...@kernel.org; devicet...@vger.kernel.o
-by: Chin-Ting Kuo
---
v2: Fix sparse warnings reported by kernel test robot .
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-aspeed.c | 969 +++
3 files changed, 980 insertions(+)
create mode 100644 drivers/spi/spi
the controller.
Signed-off-by: Chin-Ting Kuo
---
arch/arm/boot/dts/aspeed-g6.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..8a5c798db54e 100644
--- a/arch/arm/boot
Create binding file with YAML syntax for ASPEED FMC/SPI memory controller.
Signed-off-by: Chin-Ting Kuo
---
.../bindings/spi/aspeed,spi-aspeed.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
- Enable FMC CS1 and SPI2 CS0 SPI NOR flashes since both of
these two flashes are mounted on AST2600 EVB by default.
- Remove spi-max-frequency setting: 50MHz is usual SPI bus
frequency adopted on AST2600 EVB which has already been
configured in aspeed-g6.dtsi.
Signed-off-by: Chin-Ting Kuo
reported by kernel test robot .
Chin-Ting Kuo (4):
dt-bindings: spi: Add binding file for ASPEED FMC/SPI memory
controller
ARM: dts: aspeed: ast2600: Update FMC/SPI controller setting for
spi-aspeed.c
ARM: dts: aspeed: ast2600-evb: Adjust SPI flash configuration
spi: aspeed: Add ASPEED
-by: Chin-Ting Kuo
---
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-aspeed.c | 967 +++
3 files changed, 978 insertions(+)
create mode 100644 drivers/spi/spi-aspeed.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
This patch series aims to porting ASPEED FMC/SPI memory controller
driver with spi-mem interface. Adjust device tree setting of SPI NOR
flash in order to fit real AST2600 EVB and new SPI memory controller
driver. Also, this patch has been verified on AST2600-A1 EVB.
Chin-Ting Kuo (4):
dt
the controller.
Signed-off-by: Chin-Ting Kuo
---
arch/arm/boot/dts/aspeed-g6.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..8a5c798db54e 100644
--- a/arch/arm/boot
- Enable FMC CS1 and SPI2 CS0 SPI NOR flashes since both of
these two flashes are mounted on AST2600 EVB by default.
- Remove spi-max-frequency setting: 50MHz is usual SPI bus
frequency adopted on AST2600 EVB which has already been
configured in aspeed-g6.dtsi.
Signed-off-by: Chin-Ting Kuo
Create binding file with YAML syntax for ASPEED FMC/SPI memory controller.
Signed-off-by: Chin-Ting Kuo
---
.../bindings/spi/aspeed,spi-aspeed.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
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