The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
ments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
ARM: l2x0: support parity-enable/disable on aurora
dt-bindings: ARM: document marvell,ecc-enable binding
ARM: l2x0: add marvell,ecc-enable property for aurora
EDAC: armada_xp: Add support for more SoCs
Jan Luebbe (5):
ARM: l2c:
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
ments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
ARM: l2x0: support parity-enable/disable on aurora
dt-bindings: ARM: document marvell,ecc-enable binding
ARM: l2x0: add marvell,ecc-enable property for aurora
EDAC: armada_xp: Add support for more SoCs
Jan Luebbe (5):
ARM: l2c:
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
On 10/11/18 4:58 AM, Arnd Bergmann wrote:
> On Fri, Nov 9, 2018 at 12:48 PM Russell King - ARM Linux
> wrote:
>>
>> On Fri, Nov 09, 2018 at 12:40:06PM +0100, Arnd Bergmann wrote:
>>> On Fri, Nov 9, 2018 at 8:04 AM Chris Packham
>>> wrote:
>>>>
&
On 10/11/18 4:58 AM, Arnd Bergmann wrote:
> On Fri, Nov 9, 2018 at 12:48 PM Russell King - ARM Linux
> wrote:
>>
>> On Fri, Nov 09, 2018 at 12:40:06PM +0100, Arnd Bergmann wrote:
>>> On Fri, Nov 9, 2018 at 8:04 AM Chris Packham
>>> wrote:
>>>>
&
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
Add documentation for the marvell,ecc-enable and marvell,ecc-disable
properties which can be used to enable/disable ECC on the Marvell aurora
cache.
Signed-off-by: Chris Packham
---
Notes:
Changes in v6:
- new (split binding doc from implementation).
Documentation/devicetree/bindings
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
Add documentation for the marvell,ecc-enable and marvell,ecc-disable
properties which can be used to enable/disable ECC on the Marvell aurora
cache.
Signed-off-by: Chris Packham
---
Notes:
Changes in v6:
- new (split binding doc from implementation).
Documentation/devicetree/bindings
nt by Chris)
- L2 cache: Split error injection from the check function (review comment by
Chris)
- DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by
Chris)
- Use of_match_ptr() (review comments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
ARM: l2x0: suppor
nt by Chris)
- L2 cache: Split error injection from the check function (review comment by
Chris)
- DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by
Chris)
- Use of_match_ptr() (review comments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
ARM: l2x0: suppor
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
Add a "invert-pwm" device-tree property to allow hardware designs to use
inverted logic on the PWM output. We intentionally preserve the invert
PWM output bit if the property is not found to allow for
bootloaders/bios which may have configured this earlier.
Signed-off-by: Chr
With the addition of the invert-pwm property the adt7475 needs its own
binding documentation rather being captured under trivial-devices.txt.
Signed-off-by: Chris Packham
---
.../devicetree/bindings/hwmon/adt7475.txt | 22 +++
.../devicetree/bindings/trivial-devices.txt
Add a "invert-pwm" device-tree property to allow hardware designs to use
inverted logic on the PWM output. We intentionally preserve the invert
PWM output bit if the property is not found to allow for
bootloaders/bios which may have configured this earlier.
Signed-off-by: Chr
With the addition of the invert-pwm property the adt7475 needs its own
binding documentation rather being captured under trivial-devices.txt.
Signed-off-by: Chris Packham
---
.../devicetree/bindings/hwmon/adt7475.txt | 22 +++
.../devicetree/bindings/trivial-devices.txt
ris)
- Minor checkpatch cleanups
Chris Packham (3):
ARM: l2x0: support parity-enable/disable on aurora
ARM: l2x0: add marvell,ecc-enable property for aurora
EDAC: armada_xp: Add support for more SoCs
Jan Luebbe (5):
ARM: l2c: move cache-aurora-l2.h to asm/hardware
ARM: aurora-l2: add p
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
ris)
- Minor checkpatch cleanups
Chris Packham (3):
ARM: l2x0: support parity-enable/disable on aurora
ARM: l2x0: add marvell,ecc-enable property for aurora
EDAC: armada_xp: Add support for more SoCs
Jan Luebbe (5):
ARM: l2c: move cache-aurora-l2.h to asm/hardware
ARM: aurora-l2: add p
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
MAINTAINERS
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
MAINTAINERS
This board has a Micron MT29F8G08ABACAWP chip which requires a ECC
strength of 8/512. Rather than hard coding any particular strength the
the nand controller auto-detect the ECC strength based on the ONFI data.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-385-db-88f6820-amc.dts | 2
This board has a Micron MT29F8G08ABACAWP chip which requires a ECC
strength of 8/512. Rather than hard coding any particular strength the
the nand controller auto-detect the ECC strength based on the ONFI data.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-385-db-88f6820-amc.dts | 2
On 24/09/18 21:54, Olof Johansson wrote:
> On Fri, Sep 21, 2018 at 12:05:48PM +0200, Gregory CLEMENT wrote:
>> Hi Chris,
>>
>> On jeu., juil. 26 2018, Chris Packham
>> wrote:
>>
>>> We need to maintain backwards compatibility with device tr
On 24/09/18 21:54, Olof Johansson wrote:
> On Fri, Sep 21, 2018 at 12:05:48PM +0200, Gregory CLEMENT wrote:
>> Hi Chris,
>>
>> On jeu., juil. 26 2018, Chris Packham
>> wrote:
>>
>>> We need to maintain backwards compatibility with device tr
On 21/09/18 03:57, Gregory CLEMENT wrote:
> Hi Chris,
>
> On jeu., juil. 26 2018, Chris Packham
> wrote:
>
>> This series updates the armada-xp-98dx3236 SoC and related boards to use the
>> new style dts bindings for nand.
>>
>> I've also added a new
On 21/09/18 03:57, Gregory CLEMENT wrote:
> Hi Chris,
>
> On jeu., juil. 26 2018, Chris Packham
> wrote:
>
>> This series updates the armada-xp-98dx3236 SoC and related boards to use the
>> new style dts bindings for nand.
>>
>> I've also added a new
On 02/08/18 23:05, Will Deacon wrote:
> On Thu, Aug 02, 2018 at 09:45:26AM +1200, Chris Packham wrote:
>> GCC warns
>>
>>arm_pmu_platform.c:234:5: error: 'err' may be used uninitialized in this
>> function [-Werror=maybe-uninitialized]
>>
>> This is b
On 02/08/18 23:05, Will Deacon wrote:
> On Thu, Aug 02, 2018 at 09:45:26AM +1200, Chris Packham wrote:
>> GCC warns
>>
>>arm_pmu_platform.c:234:5: error: 'err' may be used uninitialized in this
>> function [-Werror=maybe-uninitialized]
>>
>> This is b
would not be running.
Initialise err to 0 to avoid the warning.
Signed-off-by: Chris Packham
---
This has been reported before in https://lkml.org/lkml/2018/3/5/508 I'm not
sure if it was dismmissed as "meh, gcc is wrong" or if it was just wainting for
someone with some round tuits.
dr
would not be running.
Initialise err to 0 to avoid the warning.
Signed-off-by: Chris Packham
---
This has been reported before in https://lkml.org/lkml/2018/3/5/508 I'm not
sure if it was dismmissed as "meh, gcc is wrong" or if it was just wainting for
someone with some round tuits.
dr
Update the 98dx3236 SoC and dependent boards to use
"nand-controller" instead of "nand".
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +-
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg
Update the 98dx3236 SoC and dependent boards to use
"nand-controller" instead of "nand".
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +-
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
b/arch/arm/boot/dts/armada-xp-db
This board is a plugin card for some of Marvell's switch development
kits. It's similar to the non-amc board except that it has no SATA
support.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/armada-385-db-88f6820-amc.dts| 147
be used if you disable the internal CPU on
those platforms.
Chris Packham (4):
ARM: dts: mvebu: 98dx3236: Rename nand controller node
ARM: dts: mvebu: db-dxbc2: use new style nand binding
ARM: dts: mvebu: db-xc3-24g4: use new style nand binding
ARM: dts: mvebu: Add device tree for db-88f6820
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
b/arch/arm/boot/dts/armada-xp-db
This board is a plugin card for some of Marvell's switch development
kits. It's similar to the non-amc board except that it has no SATA
support.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/armada-385-db-88f6820-amc.dts| 147
be used if you disable the internal CPU on
those platforms.
Chris Packham (4):
ARM: dts: mvebu: 98dx3236: Rename nand controller node
ARM: dts: mvebu: db-dxbc2: use new style nand binding
ARM: dts: mvebu: db-xc3-24g4: use new style nand binding
ARM: dts: mvebu: Add device tree for db-88f6820
() and override whatever
arm_dt_init_cpu_maps() had configured. Now we move the initial
assignment of default smp_ops to a dt_fixup and let
arm_dt_init_cpu_maps() override that if the device tree defines an
enable-method.
Signed-off-by: Chris Packham
---
Pervious versions
v1:
http
() and override whatever
arm_dt_init_cpu_maps() had configured. Now we move the initial
assignment of default smp_ops to a dt_fixup and let
arm_dt_init_cpu_maps() override that if the device tree defines an
enable-method.
Signed-off-by: Chris Packham
---
Pervious versions
v1:
http
Hi Boris,
On 07/07/18 09:37, Boris Brezillon wrote:
> On Fri, 6 Jul 2018 21:27:20 +0200
> Boris Brezillon wrote:
>
>> On Mon, 25 Jun 2018 10:44:42 +1200
>> Chris Packham wrote:
>>
>>> Hi,
>>>
>>> I'm looking at adding support for the Micron
Hi Boris,
On 07/07/18 09:37, Boris Brezillon wrote:
> On Fri, 6 Jul 2018 21:27:20 +0200
> Boris Brezillon wrote:
>
>> On Mon, 25 Jun 2018 10:44:42 +1200
>> Chris Packham wrote:
>>
>>> Hi,
>>>
>>> I'm looking at adding support for the Micron
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add doc comment and review from
Some Micron NAND chips have on-die ECC forceably enabled. Detect these
based on chip ID as there seems to be no other way of distinguishing
these chips from those that have optional support for on-die ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Add defines for the ONFI version bits and use them in
nand_flash_detect_onfi().
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Changes in v5:
- Add review from Boris
Changes in v6:
- None
drivers/mtd/nand/raw/nand_base.c | 10 +-
include/linux/mtd
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add doc comment and review from
Some Micron NAND chips have on-die ECC forceably enabled. Detect these
based on chip ID as there seems to be no other way of distinguishing
these chips from those that have optional support for on-die ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Add defines for the ONFI version bits and use them in
nand_flash_detect_onfi().
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Changes in v5:
- Add review from Boris
Changes in v6:
- None
drivers/mtd/nand/raw/nand_base.c | 10 +-
include/linux/mtd
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
This is now
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
This is now
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- None
drivers/mtd/nand/
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- None
drivers/mtd/nand/
patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Series changes in v6:
- Update commit message on 6/6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawnand: add defines for ONFI
patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Series changes in v6:
- Update commit message on 6/6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawnand: add defines for ONFI
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, expand
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, expand
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- N
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- N
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes
.
Signed-off-by: Chris Packham
---
Notes:
Changes in v4:
- New
Changes in v5:
- fail if on-die ECC is mandatory and the current ecc.mode is not
NAND_ECC_ON_DIE.
drivers/mtd/nand/raw/nand_micron.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes
.
Signed-off-by: Chris Packham
---
Notes:
Changes in v4:
- New
Changes in v5:
- fail if on-die ECC is mandatory and the current ecc.mode is not
NAND_ECC_ON_DIE.
drivers/mtd/nand/raw/nand_micron.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add doc
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add doc
patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawnand: add defines for ONFI version bits
mtd: rawnand: micron: add fixup for O
patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawnand: add defines for ONFI version bits
mtd: rawnand: micron: add fixup for O
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
---
Notes:
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, expand
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