Hi Chanwoo Choi
Thanks for your help, I am going to post V7 next week base on these
latest extcon patch.
Regards
Chris Zhong
On 07/22/2016 05:29 PM, Chanwoo Choi wrote:
Hi Chris,
I'm sorry for late reply. I finished the first draft to support the extcon
property.
You can check the patches
Hi Chanwoo Choi
Thanks for your help, I am going to post V7 next week base on these
latest extcon patch.
Regards
Chris Zhong
On 07/22/2016 05:29 PM, Chanwoo Choi wrote:
Hi Chris,
I'm sorry for late reply. I finished the first draft to support the extcon
property.
You can check the patches
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
Acked-
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
Acked-by: Mark Yao
---
Changes in v6.1:
- correct the path
-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v6:
- delete the support of PIN_ASSIGN_A/B
- set the default mode to MODE_DFP_USB
- disable DP PLL at USB3 only mode
Changes in v5:
- support get property from extcon
- remove PI
-by: Chris Zhong
Signed-off-by: Kever Yang
---
Changes in v6:
- delete the support of PIN_ASSIGN_A/B
- set the default mode to MODE_DFP_USB
- disable DP PLL at USB3 only mode
Changes in v5:
- support get property from extcon
- remove PIN ASSIGN A/B support
Changes in v4:
- select EXTCON
- use phy
not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (6):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk3399
arm64: dts: rockchip: a
not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (6):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk3399
arm64: dts: rockchip: a
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Tomasz Figa <tf...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
-
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong
Reviewed-by: Tomasz Figa
Reviewed-by: Kever Yang
Acked-by: Rob Herring
---
Changes in v6:
- add assigned-clocks and assigned-clock-rates
Changes in v5: None
Changes in v4:
- add
There are 2 Type-C phy on RK3399, they are almost same, except the
address of register. They support USB3.0 Type-C and DisplayPort1.3
Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller
and DP controller.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v6
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6:
- add assigned-clocks and assigned-clock-rates
- add power-domains
Changes in v5: None
Changes
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris Zhong <z...@r
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris Zhong
Signed-off
There are 2 Type-C phy on RK3399, they are almost same, except the
address of register. They support USB3.0 Type-C and DisplayPort1.3
Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller
and DP controller.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6:
- add assigned-clocks and assigned-clock-rates
- add power-domains
Changes in v5: None
Changes in v4:
- add a reset node
- support 2 phys
Changes
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
Reviewed-by: Sean Paul
---
Changes in v6:
- add a port struct
- select SND_SOC_HDMI_CODEC
*128. Do not use the internal
divider here, just set all mclk to 128 * sample rate directly.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
sound/soc/rockchip/rockchip_spdif.c | 17 +
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/sound/soc/ro
*128. Do not use the internal
divider here, just set all mclk to 128 * sample rate directly.
Signed-off-by: Chris Zhong
---
sound/soc/rockchip/rockchip_spdif.c | 17 +
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c
b/sound/soc
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v5.2:
- fixed the fw_wait always 0
Changes i
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
Changes in v5.2:
- fixed the fw_wait always 0
Changes in v5.1:
- modify according
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v5.1:
- modify according to Sean Paul's co
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
Changes in v5.1:
- modify according to Sean Paul's comments
Changes in v5
Hi Sean
Thanks for your detailed review. I'm working to modify most of code
according to comment.
And there is reply for some comment
On 07/13/2016 09:59 PM, Sean Paul wrote:
On Tue, Jul 12, 2016 at 8:09 AM, Chris Zhong <z...@rock-chips.com> wrote:
Add support for cdn DP controller
Hi Sean
Thanks for your detailed review. I'm working to modify most of code
according to comment.
And there is reply for some comment
On 07/13/2016 09:59 PM, Sean Paul wrote:
On Tue, Jul 12, 2016 at 8:09 AM, Chris Zhong wrote:
Add support for cdn DP controller which is embedded
Hi Chanwoo Choi
On 07/14/2016 09:15 AM, Chanwoo Choi wrote:
Hi Chris,
[snip]
Thanks,
Chanwoo Choi
There are 4 modes for Type-C DP alt mode:
1) USB host only :
extcon_set_cable_state(edev, EXTCON_USB_HOST, 1);
extcon_set_cable_state(edev, EXTCON_USB, 0);
extcon_set_cable_state(edev,
Hi Chanwoo Choi
On 07/14/2016 09:15 AM, Chanwoo Choi wrote:
Hi Chris,
[snip]
Thanks,
Chanwoo Choi
There are 4 modes for Type-C DP alt mode:
1) USB host only :
extcon_set_cable_state(edev, EXTCON_USB_HOST, 1);
extcon_set_cable_state(edev, EXTCON_USB, 0);
extcon_set_cable_state(edev,
Hi Chanwoo Choi
On 07/14/2016 08:49 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 11:54, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 10:05 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 10:39, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 09:11 AM, Chanwoo Choi wrote
Hi Chanwoo Choi
On 07/14/2016 08:49 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 11:54, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 10:05 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 10:39, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 09:11 AM, Chanwoo Choi wrote
Hi Chanwoo Choi
On 07/13/2016 10:05 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 10:39, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 09:11 AM, Chanwoo Choi wrote:
Hi Chris,
I'm now developing the extcon property on extcon-test branch.
But, it has not been completed.
On next
Hi Chanwoo Choi
On 07/13/2016 10:05 AM, Chanwoo Choi wrote:
Hi Chris,
On 2016년 07월 13일 10:39, Chris Zhong wrote:
Hi Chanwoo Choi
On 07/13/2016 09:11 AM, Chanwoo Choi wrote:
Hi Chris,
I'm now developing the extcon property on extcon-test branch.
But, it has not been completed.
On next
, Chris Zhong wrote:
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris
, Chris Zhong wrote:
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Tomasz Figa <tf...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong
Reviewed-by: Tomasz Figa
Reviewed-by: Kever Yang
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4:
- add a #phy-cells node
Changes in v3:
- use compatible: rockchip,rk3399
lize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk3399
Documentation: bindings: add dt documen
lize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
phy: Add USB Type-C PHY driver for rk3399
Documentation: bindings: add dt documen
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5: None
Changes in v4:
- add a reset node
- support 2 phys
Changes in v3:
- add SoC specific compa
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4:
- add a reset node
- support 2 phys
Changes in v3:
- add SoC specific compatible string
- remove reg = <1>;
Changes in v2
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris Zhong <z...@r
-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v5:
- support get property from extcon
- remove PIN ASSIGN A/B support
Changes in v4:
- select EXTCON
- use phy framework to control the USB3 and DP function
- rename PIN_MAP_ to
Add EXTCON_DISP_DP for the Display external connector. For Type-C
connector the DisplayPort can work as an Alternate Mode(VESA DisplayPort
Alt Mode on USB Type-C Standard). The Type-C support both normal and
flipped orientation, so add a property to extcon.
Signe-off-by: Chris Zhong
Signed-off
-by: Chris Zhong
Signed-off-by: Kever Yang
---
Changes in v5:
- support get property from extcon
- remove PIN ASSIGN A/B support
Changes in v4:
- select EXTCON
- use phy framework to control the USB3 and DP function
- rename PIN_MAP_ to PIN_ASSIGN_
Changes in v3:
- remove the phy framework(Kishon
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v5:
- alphabetical order
- do not use long, u
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
Changes in v5:
- alphabetical order
- do not use long, use u32 or u64
- return
Before phy init, the detection of phy state should be controlled
manually. After that, we can switch the detection to hardward,
it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end
of phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/d
Before phy init, the detection of phy state should be controlled
manually. After that, we can switch the detection to hardward,
it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end
of phy init.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
1 file
The vopb/vopl switch register of rk3399 mipi is different from rk3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file chan
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/ro
The vopb/vopl switch register of rk3399 mipi is different from rk3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong
Signed-off-by: Mark Yao
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index
At the first time of bind, there is no any panel attach in mipi. Add a
DRM_CONNECTOR_POLL_HPD porperty to detect the panel status, when panel
probe, the dw_mipi_dsi_host_attach would be called, then mipi-dsi will
trigger a event to notify the drm framework.
Signed-off-by: Chris Zhong <z...@r
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 5 +
1 file changed, 5 insertions(+)
diff --git
a/Documen
At the first time of bind, there is no any panel attach in mipi. Add a
DRM_CONNECTOR_POLL_HPD porperty to detect the panel status, when panel
probe, the dw_mipi_dsi_host_attach would be called, then mipi-dsi will
trigger a event to notify the drm framework.
Signed-off-by: Chris Zhong
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 5 +
1 file changed, 5 insertions(+)
diff --git
a/Documentation/devicetree/bindings
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bi
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip
Hi all
This is a bunch of dw-mipi-dsi driver for RK3399 and RK3288, they have
been tested on rk3399 and rk3288 evb board.
This series is based on Mark Yao's branch:
https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23
Chris Zhong (7):
dt-bindings: add rk3399
Hi all
This is a bunch of dw-mipi-dsi driver for RK3399 and RK3288, they have
been tested on rk3399 and rk3288 evb board.
This series is based on Mark Yao's branch:
https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23
Chris Zhong (7):
dt-bindings: add rk3399
-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v4:
- select EXTCON
- use phy framework to control the USB3 and DP function
- rename PIN_MAP_ to PIN_ASSIGN_
Changes in v3:
- remove the phy framework(Kishon Vijay Abraham I)
- add
-by: Chris Zhong
Signed-off-by: Kever Yang
---
Changes in v4:
- select EXTCON
- use phy framework to control the USB3 and DP function
- rename PIN_MAP_ to PIN_ASSIGN_
Changes in v3:
- remove the phy framework(Kishon Vijay Abraham I)
- add parentheses around the macro
- use a single space between
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v4:
- use phy framework to control DP phy
- sup
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
Changes in v4:
- use phy framework to control DP phy
- support 2 phys
Changes in v3
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4:
- add a reset node
- support 2 phys
Changes in v3:
- add SoC specific compatible string
- rem
), the default
Assignment is A(for DP only mode) or B(for DP + USB3 mode).
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v4:
- remove DP alt mode
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/extcon/extcon.c | 5 +
include/linux/extcon.h | 5 +
2
con API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PH
), the default
Assignment is A(for DP only mode) or B(for DP + USB3 mode).
Signed-off-by: Chris Zhong
---
Changes in v4:
- remove DP alt mode
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/extcon/extcon.c | 5 +
include/linux/extcon.h | 5 +
2 files changed, 10 insertions
con API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation: bindings: add dt doc for Rockchip USB Type-C PH
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4:
- add a reset node
- support 2 phys
Changes in v3:
- add SoC specific compatible string
- remove reg = <1>;
Changes in v2: None
Changes in v1:
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Tomasz Figa <tf...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
-
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong
Reviewed-by: Tomasz Figa
Reviewed-by: Kever Yang
Acked-by: Rob Herring
---
Changes in v4:
- add a #phy-cells node
Changes in v3:
- use compatible: rockchip,rk3399-typec-phy
- use
Hi Guenter
On 06/27/2016 12:01 PM, Guenter Roeck wrote:
On Sun, Jun 26, 2016 at 7:19 PM, Chris Zhong <z...@rock-chips.com> wrote:
Hi Heiko
On 06/25/2016 03:39 AM, Heiko Stuebner wrote:
Am Donnerstag, 23. Juni 2016, 18:27:52 schrieb Kishon Vijay Abraham I:
Hi,
On Thursday 23 June 2
Hi Guenter
On 06/27/2016 12:01 PM, Guenter Roeck wrote:
On Sun, Jun 26, 2016 at 7:19 PM, Chris Zhong wrote:
Hi Heiko
On 06/25/2016 03:39 AM, Heiko Stuebner wrote:
Am Donnerstag, 23. Juni 2016, 18:27:52 schrieb Kishon Vijay Abraham I:
Hi,
On Thursday 23 June 2016 06:21 PM, Chris Zhong
Hi Heiko
On 06/25/2016 03:39 AM, Heiko Stuebner wrote:
Am Donnerstag, 23. Juni 2016, 18:27:52 schrieb Kishon Vijay Abraham I:
Hi,
On Thursday 23 June 2016 06:21 PM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3
Hi Heiko
On 06/25/2016 03:39 AM, Heiko Stuebner wrote:
Am Donnerstag, 23. Juni 2016, 18:27:52 schrieb Kishon Vijay Abraham I:
Hi,
On Thursday 23 June 2016 06:21 PM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3
Hi Guenter
On 06/24/2016 10:10 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:34 PM, Chris Zhong <z...@rock-chips.com> wrote:
Hi Guenter
On 06/24/2016 05:47 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:51 AM, Chris Zhong <z...@rock-chips.com>
Hi Guenter
On 06/24/2016 10:10 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:34 PM, Chris Zhong wrote:
Hi Guenter
On 06/24/2016 05:47 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:51 AM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type
Hi Guenter
On 06/24/2016 05:47 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:51 AM, Chris Zhong <z...@rock-chips.com> wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basical
Hi Guenter
On 06/24/2016 05:47 AM, Guenter Roeck wrote:
Hi Chris,
On Thu, Jun 23, 2016 at 5:51 AM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basically has two main components
description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation:
description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line
Chris Zhong (5):
extcon: Add Type-C and DP support
Documentation:
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3:
- use EXTCON_DISP_DP and EXTCON_DISP_DP_ALT
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
Changes in v3:
- use EXTCON_DISP_DP and EXTCON_DISP_DP_ALT cable to get dp port state
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3:
- add SoC specific compatible string
- remove reg = <1>;
Changes in v2: None
Changes in v1:
- add extcon node description
- add #sou
-by: Chris Zhong <z...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- remove the phy framework(Kishon Vijay Abraham I)
- add parentheses around the macro
- use a single space between type and name
- add spaces after opening and before closing b
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Tomasz Figa <tf...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- use compatible: rockchip,rk33
is
attached, Type-C get Pin_Assignment_C(for DP only mode) or
Pin_Assignment_D(for DP alt mode), the default Assignment is A or B.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/extcon/extcon.c | 6 ++
include
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
---
Changes in v3:
- add SoC specific compatible string
- remove reg = <1>;
Changes in v2: None
Changes in v1:
- add extcon node description
- add #sound-dai-cells description
.../bi
-by: Chris Zhong
Signed-off-by: Kever Yang
---
Changes in v3:
- remove the phy framework(Kishon Vijay Abraham I)
- add parentheses around the macro
- use a single space between type and name
- add spaces after opening and before closing braces.
- use u16 for register value
- remove type-c phy header
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong
Reviewed-by: Tomasz Figa
Reviewed-by: Kever Yang
---
Changes in v3:
- use compatible: rockchip,rk3399-typec-phy
- use dashes instead of underscores.
Changes in v2:
- add some registers
is
attached, Type-C get Pin_Assignment_C(for DP only mode) or
Pin_Assignment_D(for DP alt mode), the default Assignment is A or B.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/extcon/extcon.c | 6 ++
include/linux/extcon.h | 6 ++
2
Hi Tomasz
Thanks for your comments.
I will modify all the the part of snip. Please find my reply in the
following.
On 06/18/2016 12:06 AM, Tomasz Figa wrote:
Hi Chris,
[snip]
+struct phy_reg {
+ int value;
+ int addr;
+};
+
+struct phy_reg usb_pll_cfg[] = {
+ {0xf0,
Hi Tomasz
Thanks for your comments.
I will modify all the the part of snip. Please find my reply in the
following.
On 06/18/2016 12:06 AM, Tomasz Figa wrote:
Hi Chris,
[snip]
+struct phy_reg {
+ int value;
+ int addr;
+};
+
+struct phy_reg usb_pll_cfg[] = {
+ {0xf0,
Hi Guenter
On 06/18/2016 11:45 PM, Guenter Roeck wrote:
Hi Chris,
On Mon, Jun 13, 2016 at 2:39 AM, Chris Zhong <z...@rock-chips.com> wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basical
Hi Guenter
On 06/18/2016 11:45 PM, Guenter Roeck wrote:
Hi Chris,
On Mon, Jun 13, 2016 at 2:39 AM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basically has two main components
Hi Kishon
On 06/17/2016 08:54 PM, Kishon Vijay Abraham I wrote:
On Monday 13 June 2016 03:09 PM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basically has two main components: USB3
Hi Kishon
On 06/17/2016 08:54 PM, Kishon Vijay Abraham I wrote:
On Monday 13 June 2016 03:09 PM, Chris Zhong wrote:
Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications. The
PHY basically has two main components: USB3
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