[PATCH] Documentation: Note QDF2400 SoC Erratum 44

of checking that the BUSY bit is 1, works around the issue. Note this in the customary location. To minimize conflicts, this documentation update is separate from the code changes, "tty: pl011: Work around QDF2400 E44 stuck BUSY bit". Signed-off-by: Christopher Covington <c...@codeauro

[PATCH] Documentation: Note QDF2400 SoC Erratum 44

of checking that the BUSY bit is 1, works around the issue. Note this in the customary location. To minimize conflicts, this documentation update is separate from the code changes, "tty: pl011: Work around QDF2400 E44 stuck BUSY bit". Signed-off-by: Christopher Covington Acked-by: Ru

[PATCH v4] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

and early_write functions. Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington &l

[PATCH v4] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

and early_write functions. Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington Acked

Re: [PATCH v3] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/15/2017 03:07 PM, Greg Kroah-Hartman wrote: > On Wed, Feb 15, 2017 at 07:50:27PM +, Mark Rutland wrote: >> On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote: >>> Due to known (although trivial) conflicts in silicon-errata.txt, based on >>>

Re: [PATCH v3] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/15/2017 03:07 PM, Greg Kroah-Hartman wrote: > On Wed, Feb 15, 2017 at 07:50:27PM +, Mark Rutland wrote: >> On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote: >>> Due to known (although trivial) conflicts in silicon-errata.txt, based on >>>

[PATCH v3] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

and early_write functions. Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington &l

[PATCH v3] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

and early_write functions. Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington Acked

Re: [PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 2017-02-14 21:39, Timur Tabi wrote: Christopher Covington wrote: The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1

Re: [PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 2017-02-14 21:39, Timur Tabi wrote: Christopher Covington wrote: The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1

[PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington <c...@codeaurora.org> Acked-by: Russell King &l

[PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington Acked-by: Russell King --- Changes in v2: * Improved

Re: [PATCH 2/2] tty: pl011: Work around QDF2400 E44 for earlycon

On 02/07/2017 11:31 PM, Shanker Donthineni wrote: > Hi Cov, > > The same PL011 driver will be used in virtutal machine, make sure > your changes have no side effects in VM. Fundamentally, this is the same workaround as has been tested in the qserver downstream kernel for over a year. Cheers,

Re: [PATCH 2/2] tty: pl011: Work around QDF2400 E44 for earlycon

On 02/07/2017 11:31 PM, Shanker Donthineni wrote: > Hi Cov, > > The same PL011 driver will be used in virtutal machine, make sure > your changes have no side effects in VM. Fundamentally, this is the same workaround as has been tested in the qserver downstream kernel for over a year. Cheers,

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/08/2017 06:04 PM, Timur Tabi wrote: > On 02/08/2017 04:22 PM, Christopher Covington wrote: >>>> >> -while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) >>>> >> +while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/08/2017 06:04 PM, Timur Tabi wrote: > On 02/08/2017 04:22 PM, Christopher Covington wrote: >>>> >> -while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) >>>> >> +while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/07/2017 11:05 PM, Timur Tabi wrote: > Christopher Covington wrote: >> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a >> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the >> BUSY bit in the Flag Register gets stuck as 1

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On 02/07/2017 11:05 PM, Timur Tabi wrote: > Christopher Covington wrote: >> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a >> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the >> BUSY bit in the Flag Register gets stuck as 1

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

Hi, On 02/08/2017 08:27 AM, Timur Tabi wrote: > Robin Murphy wrote: >> Is there a reason anyone would ever want to turn this off? AFAICS you >> save a few dozen bytes in return for a kernel image which you know won't >> work properly on some hardware. That doesn't seem particularly >> worthwhile,

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

Hi, On 02/08/2017 08:27 AM, Timur Tabi wrote: > Robin Murphy wrote: >> Is there a reason anyone would ever want to turn this off? AFAICS you >> save a few dozen bytes in return for a kernel image which you know won't >> work properly on some hardware. That doesn't seem particularly >> worthwhile,

Re: [PATCH v6] arm64: Work around Falkor erratum 1003

On 02/08/2017 11:34 AM, Catalin Marinas wrote: > On Tue, Feb 07, 2017 at 07:35:16PM -0500, Christopher Covington wrote: >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -480,6 +480,18 @@ config CAVIUM_ERRATUM_27456 >> >>

Re: [PATCH v6] arm64: Work around Falkor erratum 1003

On 02/08/2017 11:34 AM, Catalin Marinas wrote: > On Tue, Feb 07, 2017 at 07:35:16PM -0500, Christopher Covington wrote: >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -480,6 +480,18 @@ config CAVIUM_ERRATUM_27456 >> >>

[PATCH v7] arm64: Work around Falkor erratum 1003

ora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 18 ++ arch/arm64/include/asm/assembler.h | 23 +++ arch/arm64/include/asm/cpucaps.h

[PATCH v7] arm64: Work around Falkor erratum 1003

-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 18 ++ arch/arm64/include/asm/assembler.h | 23 +++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/mmu_context.h

[PATCH 2/2] tty: pl011: Work around QDF2400 E44 for earlycon

is available, the implementation is different than in the preceding patch. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- drivers/tty/serial/amba-pl011.c | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/amba-pl0

[PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

is available, and does not handle the erratum for earlycon, as the UAP data is not available then. Signed-off-by: Christopher Covington <c...@codeaurora.org> Acked-by: Russell King <rmk+ker...@armlinux.org.uk> --- Changes between the previous RFC [1] and this PATCH: * don't use arch/

[PATCH 2/2] tty: pl011: Work around QDF2400 E44 for earlycon

is available, the implementation is different than in the preceding patch. Signed-off-by: Christopher Covington --- drivers/tty/serial/amba-pl011.c | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba

[PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

is available, and does not handle the erratum for earlycon, as the UAP data is not available then. Signed-off-by: Christopher Covington Acked-by: Russell King --- Changes between the previous RFC [1] and this PATCH: * don't use arch/arm64/kernel/cpu_errata.c at Will's request * separate out earlycon case

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 02/01/2017 01:38 PM, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: >>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 02/01/2017 01:38 PM, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: >>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin

[PATCH v6] arm64: Work around Falkor erratum 1003

ora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 12 arch/a

[PATCH v6] arm64: Work around Falkor erratum 1003

-off-by: Christopher Covington --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 12 arch/arm64/include/asm/assembler.h | 23 +++ arch/a

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 12:56 PM, Marc Zyngier wrote: > On 31/01/17 17:48, Christopher Covington wrote: >> On 01/31/2017 07:37 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >>>> The Qualcomm Datacenter Technologies Falkor v

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 12:56 PM, Marc Zyngier wrote: > On 31/01/17 17:48, Christopher Covington wrote: >> On 01/31/2017 07:37 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >>>> The Qualcomm Datacenter Technologies Falkor v

[PATCH v6] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> Acked-by: Mark Rutland <mark.rutl...@arm.com> -

[PATCH v6] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni Signed-off-by: Christopher Covington Acked-by: Mark Rutland --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 07:37 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >&g

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 07:37 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >&g

Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009

On 01/31/2017 09:38 AM, Will Deacon wrote: > On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote: >> diff --git a/arch/arm64/include/asm/tlbflush.h >> b/arch/arm64/include/asm/tlbflush.h >> index deab52374119..fc434f421c7b 100644 >> --- a/arch/a

Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009

On 01/31/2017 09:38 AM, Will Deacon wrote: > On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote: >> diff --git a/arch/arm64/include/asm/tlbflush.h >> b/arch/arm64/include/asm/tlbflush.h >> index deab52374119..fc434f421c7b 100644 >> --- a/arch/a

[RFC] tty: pl011: Work around stuck BUSY bit on QDF2400

. Checking that the Transmit FIFO Empty (TXFE) bit is 0, instead of checking that the BUSY bit is 1, works around the issue. To facilitate this substitution, introduce vendor-specific inversion of Feature Register bits. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Based on

[RFC] tty: pl011: Work around stuck BUSY bit on QDF2400

. Checking that the Transmit FIFO Empty (TXFE) bit is 0, instead of checking that the BUSY bit is 1, works around the issue. To facilitate this substitution, introduce vendor-specific inversion of Feature Register bits. Signed-off-by: Christopher Covington --- Based on https://git.kernel.org/cgit

[PATCH v5 1/2] arm64: Work around Falkor erratum 1003

ora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++ arch/arm64/include

[PATCH v5 1/2] arm64: Work around Falkor erratum 1003

-off-by: Christopher Covington --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++ arch/arm64/include/asm/assembler.h | 23 +++ arch/a

[PATCH v5 2/2] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Based on https://git.kernel.org/cgit/linux/kern

[PATCH v5 2/2] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni Signed-off-by: Christopher Covington --- Based on https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/30/2017 05:56 AM, Mark Rutland wrote: > Hi, > > On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: >> On 01/27/2017 09:38 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > >&g

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/30/2017 05:56 AM, Mark Rutland wrote: > Hi, > > On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: >> On 01/27/2017 09:38 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > >&g

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/27/2017 09:38 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/27/2017 09:38 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum

[PATCH v4 2/4] arm64: Work around Falkor erratum 1003

ora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++ arch/arm64/include/asm/assembler.h | 23 +++ arch/arm64/include/asm/cpucaps.h | 3

[PATCH v4 2/4] arm64: Work around Falkor erratum 1003

-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++ arch/arm64/include/asm/assembler.h | 23 +++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/mmu_context.h | 8 +++-

[PATCH v4 1/4] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v4 4/4] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 +

[PATCH v4 1/4] arm64: Define Falkor v1 CPU

From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/include/asm/cputype.h | 4 1

[PATCH v4 4/4] arm64: Work around Falkor erratum 1009

), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni Signed-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++ arch

[PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b938f0..e8e7ba2bc11f 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/k

[PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

-by: Christopher Covington --- arch/arm64/kvm/hyp/tlb.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b938f0..e8e7ba2bc11f 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -16,6 +16,7

Re: [PATCH v20 08/17] clocksource/drivers/arm_arch_timer: Rework counter frequency detection.

Hi Fu, On 01/25/2017 01:46 AM, Fu Wei wrote: > Hi Mark, > > On 25 January 2017 at 01:24, Mark Rutland wrote: >> On Wed, Jan 18, 2017 at 09:25:32PM +0800, fu@linaro.org wrote: >>> From: Fu Wei >>> >>> The counter frequency detection

Re: [PATCH v20 08/17] clocksource/drivers/arm_arch_timer: Rework counter frequency detection.

Hi Fu, On 01/25/2017 01:46 AM, Fu Wei wrote: > Hi Mark, > > On 25 January 2017 at 01:24, Mark Rutland wrote: >> On Wed, Jan 18, 2017 at 09:25:32PM +0800, fu@linaro.org wrote: >>> From: Fu Wei >>> >>> The counter frequency detection call(arch_timer_detect_rate) combines two >>> ways to get

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/13/2017 11:12 AM, Will Deacon wrote: > On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote: >> On 01/12/2017 11:58 AM, Will Deacon wrote: >>> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >>>> +#define __tlbi

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/13/2017 11:12 AM, Will Deacon wrote: > On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote: >> On 01/12/2017 11:58 AM, Will Deacon wrote: >>> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >>>> +#define __tlbi

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Catalin, On 01/11/2017 01:06 PM, Catalin Marinas wrote: > Some minor comments below, nothing fundamental (as long as you say the > new sequence doesn't have the speculative TLB load problem I mentioned > on a previous version). This workaround is documented as providing functional correctness

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Catalin, On 01/11/2017 01:06 PM, Catalin Marinas wrote: > Some minor comments below, nothing fundamental (as long as you say the > new sequence doesn't have the speculative TLB load problem I mentioned > on a previous version). This workaround is documented as providing functional correctness

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On 01/12/2017 11:12 AM, Mark Rutland wrote: > On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote: >> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote: > >>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0(). >> >> This may be fine if my assumptions about

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On 01/12/2017 11:12 AM, Mark Rutland wrote: > On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote: >> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote: > >>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0(). >> >> This may be fine if my assumptions about

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/11/2017 01:45 PM, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: >> On 01/11/2017 12:37 PM, Mark Rutland wrote: >>> The name, as it is, is perfectly descriptive. >>> >>> Let's not sacrifice legibility over a non-issue. >> >> I don't want to kick a

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/11/2017 01:45 PM, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: >> On 01/11/2017 12:37 PM, Mark Rutland wrote: >>> The name, as it is, is perfectly descriptive. >>> >>> Let's not sacrifice legibility over a non-issue. >> >> I don't want to kick a

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/12/2017 11:58 AM, Will Deacon wrote: > Hi Christopher, > > On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >> This refactoring will allow an errata workaround that repeats tlbi dsb >> sequences to only change one location. This is n

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/12/2017 11:58 AM, Will Deacon wrote: > Hi Christopher, > > On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >> This refactoring will allow an errata workaround that repeats tlbi dsb >> sequences to only change one location. This is n

[PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f

[PATCH v3 2/5] arm64: Work around Falkor erratum 1003

amp;0 ASID is not subject to this erratum because hardware is prohibited from performing translations from an out-of-context translation regime. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/s

[PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

-off-by: Christopher Covington --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f28813c 100644 --- a/arch/arm64

[PATCH v3 2/5] arm64: Work around Falkor erratum 1003

atum because hardware is prohibited from performing translations from an out-of-context translation regime. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 43 +- arch/arm64/Kco

[PATCH v3 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington &l

[PATCH v3 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington

[PATCH v3 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v3 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/include/asm/cputype.h | 4 1

[PATCH v3 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 29 +++-- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..9669e4b 100644 --- a/arch/arm64/k

[PATCH v3 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington --- arch/arm64/kvm/hyp/tlb.c | 29 +++-- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..9669e4b 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

Hi Christoffer, On 01/04/2017 05:33 AM, Christoffer Dall wrote: > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> From: Shanker Donthineni <shank...@codeaurora.org> >> >> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

Hi Christoffer, On 01/04/2017 05:33 AM, Christoffer Dall wrote: > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> From: Shanker Donthineni >> >> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may >> allocate TLB entr

Re: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

On 01/03/2017 10:57 AM, Mark Rutland wrote: > On Thu, Dec 29, 2016 at 05:43:34PM -0500, Christopher Covington wrote: >> Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which >> will allow an errata workaround that repeats tlbi dsb sequences to only >>

Re: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

On 01/03/2017 10:57 AM, Mark Rutland wrote: > On Thu, Dec 29, 2016 at 05:43:34PM -0500, Christopher Covington wrote: >> Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which >> will allow an errata workaround that repeats tlbi dsb sequences to only >>

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 01/03/2017 10:55 AM, Mark Rutland wrote: > Hi, > > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 >> + > >

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 01/03/2017 10:55 AM, Mark Rutland wrote: > Hi, > > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 >> + > >

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:08 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 > > Also, since this can't be changed via the m

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:08 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 > > Also, since this can't be changed via the m

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:02 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> -| Implementor| Component | Erratum ID | Kconfig >>| >> -++-+-+---

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:02 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> -| Implementor| Component | Erratum ID | Kconfig >>| >> -++-+-+---

[PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros

-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f28813c

[PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..66e3f72 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++

[PATCH v2 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington &l

[PATCH v2 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington Change

[PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros

-by: Christopher Covington --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f28813c 100644 --- a/arch/arm64

[PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington --- arch/arm64/kvm/hyp/tlb.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..66e3f72 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c

[PATCH v2 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v2 2/5] arm64: Work around Falkor erratum 1003

<shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 43 +- arch/arm64/Kconfig | 16 + arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/k

[PATCH v2 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/include/asm/cputype.h | 4 1

[PATCH v2 2/5] arm64: Work around Falkor erratum 1003

that there are no TLB entries with incorrect ASID after changing the the ASID. Pseudo code: write TTBRx_EL1[ASID] to a reserved value ISB write TTBRx_EL1[BADDR] to a desired value ISB write TTBRx_EL1[ASID] to a desired value ISB Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington

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