On 03/21/2014 09:33 AM, Andrey Vagin wrote:
> It's required for restoring sockets in closing states:
> TCP_FIN_WAIT{1,2}, TCP_WAIT_STOP, TCP_CLOSING, TCP_LAST_ACK.
>
> A fin packet is restored by sending a control message (ancillary data).
> In which queue a packet is restored depends on a value o
tered.
Signed-off-by: Christopher Covington
---
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 464dcef..afd6dde 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -1891,6 +1891,12 @@ sub pr
device.
EXT2-fs (vda): error: ext2_check_page: bad entry in directory #2: : unaligned
directory entry - offset=0, inode=3755990991, rec_len=57311, name_len=223
To fix this, select ARCH_DMA_ADDR_T_64BIT when both LPAE and
VIRTIO_MMIO are selected.
Signed-off-by: Christopher Covington
---
arch/arm
On 02/14/2014 01:38 PM, Christopher Covington wrote:
> The kcmp system call was ported to ARM in
> commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
> "ARM: 7665/1: Wire up kcmp syscall".
>
> Signed-off-by: Christopher Covington
> ---
> arch/arm/include/asm/unis
-off-by: Christopher Covington
---
arch/arm64/include/asm/uaccess.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 7ecc2b2..5974459 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64
Hi Kumar,
On 03/17/2014 01:33 PM, Kumar Gala wrote:
>
> On Mar 17, 2014, at 12:31 PM, Christopher Covington
> wrote:
>
>> Hi Stephen,
>>
>> On 03/11/2014 05:24 PM, Stephen Boyd wrote:
>>> The architected timer is not a register addressable piece of
>
Hi Stephen,
On 03/11/2014 05:24 PM, Stephen Boyd wrote:
> The architected timer is not a register addressable piece of
> hardware. Instead it's accessed through cp15 accessors. Move it
> to the root of the devicetree to reflect this.
I find this confusing, perhaps due to overloading of the word "
Hi Catalin, Will,
Thanks for your feedback. I must admit I'm out of my depth here, so I just
posted what I had, hoping to solicit comments like what you all have kindly
provided.
On 03/13/2014 07:20 AM, Catalin Marinas wrote:
> On Wed, Mar 05, 2014 at 10:41:28PM +, Christopher C
Hi Michael,
Thanks for the comments.
On 03/06/2014 03:20 AM, Michael S. Tsirkin wrote:
> On Wed, Mar 05, 2014 at 05:41:28PM -0500, Christopher Covington wrote:
>> Without this, the following scenario is incorrectly determined
>> to be invalid.
>>
>> addr 0x7f_ff
Without this, the following scenario is incorrectly determined
to be invalid.
addr 0x7f_e000 size 8192 addr_limit 0x80_
This behavior was observed while trying to vmsplice the stack
as part of a CRIU dump of a process.
Signed-off-by: Christopher Covington
---
arch/arm64/include
On 02/20/2014 11:09 AM, Kumar Gala wrote:
> We've split Qualcomm MSM support into legacy and multiplatform. The RNG
> driver is only relevant on the multiplatform supported SoCs so switch the
> Kconfig depends to ARCH_QCOM.
>
> CC: Herbert Xu
> CC: Stanimir Varbanov
> Signed-off-by: Kumar Gala
The kcmp system call was ported to ARM in
commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
"ARM: 7665/1: Wire up kcmp syscall".
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/unistd.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/unistd.h
Hi Pawel,
On 02/11/2014 11:53 AM, Pawel Moll wrote:
> This patch tries to solve that issue in a generic way,
> adding a "populated" flag which is set in the device_node
> structure when a device is being created in the core.
> Later, of_platform_populate() skips such nodes (and
> its children) in
Hi Georgi,
On 01/30/2014 01:45 PM, Georgi Djakov wrote:
> This patchset adds basic support of the Secure Digital Host Controller
> Interface compliant controller found in Qualcomm chipsets.
>
> Tested with eMMC and various micro SD cards on APQ8074 Dragonboard.
[...]
> .../devicetree/bindings/
On 01/15/2014 12:55 PM, Stephen Boyd wrote:
> Some CPU PMUs are wired up with one PPI for all the CPUs instead
> of with a different SPI for each CPU. Add support for these
> devices.
>
> Signed-off-by: Stephen Boyd
> ---
> arch/arm/kernel/perf_event.c | 14 --
> arch/arm/kernel/perf_eve
Hi Christoffer,
On 02/02/2014 11:56 PM, Christoffer Dall wrote:
> On Thu, Jan 30, 2014 at 11:54:46AM -0500, Christopher Covington wrote:
>> I think it would be informative to provide pointers here to commonly used
>> paravirtualized devices, especially VirtIO PCI/MMIO.
>
> I
Hi Ian,
On 01/30/2014 12:15 PM, Ian Campbell wrote:
> On Thu, 2014-01-30 at 11:54 -0500, Christopher Covington wrote:
>>> +++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
>>> @@ -0,0 +1,32 @@
>>> +* Mach-virt "Dummy Virtual Machine" platfor
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
> mach-virt has existed for a while but it is not written down what it actually
> consists of. Although it seems a bit unusual to document a binding for an
> entire platform since mach-virt is entirely virtual it is helpful to have
> something to
Hi Will,
On 01/29/2014 05:57 AM, Will Deacon wrote:
> Hi Christopher,
>
> On Tue, Jan 28, 2014 at 06:51:51PM +, Christopher Covington wrote:
>> Add the trivial support necessary to get hardware breakpoints
>> working for GDB on ARMv8 simulators running in AArch32 mode.
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Acked-by: Will Deacon
Signed-off-by: Christopher Covington
---
v3: assume for now that ARMv9 and later will update FSR
v2: modify debug_exception_updates_fsr
arch/arm
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington
---
v2: modify debug_exception_updates_fsr
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel/hw_breakpoint.c | 3
On 01/24/2014 12:52 PM, Christopher Covington wrote:
> On 01/24/2014 12:17 PM, Will Deacon wrote:
>> On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
>>> 2014/1/24 Will Deacon :
>>>> Are you sure about this? The value we write is actually task_pid_nr, wh
On 01/24/2014 06:39 AM, Mark Rutland wrote:
> On Thu, Jan 23, 2014 at 07:20:01PM +, Feng Kan wrote:
>> Add documentation for generic SYSCON reboot driver.
>>
>> Signed-off-by: Feng Kan
>> ---
>> .../bindings/power/reset/syscon-reboot.txt | 16
>> 1 files changed, 16
On 01/24/2014 12:17 PM, Will Deacon wrote:
> On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
>> 2014/1/24 Will Deacon :
>>> Are you sure about this? The value we write is actually task_pid_nr, which I
>>> believe to be globally unique.
>>
>> You are right: the task_pid_nr is unique in
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel/hw_breakpoint.c | 1 +
2 files changed, 2 insertions(+)
diff
On 01/17/2014 01:50 PM, Stephen Boyd wrote:
> On 01/06, Christopher Covington wrote:
>> The pgtbl macro couldn't handle the specific
>> (TEXT_OFFSET - PG_DIR_SIZE) value that the combination of
>> MSM platforms and LPAE created:
>>
>> head.S:163: Error:
Hi Josh,
On 01/17/2014 12:26 PM, Josh Cartwright wrote:
[...]
> @@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
> #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
> #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
>
> -#ifdef CONFIG_PM_SLEEP
> +#if defined(CONFIG_PM_SLEE
db.de
> CC: o...@lixom.net
> CC: catalin.mari...@arm.com
Looks good to me.
Acked-by Christopher Covington
While I don't think it should necessarily gate these changes, I wonder if at
some point the config options could be consolidated across the various
architectures using them.
R
forms at run time, make it
at least assemble properly.
Signed-off-by: Christopher Covington
---
arch/arm/kernel/head.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..af30cac 100644
--- a/arch/arm/kernel/head.S
On 12/05/2013 03:16 PM, Greg Kroah-Hartman wrote:
> On Thu, Dec 05, 2013 at 03:12:50PM -0500, Christopher Covington wrote:
[...]
> And adding new features to code that is "dead" and should probably be
> removed isn't a good idea, as I'm sure you can understand.
I wou
Hi Greg,
On 12/04/2013 11:01 PM, Greg Kroah-Hartman wrote:
> On Wed, Dec 04, 2013 at 10:49:25PM -0500, Adrien Vergé wrote:
>> 2013/12/4 Greg Kroah-Hartman :
>>> How much overhead does the existing tracing code have on ARM? Is ETM
>>> still even needed? Why not just use ETM for the core tracing c
Hi Pavel,
On 11/28/2013 12:11 PM, Pavel Machek wrote:
> Hi!
>
> For testing, it would be good to have some real
> userland... unfortunately I can't figure out how to do it.
>
> Ideally, I'd like to put nemo-armv7hl-n900-mmcblk0p.raw on emulated sd
> card, but I get:
>
> [1.566345] Initializ
Hi Catalin,
On 11/18/2013 12:30 PM, Catalin Marinas wrote:
[...]
> You can't run legacy AArch32 code at EL3 and have lower levels in AArch64
> mode (architectural constraint).
What prevents AArch32 code from running at EL3 and then requesting a reset to
AArch64 by writing to the Reset Management
Hi Ivan,
On 11/12/2013 09:51 AM, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> This patch fix compilation error when driver is compiled
> in multi-platform builds.
>
> drivers/built-in.o: In function `msm_otg_link_clk_reset':
> ./drivers/usb/phy/phy-msm-usb.c:314: undefined reference to `c
Hi Stephen,
On 11/07/2013 02:20 PM, Stephen Boyd wrote:
> If we're running on a v7 ARM CPU, detect if the CPU supports the
> sdiv/udiv instructions and replace the signed and unsigned
> division library functions with an sdiv/udiv instruction.
[...]
> +++ b/arch/arm/lib/div-v7.c
> @@ -0,0 +1,58
Put architecture-specific assembly code where it belongs,
allowing for support of additional architectures such as arm64 in
the future.
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/dcc.h | 45 +++
drivers/tty/hvc/hvc_dcc.c | 48
Hi Jiang,
On 09/25/2013 06:44 AM, Jiang Liu wrote:
[...]
> diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
[...]
> +static int aarch64_insn_cls[] = {
> + AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
> + AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
> + AARCH64_INS
On 07/30/2013 06:09 AM, Jean-Francois Moine wrote:
> On Tue, 30 Jul 2013 10:44:57 +0100
> Dave Martin wrote:
>> On Tue, Jul 30, 2013 at 11:38:53AM +0200, Jean-Francois Moine wrote:
>>> On Tue, 30 Jul 2013 10:25:18 +0100
>>> Dave Martin wrote:
The pragmatic route is less contraversial and low
rtions(+), 115 deletions(-)
>
I ran 32-bit and 64-bit kernels with these patches on the Versatile Express
software model and things looked fine, so for the applicable patches,
Tested-by: Christopher Covington
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. i
On 06/26/2013 01:11 PM, Will Deacon wrote:
> On Mon, Jun 24, 2013 at 04:15:06PM +0100, Christopher Covington wrote:
>> On 06/24/2013 10:53 AM, Will Deacon wrote:
>>> On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
>>>> Hi Will,
>>>>
On 06/25/2013 02:11 PM, Leif Lindholm wrote:
> This patch provides documentation of the [U]EFI runtime services and
> configuration features.
>
> Signed-off-by: Leif Lindholm
> ---
> Documentation/arm/00-INDEX |3 +++
> Documentation/arm/uefi.txt | 39 ++
On 06/24/2013 10:53 AM, Will Deacon wrote:
> On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
>> Hi Will,
>>
>> On 06/24/2013 10:04 AM, Will Deacon wrote:
>> [...]
>>
>>> What's the advantage of this approach, other than you ge
Hi Will,
On 06/24/2013 10:04 AM, Will Deacon wrote:
[...]
> What's the advantage of this approach, other than you get an extra byte's
> worth of PID?
In my view, the real advantage is that the the PID is located where people
reading ARM Architecture Reference Manual are told they can find it.
R
Using the long-descriptor translation table format changes
the layout of the CONTEXTIDR register.
Signed-off-by: Christopher Covington
---
arch/arm/mm/context.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mm/context.c b
e timestamps when
> the hardware returns a value instead of 0 upon the first read.
Builds and runs for me on software models.
Tested-by: Christopher Covington
Cheers,
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
Hi Will,
On 06/05/2013 08:50 AM, Will Deacon wrote:
> On Wed, Jun 05, 2013 at 01:44:55PM +0100, Arnd Bergmann wrote:
>> On Wednesday 05 June 2013 13:15:29 Stefano Stabellini wrote:
>>> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
>>> index c95c5cb..79dd13d 100644
>>> --- a/arch/arm64/Mak
> Changes in v3:
> - improve commit description and Kconfig help text;
> - no need to initialize pv_time_ops;
> - add PARAVIRT_TIME_ACCOUNTING.
Looks good to me.
Acked-by: Christopher Covington
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a mem
Hi Pranavkumar,
On 05/13/2013 02:56 AM, Pranavkumar Sawargaonkar wrote:
> Hi Rusty,
>
> On 13 May 2013 08:22, Rusty Russell wrote:
>> Pranavkumar Sawargaonkar writes:
>>> Signed-off-by: Pranavkumar Sawargaonkar
>>> Signed-off-by: Anup Patel
>>> ---
>>> Documentation/virtual/virtio-spec.txt |
Hi Will,
On 05/08/2013 05:06 AM, Will Deacon wrote:
> Hello Christopher,
>
> On Tue, May 07, 2013 at 04:48:26PM +0100, Christopher Covington wrote:
>> On 05/07/2013 05:08 AM, Will Deacon wrote:
>>> That seems like a lot of effort in order to preserve something that isn&#
On 05/08/2013 07:19 AM, Stefano Stabellini wrote:
> On Tue, 7 May 2013, Christopher Covington wrote:
>> Hi Konrad,
>>
>> On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>
Hi Konrad,
On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
>>> where the timer goes off. Nor does it make sense to require that the
>>> gues
On 05/07/2013 08:19 AM, Peter Maydell wrote:
> On 7 May 2013 05:46, Rusty Russell wrote:
>> Peter Maydell writes:
>>> That all looks like sensible QEMU implementation possibilities
>>> but it seems to be a bit of a non-sequitur from "how do we
>>> tell the kernel to actually use this?"
>>
>> You
On 05/07/2013 05:08 AM, Will Deacon wrote:
> On Mon, May 06, 2013 at 07:01:23PM +0100, Christopher Covington wrote:
>> Hi Will,
>>
>> On 05/03/2013 01:35 PM, Will Deacon wrote:
>>> Hi all,
>>>
>>> This small patch set may look a little over a m
Hi Will,
On 05/03/2013 01:35 PM, Will Deacon wrote:
> Hi all,
>
> This small patch set may look a little over a month late, but there is a
> serious reason for posting it.
>
> When I moved the ARM delay loop over to using the architected timers
> rather than the CPU spinning loop (which has all
On 05/05/2013 12:47 PM, Stefano Stabellini wrote:
> On Fri, 3 May 2013, Marc Zyngier wrote:
>> On 03/05/13 11:43, Stefano Stabellini wrote:
>>> On Thu, 2 May 2013, Christopher Covington wrote:
>>>>> So the virtual timer should appear to have been running even whi
Hi Ian,
On 05/02/2013 04:19 AM, Ian Campbell wrote:
> On Wed, 2013-05-01 at 21:36 +0100, Christopher Covington wrote:
>> Hi Stefano,
>>
>> On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
>>> Introduce a function, called arch_timer_stolen_ticks, called from the
&g
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> static variables to common code (drivers/xen/time.c).
>
> Signed-off-by: Stefano Stabellini
> ---
> arch/x86/xen/time.c | 127 +--
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Introduce a function, called arch_timer_stolen_ticks, called from the
> arch_timer interrupt handler to account for stolen ticks.
[...]
> diff --git a/arch/arm/include/asm/arch_timer.h
> b/arch/arm/include/asm/arch_timer.h
> index
his change and dependencies on top of Catalin's
soc-armv8-model branch [1] and was able to verify that it fixed the printk
timestamp jump.
1.
http://git.kernel.org/cgit/linux/kernel/git/cmarinas/linux-aarch64.git/log/?h=soc-armv8-model
Tested-by: Christopher Covington
--
Employee of Qualcomm
Hi Pranavkumar,
On 04/18/2013 01:52 AM, PranavkumarSawargaonkar wrote:
> From: Pranavkumar Sawargaonkar
>
> This patch implements early printk support for virtio-mmio console devices
> without using any hypercalls.
Is it possible that using DCC might be an easier solution?
[...]
Regards,
Chr
On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
>>>>> For accurate accounting pass contextidr_thread_switch the prev
>>>>> task pointer, since cpu_switch_to has at that point changed the
>>>>> the stack pointer.
>>>>>
&g
Hi Will,
On 04/10/2013 07:41 AM, Will Deacon wrote:
> On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
>> For accurate accounting pass contextidr_thread_switch the prev
>> task pointer, since cpu_switch_to has at that point changed the
>> the stack poin
For accurate accounting pass contextidr_thread_switch the prev
task pointer, since cpu_switch_to has at that point changed the
the stack pointer.
Signed-off-by: Christopher Covington
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64
Hi Will,
On 04/03/2013 02:04 PM, Will Deacon wrote:
> Hi Christopher,
>
> On Wed, Apr 03, 2013 at 07:01:01PM +0100, Christopher Covington wrote:
>> For accurate accounting call contextidr_thread_switch before a
>> task is scheduled, rather than after.
>>
>> Sig
For accurate accounting call contextidr_thread_switch before a
task is scheduled, rather than after.
Signed-off-by: Christopher Covington
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
Hi Chen,
On 04/03/2013 04:13 AM, Chen Gang wrote:
> Hello Maintainers:
>
> it seems, this issue still exists in next-20130402.
>
> have you already fixed it in another tree ?
Maybe somebody else does have a fix, but Catalin mentioned he was going on
vacation for two weeks on March 28th in "
Hi Catalin and Will,
On 09/12/2012 09:49 AM, Catalin Marinas wrote:
> On Wed, Sep 12, 2012 at 01:08:58PM +0100, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
>> On 17:11 Mon 10 Sep , Catalin Marinas wrote:
>>> On Sun, Sep 09, 2012 at 06:20:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD
>>> wrote:
On 08/14/2012 01:52 PM, Catalin Marinas wrote:
> From: Marc Zyngier
>
> This patch adds support for the ARM generic timers with A64 instructions
> for accessing the timer registers. It uses the physical counter as the
> clock source and the virtual counter as sched_clock.
>
> The timer frequency
Hi Catalin,
On 07/06/2012 05:06 PM, Catalin Marinas wrote:
> This patch updates the MAINTAINERS file for the AArch64 Linux kernel
> port.
>
> Signed-off-by: Catalin Marinas
>
> ---
> MAINTAINERS |6 ++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
>
> --
> To unsubscribe from t
Hi Catalin,
Thanks for your response.
On 08/09/2012 01:23 PM, Catalin Marinas wrote:
> Hi Christopher,
>
> On Thu, Aug 09, 2012 at 06:05:36PM +0100, Christopher Covington wrote:
>> On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
>>> +/*
>>> + * Exception
Hi Catalin and Will,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> The patch contains the exception entry code (kernel/entry.S), pt_regs
> structure and related accessors, undefined instruction trapping and
> stack tracing.
>
> AArch64 Linux kernel (including kernel threads) runs in EL1 mod
On 07/27/2012 05:19 AM, Ian Campbell wrote:
> On Thu, 2012-07-26 at 20:19 +0100, Christopher Covington wrote:
>> Hi Stefano,
>>
>> On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
>>> Use r12 to pass the hypercall number to the hypervisor.
>>>
>>>
Hi Stefano,
On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
> Use r12 to pass the hypercall number to the hypervisor.
>
> We need a register to pass the hypercall number because we might not
> know it at compile time and HVC only takes an immediate argument.
You're not going to JIT assemble th
On 07/25/2012 04:47 AM, Catalin Marinas wrote:
> On Tue, Jul 24, 2012 at 08:42:28PM +0100, Christopher Covington wrote:
>> On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
>>> +- Architected timers
>>> + CNTFRQ must be programmed with the timer frequency.
>>&
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> The patch adds the kernel booting and the initial setup code.
> Documentation/aarch64/booting.txt describes the booting protocol on the
> AArch64 Linux kernel. This is subject to change following the work on
> boot standardisation, AC
Hi Catalin and Stephen,
Catalin Marinas - July 8, 2012, 9:18 a.m.
> On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
>
>> Also, on Tegra at least and perhaps OMAP too, there are a few parts
>> of earlyprintk serial port setup (i.e. port selection) which happen
>> as part of the dec
Hi Catalin,
On 07/20/2012 09:48 AM, Catalin Marinas wrote:
> On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
>>>> +- CPU mode
>>
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> This patch introduces several assembly macros and definitions used in
> the .S files across arch/aarch64/ like IRQ disabling/enabling, together
> with asm-offsets.c.
[...]
> diff --git a/arch/aarch64/include/asm/assembler.h
> b/arc
Hi Jon,
On 07/20/2012 03:10 AM, Jon Masters wrote:
> On 07/19/2012 01:31 PM, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
>>>> +- CPU mode
>>>> + All forms
On 07/18/2012 02:57 AM, Jon Masters wrote:
> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>
>> +- CPU mode
>> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
>> + IRQ and FIQ).
>> + The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
Why not secure EL1?
>
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