Hi Konrad,
On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>> would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
>>> where the timer goes off. Nor does it make sense to require that the
>>>
On 05/07/2013 08:19 AM, Peter Maydell wrote:
> On 7 May 2013 05:46, Rusty Russell wrote:
>> Peter Maydell writes:
>>> That all looks like sensible QEMU implementation possibilities
>>> but it seems to be a bit of a non-sequitur from "how do we
>>> tell the kernel to actually use this?"
>>
>> You
On 05/07/2013 05:08 AM, Will Deacon wrote:
> On Mon, May 06, 2013 at 07:01:23PM +0100, Christopher Covington wrote:
>> Hi Will,
>>
>> On 05/03/2013 01:35 PM, Will Deacon wrote:
>>> Hi all,
>>>
>>> This small patch set may look a little over
On 05/07/2013 05:08 AM, Will Deacon wrote:
On Mon, May 06, 2013 at 07:01:23PM +0100, Christopher Covington wrote:
Hi Will,
On 05/03/2013 01:35 PM, Will Deacon wrote:
Hi all,
This small patch set may look a little over a month late, but there is a
serious reason for posting it.
When I
On 05/07/2013 08:19 AM, Peter Maydell wrote:
On 7 May 2013 05:46, Rusty Russell ru...@rustcorp.com.au wrote:
Peter Maydell peter.mayd...@linaro.org writes:
That all looks like sensible QEMU implementation possibilities
but it seems to be a bit of a non-sequitur from how do we
tell the kernel
Hi Konrad,
On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
would not make sense (from the guests PoV) for NOW'==NOW+2 at the point
where the timer goes off. Nor does it make sense to require that the
guest actually
Hi Will,
On 05/03/2013 01:35 PM, Will Deacon wrote:
> Hi all,
>
> This small patch set may look a little over a month late, but there is a
> serious reason for posting it.
>
> When I moved the ARM delay loop over to using the architected timers
> rather than the CPU spinning loop (which has all
On 05/05/2013 12:47 PM, Stefano Stabellini wrote:
> On Fri, 3 May 2013, Marc Zyngier wrote:
>> On 03/05/13 11:43, Stefano Stabellini wrote:
>>> On Thu, 2 May 2013, Christopher Covington wrote:
>>>>> So the virtual timer should appear to have been running even
On 05/05/2013 12:47 PM, Stefano Stabellini wrote:
On Fri, 3 May 2013, Marc Zyngier wrote:
On 03/05/13 11:43, Stefano Stabellini wrote:
On Thu, 2 May 2013, Christopher Covington wrote:
So the virtual timer should appear to have been running even while time
is being stolen and therefore stolen
Hi Will,
On 05/03/2013 01:35 PM, Will Deacon wrote:
Hi all,
This small patch set may look a little over a month late, but there is a
serious reason for posting it.
When I moved the ARM delay loop over to using the architected timers
rather than the CPU spinning loop (which has all the
Hi Ian,
On 05/02/2013 04:19 AM, Ian Campbell wrote:
> On Wed, 2013-05-01 at 21:36 +0100, Christopher Covington wrote:
>> Hi Stefano,
>>
>> On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
>>> Introduce a function, called arch_timer_stolen_ticks, called from the
&g
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Move do_stolen_accounting, xen_vcpu_stolen and related functions and
> static variables to common code (drivers/xen/time.c).
>
> Signed-off-by: Stefano Stabellini
> ---
> arch/x86/xen/time.c | 127
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
Move do_stolen_accounting, xen_vcpu_stolen and related functions and
static variables to common code (drivers/xen/time.c).
Signed-off-by: Stefano Stabellini stefano.stabell...@eu.citrix.com
---
arch/x86/xen/time.c | 127
Hi Ian,
On 05/02/2013 04:19 AM, Ian Campbell wrote:
On Wed, 2013-05-01 at 21:36 +0100, Christopher Covington wrote:
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
Introduce a function, called arch_timer_stolen_ticks, called from the
arch_timer interrupt handler to account
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
> Introduce a function, called arch_timer_stolen_ticks, called from the
> arch_timer interrupt handler to account for stolen ticks.
[...]
> diff --git a/arch/arm/include/asm/arch_timer.h
> b/arch/arm/include/asm/arch_timer.h
> index
his change and dependencies on top of Catalin's
soc-armv8-model branch [1] and was able to verify that it fixed the printk
timestamp jump.
1.
http://git.kernel.org/cgit/linux/kernel/git/cmarinas/linux-aarch64.git/log/?h=soc-armv8-model
Tested-by: Christopher Covington
--
Employee of Qualcom
of Catalin's
soc-armv8-model branch [1] and was able to verify that it fixed the printk
timestamp jump.
1.
http://git.kernel.org/cgit/linux/kernel/git/cmarinas/linux-aarch64.git/log/?h=soc-armv8-model
Tested-by: Christopher Covington c...@codeaurora.org
--
Employee of Qualcomm Innovation Center
Hi Stefano,
On 05/01/2013 03:27 PM, Stefano Stabellini wrote:
Introduce a function, called arch_timer_stolen_ticks, called from the
arch_timer interrupt handler to account for stolen ticks.
[...]
diff --git a/arch/arm/include/asm/arch_timer.h
b/arch/arm/include/asm/arch_timer.h
index
Hi Pranavkumar,
On 04/18/2013 01:52 AM, PranavkumarSawargaonkar wrote:
> From: Pranavkumar Sawargaonkar
>
> This patch implements early printk support for virtio-mmio console devices
> without using any hypercalls.
Is it possible that using DCC might be an easier solution?
[...]
Regards,
Hi Pranavkumar,
On 04/18/2013 01:52 AM, PranavkumarSawargaonkar wrote:
From: Pranavkumar Sawargaonkar pranavku...@linaro.org
This patch implements early printk support for virtio-mmio console devices
without using any hypercalls.
Is it possible that using DCC might be an easier solution?
On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
>>>>> For accurate accounting pass contextidr_thread_switch the prev
>>>>> task pointer, since cpu_switch_to has at that point changed the
>>>>> the stack pointer.
>>>>>
&g
, Christopher Covington wrote:
For accurate accounting pass contextidr_thread_switch the prev
task pointer, since cpu_switch_to has at that point changed the
the stack pointer.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1
Hi Will,
On 04/10/2013 07:41 AM, Will Deacon wrote:
> On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
>> For accurate accounting pass contextidr_thread_switch the prev
>> task pointer, since cpu_switch_to has at that point changed the
>> the stack poin
Hi Will,
On 04/10/2013 07:41 AM, Will Deacon wrote:
On Tue, Apr 09, 2013 at 01:33:34PM +0100, Christopher Covington wrote:
For accurate accounting pass contextidr_thread_switch the prev
task pointer, since cpu_switch_to has at that point changed the
the stack pointer.
Signed-off
For accurate accounting pass contextidr_thread_switch the prev
task pointer, since cpu_switch_to has at that point changed the
the stack pointer.
Signed-off-by: Christopher Covington
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64
For accurate accounting pass contextidr_thread_switch the prev
task pointer, since cpu_switch_to has at that point changed the
the stack pointer.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hi Will,
On 04/03/2013 02:04 PM, Will Deacon wrote:
> Hi Christopher,
>
> On Wed, Apr 03, 2013 at 07:01:01PM +0100, Christopher Covington wrote:
>> For accurate accounting call contextidr_thread_switch before a
>> task is scheduled, rather than after.
>>
>> Sig
Hi Will,
On 04/03/2013 02:04 PM, Will Deacon wrote:
Hi Christopher,
On Wed, Apr 03, 2013 at 07:01:01PM +0100, Christopher Covington wrote:
For accurate accounting call contextidr_thread_switch before a
task is scheduled, rather than after.
Signed-off-by: Christopher Covington c
For accurate accounting call contextidr_thread_switch before a
task is scheduled, rather than after.
Signed-off-by: Christopher Covington
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
Hi Chen,
On 04/03/2013 04:13 AM, Chen Gang wrote:
> Hello Maintainers:
>
> it seems, this issue still exists in next-20130402.
>
> have you already fixed it in another tree ?
Maybe somebody else does have a fix, but Catalin mentioned he was going on
vacation for two weeks on March 28th in
Hi Chen,
On 04/03/2013 04:13 AM, Chen Gang wrote:
Hello Maintainers:
it seems, this issue still exists in next-20130402.
have you already fixed it in another tree ?
Maybe somebody else does have a fix, but Catalin mentioned he was going on
vacation for two weeks on March 28th in [GIT
For accurate accounting call contextidr_thread_switch before a
task is scheduled, rather than after.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm64/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/process.c b/arch
Hi Catalin and Will,
On 09/12/2012 09:49 AM, Catalin Marinas wrote:
> On Wed, Sep 12, 2012 at 01:08:58PM +0100, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
>> On 17:11 Mon 10 Sep , Catalin Marinas wrote:
>>> On Sun, Sep 09, 2012 at 06:20:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD
>>> wrote:
Hi Catalin and Will,
On 09/12/2012 09:49 AM, Catalin Marinas wrote:
On Wed, Sep 12, 2012 at 01:08:58PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
On 17:11 Mon 10 Sep , Catalin Marinas wrote:
On Sun, Sep 09, 2012 at 06:20:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
On 17:26
On 08/14/2012 01:52 PM, Catalin Marinas wrote:
> From: Marc Zyngier
>
> This patch adds support for the ARM generic timers with A64 instructions
> for accessing the timer registers. It uses the physical counter as the
> clock source and the virtual counter as sched_clock.
>
> The timer
On 08/14/2012 01:52 PM, Catalin Marinas wrote:
From: Marc Zyngier marc.zyng...@arm.com
This patch adds support for the ARM generic timers with A64 instructions
for accessing the timer registers. It uses the physical counter as the
clock source and the virtual counter as sched_clock.
The
Hi Catalin,
On 07/06/2012 05:06 PM, Catalin Marinas wrote:
> This patch updates the MAINTAINERS file for the AArch64 Linux kernel
> port.
>
> Signed-off-by: Catalin Marinas
>
> ---
> MAINTAINERS |6 ++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
>
> --
> To unsubscribe from
Hi Catalin,
On 07/06/2012 05:06 PM, Catalin Marinas wrote:
This patch updates the MAINTAINERS file for the AArch64 Linux kernel
port.
Signed-off-by: Catalin Marinas catalin.mari...@arm.com
---
MAINTAINERS |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
--
To
Hi Catalin,
Thanks for your response.
On 08/09/2012 01:23 PM, Catalin Marinas wrote:
> Hi Christopher,
>
> On Thu, Aug 09, 2012 at 06:05:36PM +0100, Christopher Covington wrote:
>> On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
>>> +/*
>>> + * Exception
Hi Catalin and Will,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> The patch contains the exception entry code (kernel/entry.S), pt_regs
> structure and related accessors, undefined instruction trapping and
> stack tracing.
>
> AArch64 Linux kernel (including kernel threads) runs in EL1
Hi Catalin and Will,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
The patch contains the exception entry code (kernel/entry.S), pt_regs
structure and related accessors, undefined instruction trapping and
stack tracing.
AArch64 Linux kernel (including kernel threads) runs in EL1 mode
Hi Catalin,
Thanks for your response.
On 08/09/2012 01:23 PM, Catalin Marinas wrote:
Hi Christopher,
On Thu, Aug 09, 2012 at 06:05:36PM +0100, Christopher Covington wrote:
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
+/*
+ * Exception vectors.
+ */
+ .macro ventry label
On 07/27/2012 05:19 AM, Ian Campbell wrote:
> On Thu, 2012-07-26 at 20:19 +0100, Christopher Covington wrote:
>> Hi Stefano,
>>
>> On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
>>> Use r12 to pass the hypercall number to the hypervisor.
>>>
>>>
On 07/27/2012 05:19 AM, Ian Campbell wrote:
On Thu, 2012-07-26 at 20:19 +0100, Christopher Covington wrote:
Hi Stefano,
On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
Use r12 to pass the hypercall number to the hypervisor.
We need a register to pass the hypercall number because we might
Hi Stefano,
On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
> Use r12 to pass the hypercall number to the hypervisor.
>
> We need a register to pass the hypercall number because we might not
> know it at compile time and HVC only takes an immediate argument.
You're not going to JIT assemble
Hi Stefano,
On 07/26/2012 11:33 AM, Stefano Stabellini wrote:
Use r12 to pass the hypercall number to the hypervisor.
We need a register to pass the hypercall number because we might not
know it at compile time and HVC only takes an immediate argument.
You're not going to JIT assemble the
On 07/25/2012 04:47 AM, Catalin Marinas wrote:
> On Tue, Jul 24, 2012 at 08:42:28PM +0100, Christopher Covington wrote:
>> On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
>>> +- Architected timers
>>> + CNTFRQ must be programmed with the timer frequency.
>>&
On 07/25/2012 04:47 AM, Catalin Marinas wrote:
On Tue, Jul 24, 2012 at 08:42:28PM +0100, Christopher Covington wrote:
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
+- Architected timers
+ CNTFRQ must be programmed with the timer frequency.
+ If entering the kernel at EL1, CNTHCTL_EL2
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> The patch adds the kernel booting and the initial setup code.
> Documentation/aarch64/booting.txt describes the booting protocol on the
> AArch64 Linux kernel. This is subject to change following the work on
> boot standardisation,
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
The patch adds the kernel booting and the initial setup code.
Documentation/aarch64/booting.txt describes the booting protocol on the
AArch64 Linux kernel. This is subject to change following the work on
boot standardisation, ACPI.
Hi Catalin and Stephen,
Catalin Marinas - July 8, 2012, 9:18 a.m.
> On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
>
>> Also, on Tegra at least and perhaps OMAP too, there are a few parts
>> of earlyprintk serial port setup (i.e. port selection) which happen
>> as part of the
Hi Catalin and Stephen,
Catalin Marinas - July 8, 2012, 9:18 a.m.
On Fri, Jul 06, 2012 at 10:32:54PM +0100, Stephen Warren wrote:
Also, on Tegra at least and perhaps OMAP too, there are a few parts
of earlyprintk serial port setup (i.e. port selection) which happen
as part of the
Hi Catalin,
On 07/20/2012 09:48 AM, Catalin Marinas wrote:
> On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
>>>> +- CPU mode
>>
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> This patch introduces several assembly macros and definitions used in
> the .S files across arch/aarch64/ like IRQ disabling/enabling, together
> with asm-offsets.c.
[...]
> diff --git a/arch/aarch64/include/asm/assembler.h
>
Hi Jon,
On 07/20/2012 03:10 AM, Jon Masters wrote:
> On 07/19/2012 01:31 PM, Christopher Covington wrote:
>> On 07/18/2012 02:57 AM, Jon Masters wrote:
>>> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>>>
>>>> +- CPU mode
>>>> + All forms
Hi Jon,
On 07/20/2012 03:10 AM, Jon Masters wrote:
On 07/19/2012 01:31 PM, Christopher Covington wrote:
On 07/18/2012 02:57 AM, Jon Masters wrote:
On 07/06/2012 05:05 PM, Catalin Marinas wrote:
+- CPU mode
+ All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
+ IRQ
Hi Catalin,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
This patch introduces several assembly macros and definitions used in
the .S files across arch/aarch64/ like IRQ disabling/enabling, together
with asm-offsets.c.
[...]
diff --git a/arch/aarch64/include/asm/assembler.h
Hi Catalin,
On 07/20/2012 09:48 AM, Catalin Marinas wrote:
On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
On 07/18/2012 02:57 AM, Jon Masters wrote:
On 07/06/2012 05:05 PM, Catalin Marinas wrote:
+- CPU mode
+ All forms of interrupts must be masked in PSTATE.DAIF
On 07/18/2012 02:57 AM, Jon Masters wrote:
> On 07/06/2012 05:05 PM, Catalin Marinas wrote:
>
>> +- CPU mode
>> + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
>> + IRQ and FIQ).
>> + The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
Why not secure EL1?
>
On 07/18/2012 02:57 AM, Jon Masters wrote:
On 07/06/2012 05:05 PM, Catalin Marinas wrote:
+- CPU mode
+ All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
+ IRQ and FIQ).
+ The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
Why not secure EL1?
Even
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