:
.handle_reply
.handle_request
- the callbacks will be used by the protocol on
notification arrival from DSP.
Signed-off-by: Daniel Baluta
---
Changes since v2:
- remove DSP IPC own DT node as per Rob comments
- make dsp responsability to add MU nodes
I just made some minor changes and will send the patch right now.
Shawn please skip this.
On Tue, Jul 9, 2019 at 3:02 PM Oleksij Rempel wrote:
>
> On Tue, Jul 09, 2019 at 08:48:20AM +0300, Daniel Baluta wrote:
> > Hi Oleksij,
> >
> > Any comments on this?
>
On Thu, Jul 18, 2019 at 6:30 AM Aisheng Dong wrote:
>
> > From: Daniel Baluta
> > Sent: Thursday, July 4, 2019 3:04 AM
> > Subject: [PATCH 2/3] firmware: imx: scu-pd: Add mu_b side PD range
> >
> > LSIO subsystem contains 14 MU instances.
> >
>
Aisheng/Shengjiu,
Care to help with review on this?
On Wed, Jul 3, 2019 at 10:06 PM Daniel Baluta wrote:
>
> This patch adds power domain range for MU side b and irqsteer in
> preparation for adding support for DSP <-> AP IPC communication.
>
> Daniel Baluta (3):
>
Aisheng/Jacky,
Can you help with review on this?
On Tue, Jul 2, 2019 at 6:22 PM Daniel Baluta wrote:
>
> i.MX8QXP contains Hifi4 DSP. There are four clocks
> associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_ipg_
On Tue, Jul 16, 2019 at 6:58 PM Lucas Stach wrote:
>
> Hi Daniel,
>
> Am Mittwoch, den 03.07.2019, 16:25 +0300 schrieb Daniel Baluta:
> > > On Wed, Jul 3, 2019 at 4:12 PM Angus Ainslie wrote:
> > >
> > > Hi Daniel,
> > >
> > > On 2019-07-0
On Thu, Jul 11, 2019 at 12:19 PM Oliver Graute wrote:
>
> On 11/07/19, Abel Vesa wrote:
> > On 19-06-19 09:39:52, Oliver Graute wrote:
> > > From: Oliver Graute
> > >
> > > added header defines for imx8qm clock
> > >
> > > Signed-off-by: Oliver Graute
> >
> > Again, this seems to be taken from s
Hi Oleksij,
Any comments on this?
On Thu, Jun 27, 2019 at 11:14 AM Daniel Baluta wrote:
>
> Some of i.MX8 processors (e.g i.MX8QM, i.MX8QXP) contain
> the Tensilica HiFi4 DSP for advanced pre- and post-audio
> processing.
>
> The communication between Host CPU and DSP fi
The DSP interrupt steer gathers interrupts from the system
and can be used to steer them to DSP.
Signed-off-by: Daniel Baluta
---
drivers/firmware/imx/scu-pd.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index 30adc3104347
LSIO subsystem contains 14 MU instances.
5 MUs to communicate between AP <-> SCU
- side-A PD range managed by AP
- side-B PD range managed by SCU
9 MUs to communicate between AP <-> M4
- side-A PD range managed by AP
- side-B PD range managed by AP
Signed-off-by: D
This patch adds power domain range for MU side b and irqsteer in
preparation for adding support for DSP <-> AP IPC communication.
Daniel Baluta (3):
firmware: imx: scu-pid: Rename mu PD range to mu_a
firmware: imx: scu-pd: Add mu_b side PD range
firmware: imx: scu-pd: Add IRQSTR_
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages through the MU interface.
MUs have 2 “sides” with independent programming interfaces. Rename
mu PD range to mu_a because it's actually side A of MUs.
Signed-off-by: Daniel B
On Wed, Jul 3, 2019 at 4:12 PM Angus Ainslie wrote:
>
> Hi Daniel,
>
> On 2019-07-03 07:10, Daniel Baluta wrote:
> > On Wed, Jul 3, 2019 at 4:01 PM Angus Ainslie wrote:
> >>
> >> Hi Andra,
> >>
> >> I tried this out on linux-next and I
AI patches that need to be upstream. Me and Andra
will be working on that over this summer.
>
> On 2019-07-02 07:23, Andra Danciu wrote:
> > SAI3 and SAI6 nodes are used to connect to an external codec.
> > They have 1 Tx and 1 Rx dataline.
> >
> > Cc: Daniel Baluta
&g
t; consumer API in a clock provider driver.
>
> Signed-off-by: Abel Vesa
For audio related clock:
Acked-by: Daniel Baluta
> ---
>
> Changes since v1:
> - removed the PCIE and CSI clocks parent setting since
>that should be done from their driver, as suggested
>
t; consumer API in a clock provider driver.
>
> Signed-off-by: Abel Vesa
Thanks Abel, this helps audio. For audio clk:
Acked-by: Daniel Baluta
> ---
>
> Changes since v1:
> - removed the PCIE, CSI and DISP clocks parent setting since
>that should be done from th
On Tue, Jul 2, 2019 at 4:25 PM Andra Danciu wrote:
>
> SAI3 and SAI6 nodes are used to connect to an external codec.
> They have 1 Tx and 1 Rx dataline.
>
> Cc: Daniel Baluta
> Signed-off-by: Andra Danciu
Reviewed-by: Daniel Baluta
> ---
> Changes since v2:
>
i.MX8QXP contains Hifi4 DSP. There are four clocks
associated with DSP:
* dsp_lpcg_core_clk
* dsp_lpcg_ipg_clk
* dsp_lpcg_adb_aclk
* ocram_lpcg_ipg_clk
Signed-off-by: Daniel Baluta
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 +
include/dt-bindings/clock/imx8-clock.h | 6 +-
2
On Tue, Jul 2, 2019 at 4:26 PM Abel Vesa wrote:
>
> On 19-06-26 15:45:15, Daniel Baluta wrote:
> > On Tue, Jun 25, 2019 at 4:42 PM Abel Vesa wrote:
> > >
> > > Add the initial configuration for clocks that need default parent and rate
> > > setting.
Looks better now. One comment inline:
On Tue, Jul 2, 2019 at 4:12 PM Andra Danciu wrote:
>
> SAI3 and SAI6 nodes are used to connect to an external codec.
> They have 1 Tx and 1 Rx dataline.
>
> Cc: Daniel Baluta
> Signed-off-by: Andra Danciu
> ---
> Changes since v1
3/6 supports up to 2-channels TX (1 dataline) and 2-channels RX (1 dataline).
>
> > Cc: Daniel Baluta
> > Signed-off-by: Andra Danciu
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 14 ++
> > 1 file changed, 14 insertions(+)
> >
> &g
On Thu, Jun 27, 2019 at 6:59 PM Rob Herring wrote:
>
> On Thu, Jun 27, 2019 at 1:40 AM Daniel Baluta wrote:
> >
> >
> >
> > > > > > + mboxes:
> > > > > > +description:
> > > > > > + List of phandle of 2 MU
On Fri, Jun 28, 2019 at 6:36 AM wrote:
>
> From: Anson Huang
>
> Add i.MX SCU SoC's UID(unique identifier) support, user
> can read it from sysfs:
>
> root@imx8qxpmek:~# cat /sys/devices/soc0/soc_uid
> 7B64280B57AC1898
>
> Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
GIEn is enabled at startup for RX doorbell mailboxes so
we need to clear the bit at shutdown in order to avoid
leaving the interrupt line enabled.
Signed-off-by: Daniel Baluta
Reviewed-by: Oleksij Rempel
---
Changes since v1:
- separate patch from inital series of creating DSP IPC driver
DSP IPC is the layer that allows the Host CPU to communicate
with DSP firmware.
DSP is part of some i.MX8 boards (e.g i.MX8QM, i.MX8QXP)
Signed-off-by: Daniel Baluta
---
.../devicetree/bindings/dsp/fsl,dsp_ipc.yaml | 44 +++
1 file changed, 44 insertions(+)
create mode 100644
callbacks:
.handle_reply
.handle_request
- the callbacks will be used by the protocol driver on
notification arrival from DSP.
Signed-off-by: Daniel Baluta
---
drivers/firmware/imx/Kconfig | 11 +++
drivers/firmware/imx/Makefile| 1 +
drivers/firmware/imx/imx-dsp.c
s and Oleksij comments)
- removed imx_dsp_get_handle now drivers wanting to use DSP IPC
will get a reference to dsp_ipc node in dts.
- added chip name in compatible string fsl,imx8qxp-dsp
- avoid memory leaks
- make dt_binding_check works fine now!
Daniel Balu
> > > > + mboxes:
> > > > +description:
> > > > + List of phandle of 2 MU channels for TXDB, 2 MU channels for RXDB
> > > > + (see mailbox/fsl,mu.txt)
> > > > +maxItems: 1
> > >
> > > Should be 4?
> >
> > Actually is just a list with 1 item. I think is the terminology:
> >
> >
On Thu, Jun 27, 2019 at 3:48 AM Anson Huang wrote:
>
> Hi, Daniel
>
> > -Original Message-
> > From: Daniel Baluta
> > Sent: Wednesday, June 26, 2019 8:42 PM
> > To: Anson Huang
> > Cc: Shawn Guo ; Sascha Hauer
> > ; Pengutronix Kernel Team
Hi Rob,
This is my first time documenting the bindings using the
new yaml format so thanks for your patience and explanations!
On Fri, Jun 14, 2019 at 5:53 PM Rob Herring wrote:
>
> On Fri, Jun 14, 2019 at 2:15 AM wrote:
> >
> > From: Daniel Baluta
> >
> > DSP IP
On Tue, Jun 25, 2019 at 4:42 PM Abel Vesa wrote:
>
> Add the initial configuration for clocks that need default parent and rate
> setting. This is based on the vendor tree clock provider parents and rates
> configuration except this is doing the setup in dts rather than using clock
> consumer API
On Wed, Jun 26, 2019 at 10:06 AM wrote:
>
> From: Anson Huang
>
> Add i.MX SCU SoC's UID(unique identifier) support, user
> can read it from sysfs:
>
> root@imx8qxpmek:~# cat /sys/devices/soc0/soc_uid
> 7B64280B57AC1898
>
> Signed-off-by: Anson Huang
> ---
> drivers/soc/imx/soc-imx-scu.c | 35 +
stems that are active :
> - Ethernet
> - USB
>
> Cc: Daniel Baluta
> Signed-off-by: Richard Hu
> Signed-off-by: Andra Danciu
> ---
> I am using pico-pi-8mxm board to work on my project for Google Summer of
> Code.
> This is based on patches from https:/
On Mon, 2019-06-24 at 08:52 +0300, Matti Vaittinen wrote:
> Hello Richard,
>
> Nice to see you upstreaming this! Thumbs up!
>
> Just few remarks to pmic node from me:
>
>
Thanks a lot Matti for review. I am working together with Andra
for a Google Summer of Code project.
The first step of th
lsio_mu13 node is used to communicate with DSP.
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index b2cb818c76c6
Shawn,
Care to have a look at this? git send-email should correctly work now.
Let me know if you want me to resend
On Tue, Jun 4, 2019 at 3:34 PM wrote:
>
> From: Daniel Baluta
>
> i.MX8MM has one wm8524 audio codec connected with
> SAI3 digital audio interface.
>
> T
On Fri, Jun 14, 2019 at 12:08 PM Oleksij Rempel wrote:
>
> Hi Daniel,
>
> please, see my review inline.
Thanks Oleksij for review. See my answers inline.
>
> On Fri, Jun 14, 2019 at 04:16:49PM +0800, daniel.bal...@nxp.com wrote:
> > From: Daniel Baluta
> >
>
From: Daniel Baluta
DSP IPC is the layer that allows the Host CPU to communicate
with DSP firmware.
DSP is part of some i.MX8 boards (e.g i.MX8QM, i.MX8QXP)
Signed-off-by: Daniel Baluta
---
.../bindings/arm/freescale/fsl,dsp.yaml | 43 +++
1 file changed, 43 insertions
From: Daniel Baluta
Hifi4 DSP can be found on some i.MX8 platforms (e.g i.MX8QXP, i.MX8QM).
This patch series introduces the layer that allows Host CPU to
communicate with DSP.
This layer provides a doorbell and clients can used that to notify DSP
that a message is placed somewhere in the
From: Daniel Baluta
Some of i.MX8 processors (e.g i.MX8QM, i.MX8QXP) contain
the Tensilica HiFi4 DSP for advanced pre- and post-audio
processing.
The communication between Host CPU and DSP firmware is
taking place using a shared memory area for message passing
and a dedicated Messaging Unit for
On Tue, Jun 11, 2019 at 11:40 AM Oleksij Rempel wrote:
>
> On Tue, Jun 11, 2019 at 10:52:47AM +0300, Daniel Baluta wrote:
> > Hi Oleksij,
> >
> > On Tue, Jun 11, 2019 at 8:56 AM Oleksij Rempel
> > wrote:
> > >
> > > Hi Daniel,
> > >
&
Hi Oleksij,
On Tue, Jun 11, 2019 at 8:56 AM Oleksij Rempel wrote:
>
> Hi Daniel,
>
> On Mon, Jun 10, 2019 at 10:16:09PM +0800, daniel.bal...@nxp.com wrote:
> > From: Daniel Baluta
> >
> > TX doorbell with ACK will allow us to push the doorbell ring button
> &g
GIEn is enabled at startup for RX doorbell mailboxes so
we need to clear the bit at shutdown in order to avoid
leaving the interrupt line enabled.
Signed-off-by: Daniel Baluta
Reviewed-by: Oleksij Rempel
---
Changes since v1:
- no changes since v1 just sent it as a separate patch from
From: Daniel Baluta
We need this in order to implement the communication protocol
between Linux kernel SOF IPC layer and DSP firmware found on i.MX8 boards.
First patch is just a bugfix and can be merged as it is.
The second patch is just a RFC to open the discussion on how to use the i.MX
From: Daniel Baluta
TX doorbell with ACK will allow us to push the doorbell ring button
(trigger GIR) and also will allow us to handle the response from DSP.
DSP firmware found on i.MX8 boards implements a duplex
communication protocol over MU channels.
On the host side (Linux) we need to
From: Daniel Baluta
GIEn is enabled at startup for RX doorbell mailboxes so
we need to clear the bit at shutdown in order to avoid
leaving the interrupt line enabled.
Signed-off-by: Daniel Baluta
---
drivers/mailbox/imx-mailbox.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Daniel Baluta
i.MX8MM has one wm8524 audio codec connected with
SAI3 digital audio interface.
This patch uses simple-card machine driver in order
to enable wm8524 codec.
We need to set:
* SAI3 pinctrl configuration
* codec reset gpio pinctrl configuration
* clock
From: Daniel Baluta
This patch series introduces the SAI nodes on i.MX8MM EVK then
creates the wm8524 codec node and finally uses simple card machine
driver to create a sound card.
Changes since v3:
- rebased on latest for-next branch
- fixed encoding problems
Changes since v2
From: Daniel Baluta
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Daniel Baluta
Reviewed-by
On Wed, 2019-05-29 at 16:03 -0700, Nicolin Chen wrote:
> On Tue, May 28, 2019 at 01:20:46PM +0000, Daniel Baluta wrote:
>
> > 1) SAI clock source select MUX is really part of the hardware
> > 2) flexibility! We let DT tell us which is the option for MUX
> > option 0.
&
SAI might have up to 4 clock sources selected by an internal
CLK mux.
On imx6/7 mclk0/mclk1 are the same, while on imx8 mclk0 and
mclk1 are coming from different sources.
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++--
1 file changed, 3
ion selected.
11b - Master Clock (MCLK) 3 option selected.
So, this patch will read mclk0 source clock from device tree.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.
generic way in SAI driver.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
---
arch/arm/boot/dts/imx6sx.dtsi | 6 --
arch/arm/boot/dts/imx6ul.dtsi | 9 ++---
arch/arm/boot/dts/imx7s.dtsi | 9 ++---
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot
r MUX
option 0.
[1] lkml.org/lkml/2019/4/20/141
[2] lkml.org/lkml/2019/4/20/56
Daniel Baluta (2):
dt-bindings: sound: Clarify the usage of clocks in SAI
ASoC: fsl_sai: Read SAI clock source 0 from DT
Shengjiu Wang (1):
ARM: dts: imx: Add mclk0 clock for SAI
Documentation/devicetree/bin
On Sun, Apr 21, 2019 at 11:26 AM Nicolin Chen wrote:
>
> On Sun, Apr 21, 2019 at 01:04:39AM -0700, Nicolin Chen wrote:
> > On Sun, Apr 21, 2019 at 10:26:40AM +0300, Daniel Baluta wrote:
> > > > Firstly, according to your commit message, neither imx8qm nor
> > >
On Mon, May 20, 2019 at 10:33 PM Fabio Estevam wrote:
>
> On Thu, May 16, 2019 at 3:35 PM Fabio Estevam wrote:
> >
> > On Wed, May 15, 2019 at 11:42 AM Daniel Baluta
> > wrote:
> >
> > > + simple-audio-card,codec {
> > &
the codec.
Unless, we can really look into the schematics and prove it otherwise.
On Thu, May 16, 2019 at 10:14 PM Fabio Estevam wrote:
>
> On Wed, May 15, 2019 at 11:42 AM Daniel Baluta wrote:
>
> > + simple-audio-card,codec {
> > +
gfs_name is allocated using kasprintf
and then the pointer is lost by assigning it other memory address.
Reported-by: Stefan Wahren
Signed-off-by: Daniel Baluta
---
drivers/base/regmap/regmap-debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/base/regmap/regmap-debugfs
On Thu, 2019-05-16 at 13:00 +, Viorel Suman wrote:
> From: Shengjiu Wang
>
> Add regulator for ak4458.
>
Hi Viorel,
While at it please disable/enable the regulator in suspend/resume.
thanks,
Daniel.
codec phandle
Changes since v1:
- use "fsl,imx8mm-sai", "fsl,imx8mq-sai" compatbile strings and
remove "fsl,imx6sx-sai" because SAI module on i.MX8M is not
compatbile with SAI modules form i.MX6
RESEND to fix email encoding.
Daniel Baluta
* codec node
* simple-card configuration
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale
Hi Anson,
Since you are going to send a new version for this please consider my
comment inline.
> +static u32 imx8qxp_soc_revision(void)
> +{
> + struct imx_sc_msg_misc_get_soc_id msg;
> + struct imx_sc_rpc_msg *hdr = &msg.hdr;
> + u32 rev = 0;
No need to initialize this here
On Tue, May 14, 2019 at 2:34 AM Anson Huang wrote:
>
> Hi, Daniel
>
> > -Original Message-
> > From: Daniel Baluta [mailto:daniel.bal...@gmail.com]
> > Sent: Monday, May 13, 2019 10:30 PM
> > To: Anson Huang
> > Cc: catalin.mari...@arm.com; will.
On Tue, May 14, 2019 at 9:09 AM Anson Huang wrote:
>
> Unnecessary blank lines do NOT help readability, so remove them.
>
> Signed-off-by: Anson Huang
Reviewed-by: Daniel Baluta
> +
> +static u32 imx8qxp_soc_revision(void)
> +{
> + struct imx_sc_msg_misc_get_soc_id msg;
> + struct imx_sc_rpc_msg *hdr = &msg.hdr;
> + u32 rev = 0;
> + int ret;
> +
> + hdr->ver = IMX_SC_RPC_VERSION;
> + hdr->svc = IMX_SC_RPC_SVC_MISC;
> + hdr->func
g
> Signed-off-by: Viorel Suman
Reviewed-by: Daniel Baluta
> ---
> sound/soc/codecs/ak4458.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/sound/soc/codecs/ak4458.c b/sound/soc/codecs/ak4458.c
> index baf990a..7156215 100644
&g
-off-by: Viorel Suman
Reviewed-by: Daniel Baluta
> ---
> sound/soc/codecs/ak4458.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/sound/soc/codecs/ak4458.c b/sound/soc/codecs/ak4458.c
> index eab7c76..baf990a 100644
> --- a/sound/soc/codecs/
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale
* codec node
* simple-card configuration
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index
se SAI module on i.MX8M is not
compatbile with SAI modules form i.MX6
Daniel Baluta (2):
arm64: dts: imx8mm: Add SAI nodes
arm64: dts: imx8mm-evk: Enable audio codec wm8524
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 55
arch/arm64/boot/dts
From: Shengjiu Wang
Turn off/on clocks when device enters suspend/resume. This
can help saving power.
As a further optimization, we turn off/on mclk only when SAI
is in master mode because otherwise mclk is externally provided.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
* codec node
* simple-card configuration
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index
- remove codec phandle
Changes since v1:
- use "fsl,imx8mm-sai", "fsl,imx8mq-sai" compatbile strings and
remove "fsl,imx6sx-sai" because SAI module on i.MX8M is not
compatbile with SAI modules form i.MX6
Daniel Baluta (2):
arm64: dts: imx8
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale
Hi Marco,
On Tue, Apr 23, 2019 at 8:19 AM Marco Felsch wrote:
>
> Hi Daniel,
>
> On 19-04-22 19:36, Daniel Baluta wrote:
> > i.MX8MM has one wm8524 audio codec connected with
> > SAI3 digital audio interface.
> >
> > This patch uses simple-card machine driver
On Tue, Apr 23, 2019 at 8:21 AM Marco Felsch wrote:
>
> Hi Daniel,
>
> On 19-04-22 19:35, Daniel Baluta wrote:
> > i.MX8MM has 5 SAI instances with the following base
> > addresses according to RM.
> >
> > SAI1 base address: 3001_h
> > SAI2 base
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 48
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 2d5d89475b76..207b13266a96 100644
--- a/arch/arm64
l,imx6sx-sai" because SAI module on i.MX8M is not
compatbile with SAI modules form i.MX6
Daniel Baluta (2):
arm64: dts: imx8mm: Add SAI nodes
arm64: dts: imx8mm-evk: Enable audio codec wm8524
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 48 +
arch/arm64/boot/dts
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale
Basically the same actions as for system PM, so make use
of pm_runtime_force_suspend/pm_runtime_force_resume.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
---
sound/soc/fsl/fsl_sai.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/sound
On Mon, Apr 22, 2019 at 9:51 AM Daniel Baluta wrote:
>
> On Mon, Apr 22, 2019 at 5:45 AM Shawn Guo wrote:
> >
> > On Fri, Apr 19, 2019 at 08:20:39PM +0000, Daniel Baluta wrote:
> > > i.MX8MM has 5 SAI instances with the following base
> > > addresses ac
From: Shengjiu Wang
Turn off/on clocks when device enters suspend/resume. This
can help saving power.
As a further optimization, we turn off/on mclk only when SAI
is in master mode because otherwise mclk is externally provided.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
On Mon, Apr 22, 2019 at 5:45 AM Shawn Guo wrote:
>
> On Fri, Apr 19, 2019 at 08:20:39PM +, Daniel Baluta wrote:
> > i.MX8MM has 5 SAI instances with the following base
> > addresses according to RM.
> >
> > SAI1 base address: 3001_h
> > SAI2 base addre
.
Signed-off-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
---
arch/arm/boot/dts/imx6sx.dtsi | 6 --
arch/arm/boot/dts/imx6ul.dtsi | 9 ++---
arch/arm/boot/dts/imx7s.dtsi | 9 ++---
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch
i.MX8MM has 5 SAI instances with the following base
addresses according to RM.
SAI1 base address: 3001_h
SAI2 base address: 3002_h
SAI3 base address: 3003_h
SAI5 base address: 3005_h
SAI6 base address: 3006_h
Signed-off-by: Bai Ping
Signed-off-by: Daniel Baluta
---
arch
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 48
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 2d5d89475b76..207b13266a96 100644
--- a/arch
This patch series introduces the SAI nodes on i.MX8MM EVK then
creates the wm8524 codec node and finally uses simple card machine
driver to create a sound card.
Daniel Baluta (2):
arm64: dts: imx8mm: Add SAI nodes
arm64: dts: imx8mm-evk: Enable audio codec wm8524
arch/arm64/boot/dts
Hello Pengcheng,
Make sure you run ./scripts/checkpatch.pl --strict yourpatchfile.patch
On Thu, Feb 28, 2019 at 4:15 PM Pengcheng Li wrote:
>
> From: Youlin Wang
>
> Add i2s driver for hisi3660 soc found on the hikey960 board.
> Add conpile line in make file.
> Technical support by Guangke Ji.
lpuart nodes are part of the ADMA subsystem. See Audio DMA
memory map in iMX8 QXP RM [1]
This patch is based on the dtsi file initially submitted by
Teo Hall in i.MX NXP internal tree.
[1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
Signed-off-by: Teo Hall
Signed-off-by: Daniel
On Fri, Mar 29, 2019 at 5:22 PM Angus Ainslie (Purism) wrote:
>
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism)
Reviewed-by: Daniel Baluta
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 delet
On Fri, Mar 29, 2019 at 11:11 AM Aisheng Dong wrote:
>
> > From: Angus Ainslie (Purism) [mailto:an...@akkea.ca]
> > Sent: Thursday, March 28, 2019 9:38 PM
> >
> > Fix a typo in the compatible string
> >
> > Signed-off-by: Angus Ainslie (Purism)
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq.dt
On Thu, Mar 28, 2019 at 3:41 PM Angus Ainslie (Purism) wrote:
>
> The imx8mq needs to be specified to check the clk ratio.
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentati
On Thu, 2019-03-28 at 06:38 -0700, Angus Ainslie (Purism) wrote:
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism)
Reviwed-by: Daniel Baluta
On Thu, Mar 28, 2019 at 4:32 AM Aisheng Dong wrote:
>
> > From: Daniel Baluta
> > Sent: Thursday, March 28, 2019 3:03 AM
> >
> > i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily
> > for audio components and the other two are for non-audi
-manual/IMX8DQXPRM.pdf
Cc: Teo Hall
Signed-off-by: Daniel Baluta
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 72 ++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0cb939861a60
Add imx8qxp edma support.
Signed-off-by: Daniel Baluta
---
Documentation/devicetree/bindings/dma/fsl-edma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt
b/Documentation/devicetree/bindings/dma/fsl-edma.txt
index 97e213e07660
MA driver is similar
for 8QM/8QXP but it doesn't have yet support added for these boards
so just the compatible string closer to the actual hardware.
Daniel Baluta (2):
bindings: fsl-edma: Document fsl,imx8qxp-edma compatbile string
arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes
On Wed, Mar 27, 2019 at 11:33 AM Lucas Stach wrote:
>
> Hi Daniel,
>
> Am Mittwoch, den 27.03.2019, 10:51 +0200 schrieb Daniel Baluta:
> [...]
> >
> > > or
> > > "fsl,imx8qxp-edma", "fsl,imx8qm-edma"?
> >
> > One thing t
On Tue, Mar 26, 2019 at 11:44 PM Angus Ainslie wrote:
>
> On 2019-03-19 07:31, Shawn Guo wrote:
> > On Fri, Mar 08, 2019 at 12:02:22PM +0000, Daniel Baluta wrote:
> >> SDMA1 is part of AIPS-3 region and SDMA2 is part
> >> of AIPS-1 region.
> >>
> >>
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