On Tue, Jan 09, 2018 at 01:43:25AM +, Anson Huang wrote:
>
>
> Best Regards!
> Anson Huang
>
>
> > -Original Message-
> > From: Dong Aisheng [mailto:donga...@gmail.com]
> > Sent: 2018-01-08 6:39 PM
> > To: Anson Huang
> >
On Wed, Jan 03, 2018 at 07:22:14PM +0800, Anson Huang wrote:
> Remove unnecessary clocks for cpu-freq driver to
> avoid confusion.
>
> Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
Regards
Dong Aisheng
lcdif_pixel_pre_div
> lcdif_pixel_post_div
> lcdif_pixel_root_clk
>
> Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
Regards
Dong Aisheng
ime?
BTW, syscon-poweroff seems still not introduce clock support and
fsl,sec-v4.0-pwrkey also does not handle clock, they may need to
be added later.
Regards
Dong Aisheng
> ---
> arch/arm/boot/dts/imx7s.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/d
te.
>
> Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
Regards
Dong Aisheng
6ULL
>
> Stefan Agner (4):
> pinctrl: imx: use struct imx_pinctrl_soc_info as a const
> pinctrl: imx7d: simplify imx7d_pinctrl_probe
> pinctrl: imx: constify struct imx_pinctrl_soc_info
> pinctrl: imx7ulp: constify struct imx_cfg_params_decode
>
This patch series looks
ject devices form power domain,
+ * so we can't really remove power domains once they
+ * were added.
+ */
+.suppress_bind_attrs = true,
},
.probe = imx_gpc_probe,
- .remove = imx_gpc_remove,
};
builtin
igned-off-by: Peng Fan
> > > Cc: Shawn Guo
> > > Cc: Sascha Hauer
> > > Cc: Fabio Estevam
> > > Cc: Russell King
> > > Cc: Dong Aisheng
> >
> > @Aisheng, can you please give it a test?
> >
>
> Yes, of course.
>
Not su
On Tue, Dec 26, 2017 at 06:20:38PM +0800, Dong Aisheng wrote:
> On Tue, Dec 26, 2017 at 10:11:41AM +, Peng Fan wrote:
> >
> > Hi Aisheng,
> >
> > > -Original Message-
> > > From: Dong Aisheng [mailto:donga...@gmail.com]
> > > Sent: T
On Tue, Dec 26, 2017 at 10:11:41AM +, Peng Fan wrote:
>
> Hi Aisheng,
>
> > -Original Message-
> > From: Dong Aisheng [mailto:donga...@gmail.com]
> > Sent: Tuesday, December 26, 2017 6:04 PM
> > To: Peng Fan
> > Cc: Shawn Guo ; A.s. Dong ;
&g
gt; > Signed-off-by: Peng Fan
> > > Cc: Shawn Guo
> > > Cc: Sascha Hauer
> > > Cc: Fabio Estevam
> > > Cc: Russell King
> > > Cc: Dong Aisheng
> >
> > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
>
> I jus
On Fri, Dec 22, 2017 at 07:34:57PM +0100, Rafael J. Wysocki wrote:
> On Thursday, December 21, 2017 2:18:01 PM CET Dong Aisheng wrote:
> > Hi Rafael,
> >
> > On Thu, Sep 14, 2017 at 02:40:32PM -0700, Viresh Kumar wrote:
> > > On 31-08-17, 19:43, Dong Aisheng wrot
Those comments are invalid anymore. So remove them.
Cc: Stephen Boyd
Signed-off-by: Dong Aisheng
---
drivers/clk/clk.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d6e2d5c..4675adf 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
operations."
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
drivers/clk/clk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index e24968f..d6e2d5c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/c
: 9a34b45397e5 ("clk: Add support for runtime PM")
Signed-off-by: Dong Aisheng
---
drivers/clk/clk.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 5ec5809..e24968f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
On Thu, Dec 21, 2017 at 05:24:01PM -0800, Stephen Boyd wrote:
> On 12/20, Dong Aisheng wrote:
> > On Thu, Nov 02, 2017 at 12:50:39AM -0700, Stephen Boyd wrote:
> > > On 07/13, Dong Aisheng wrote:
> > > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-d
series then I think I can apply the
> > rest of it without you needing to resend. I'll check today.
> >
>
> I pushed it into clk-imx7ulp and merged that into clk-next. You
> can use that patch in your series.
>
Okay, great.
Thanks
Regards
Dong Aisheng
On Thu, Dec 21, 2017 at 03:20:32PM -0800, Stephen Boyd wrote:
> On 12/20, Dong Aisheng wrote:
> > On Fri, Sep 29, 2017 at 03:48:21PM -0700, Stephen Boyd wrote:
> > > On 09/26, Dong Aisheng wrote:
> > > > here to handle this for DT users without 'clock-nam
Hi Rafael,
On Thu, Sep 14, 2017 at 02:40:32PM -0700, Viresh Kumar wrote:
> On 31-08-17, 19:43, Dong Aisheng wrote:
> > Use clk_bulk_get to ease the driver clocks handling.
> >
> > Cc: "Rafael J. Wysocki"
> > Cc: Viresh Kumar
> > Cc: Shawn Guo
&
On Thu, Nov 02, 2017 at 12:36:09AM -0700, Stephen Boyd wrote:
> On 07/13, Dong Aisheng wrote:
> > The orphan clocks reparent operation should be moved after the critical
> > clocks enabled, otherwise it may get a chance to disable a newly
> > registered critical clock which t
On Thu, Nov 02, 2017 at 12:50:39AM -0700, Stephen Boyd wrote:
> On 07/13, Dong Aisheng wrote:
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 9bb472c..55f8c41 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-div
On Fri, Sep 29, 2017 at 03:48:21PM -0700, Stephen Boyd wrote:
> On 09/26, Dong Aisheng wrote:
> > 'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
>
> s/optinal/optional/
>
Got it.
> > here to handle this for DT users without &#
'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
here to handle this for DT users without 'clock-names' specified.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Russell King
Reported-by: Shawn Guo
Signed-off-by: Dong Aisheng
---
Changes since v3:
'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
here to handle this for DT users without 'clock-names' specified.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Russell King
Reported-by: Shawn Guo
Signed-off-by: Dong Aisheng
---
Changes since v2
rong git tree, please drop us a note to
> > help improve the system]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Dong-Aisheng/clk-bulk-add-of_clk_bulk_get/20170913-075645
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
>
On Tue, Sep 19, 2017 at 04:10:07PM -0700, Viresh Kumar wrote:
> On 24-08-17, 00:10, Dong Aisheng wrote:
> > If no valid transition_latency specified, let's make it default to
> > CPUFREQ_ETERNAL which is consistent with its definition.
> >
> > This can save some
Hi Viresh,
On Tue, Sep 19, 2017 at 03:58:40PM -0700, Viresh Kumar wrote:
> On 24-08-17, 00:10, Dong Aisheng wrote:
> > This is useful to support platforms which only the clk setting is
> > different from the generic OPP set rate but others like voltage
> > setti
'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
here to handle this for DT users without 'clock-names' specified.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Russell King
Reported-by: Shawn Guo
Signed-off-by: Dong Aisheng
---
Changes sin
On Mon, Sep 11, 2017 at 10:58:19AM +0200, Sylwester Nawrocki wrote:
> On 09/11/2017 09:36 AM, Dong Aisheng wrote:
> >'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
> >here to handle this for DT users without 'clock-names' specif
'clock-names' property is optinal in DT, so of_clk_bulk_get() is introduced
here to handle this for DT users without 'clock-names' specified.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Russell King
Reported-by: Shawn Guo
Signed-off-by: Dong Aisheng
---
drivers
Hi Viresh and Rafael,
On Thu, Aug 24, 2017 at 12:10:03AM +0800, Dong Aisheng wrote:
> This patch series does three things:
> 1) Add platform specific set_clk function
> 2) Add per OPP node clock support
> 3) Add imx7ulp cpufreq driver support
>
> 3 is depends on 1 & 2.
>
Hi Stephen,
On Thu, Jul 13, 2017 at 07:47:05PM +0800, Dong Aisheng wrote:
> This patch series intends to add imx7ulp clk support.
>
> i.MX7ULP Clock functions are under joint control of the System
> Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
> modules
On Thu, Aug 31, 2017 at 12:39:20PM -0500, Rob Herring wrote:
> On Thu, Aug 24, 2017 at 12:10:05AM +0800, Dong Aisheng wrote:
> > It's used for platforms where different OPPs may use different clocks.
> > With this extended binding, user could specify the correct clock f
Use clk_bulk_get to ease the driver clocks handling.
Cc: "Rafael J. Wysocki"
Cc: Viresh Kumar
Cc: Shawn Guo
Cc: Anson Huang
Cc: Leonard Crestez
Signed-off-by: Dong Aisheng
--
The original one is here which depends on clk_bulk APIs.
https://patchwork.kernel.org/patch/973733
dev_pm_opp_set_rate(). Then user can still use dev_pm_opp_set_rate()
with .set_clk() to save a lot duplicated work.
Cc: Viresh Kumar
Cc: Nishanth Menon
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Signed-off-by: Dong Aisheng
---
drivers/base/power/opp/c
"Rafael J. Wysocki"
Signed-off-by: Dong Aisheng
---
drivers/base/power/opp/core.c | 30 +++---
drivers/base/power/opp/opp.h | 4 ++--
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/base/power/opp/core.c b/drivers/base/power/opp/c
Kumar
Cc: Nishanth Menon
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
drivers/cpufreq/Kconfig.arm | 8 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/imx7ulp-cpufreq.c | 234 +++
User may need to know the current OPP clock for updating policy clk
accordingly. e.g. cpufreq policy clock.
This function does the work.
Cc: Viresh Kumar
Cc: Nishanth Menon
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Signed-off-by: Dong Aisheng
---
drivers/base/power/opp/c
tency)
- transition_latency = CPUFREQ_ETERNAL;
ret = cpufreq_generic_init(policy, freq_table, transition_latency);
Cc: Viresh Kumar
Cc: Nishanth Menon
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Signed-off-by: Dong Aisheng
---
drivers/cpufreq/cpufreq.c | 2 ++
1 file change
If OPP node has a valid clock, we use this corresponding OPP clock to
set the device clock frequency instead of the default opp_table->clk which
is shared by all OPPs.
Cc: Viresh Kumar
Cc: Nishanth Menon
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Signed-off-by: Dong Aisheng
---
nd
Cc: devicet...@vger.kernel.org
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bindings/opp/opp.txt | 52 +++
1 file changed, 52 insertions(+)
diff --git a/Documentation/devicetree/bindings/opp/opp.txt
b/Documentation/devicetree/bindings/opp/opp.txt
index e36d261..40a43
clock to set CPU frequency"
And since IMX7ULP CPU clock setting is different from the generic
set OPP clock, we also implemented a private set_clk function.
Dong Aisheng (7):
PM / OPP: Add platform specific set_clk function
dt-bindings: PM / OPP: add clocks per OPP node support
PM
readl/writel from __raw_readl/writel according to Arnd's
suggestion to avoid endian issue
* add help information in Kconfig
* add more error checking
Dong Aisheng (2):
dt-bindings: timer: add nxp tpm timer binding doc
clocksource/drivers/imx-tpm: add imx tpm timer support
.../devicetr
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Bai Ping
Acked-by: Rob Herring
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v5:
* No chan
: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* use request_irq instead of setup_irq
* switch to TIMER_OF_DECLARE from CLOCKSOURCE_OF_DECLARE
* add more error check
* patch title change to clocksource/drivers/imx-tpm: add imx tpm timer support
v3->v4:
* al
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
ENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signe
wn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* add more detailed commit messages
---
drivers/clk/clk.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fc58c52..e2955b1 100644
: Dong Aisheng
---
ChangeLog:
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile| 3 +-
drivers/clk/imx/clk-pfdv2.c |
- Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++
include/linux/clk-provider.h | 8
2 files changed,
d the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
-
: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* ot
CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possi
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h |
Rutland
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt| 62
include/dt-bindings/clock/imx7ulp-clock.h |
pis to register clocks
* use of_clk_add_hw_provider
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
Dong Aisheng (10):
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Bai Ping
Acked-by: Rob Herring
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v4:
* No chan
: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* also add ETIME explanation in function
v2->v3:
* address all comments from Daniel Lezcano
* add more explaination on ETIME check in commit message
v1->v2:
* change to readl/writel from __raw_readl/writel
ezcano
* add more explaination on ETIME check in commit message
v1->v2:
* change to readl/writel from __raw_readl/writel according to Arnd's
suggestion to avoid endian issue
* add help information in Kconfig
* add more error checking
Dong Aisheng (2):
dt-bindings: timer: add nxp tpm
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Bai Ping
Acked-by: Rob Herring
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v3:
* No chan
contention, the CNT write may
take a few more cycles and we need add ETIME check in case current
delta event program gets missed.
Cc: Daniel Lezcano
Cc: Arnd Bergmann
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* addr
mit message
v1->v2:
* change to readl/writel from __raw_readl/writel according to Arnd's
suggestion to avoid endian issue
* add help information in Kconfig
* add more error checking
Dong Aisheng (2):
dt-bindings: timer: add nxp tpm timer binding doc
timer: imx-tpm: add imx tpm ti
On Mon, Jun 19, 2017 at 07:01:19PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > +
> > + clks[IMX7ULP_CLK_VIU] = imx_clk_gate("viu", "nic1_clk",
> > base + 0xA0, 30);
> > + clks[IMX7ULP_CLK_PCTLC] =
On Mon, Jun 19, 2017 at 06:59:17PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
> > diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
> > new file mode 100644
> > index 000..502da64
On Mon, Jun 19, 2017 at 07:00:13PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> > index 51b84e4..665777e 100644
> > --- a/drivers/clk/imx/clk.h
> > +++ b/drivers/clk/imx/clk.h
> &
On Mon, Jun 19, 2017 at 06:55:47PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> > index a6efbb9..4466cae 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/c
On Mon, Jun 19, 2017 at 06:51:40PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > The orphan clocks reparent operation should be moved after the critical
> > clocks enabled, otherwise it may get a chance to disable a newly registered
> > critical clock which t
Hi Stephen,
On Mon, Jun 19, 2017 at 06:45:12PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > ---
> > drivers/clk/clk-divider.c| 2 ++
> > include/linux/clk-provider.h | 4
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/
Hi Jmondi,
On Thu, Jun 15, 2017 at 7:11 PM, jmondi wrote:
> Hi Dong,
>
> On Tue, Jun 13, 2017 at 02:25:08PM +0800, Dong Aisheng wrote:
>> On Mon, Jun 12, 2017 at 5:44 PM, jmondi wrote:
>> > Fair enough :)
>> >
>> > I'll try to keep this short: I d
On Tue, Jun 13, 2017 at 03:54:24PM +0200, Daniel Lezcano wrote:
> On 13/06/2017 09:58, Dong Aisheng wrote:
> > IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> > this patch only adds the timer support. PWM would be added later.
> >
> > The TPM c
On Tue, Jun 13, 2017 at 10:19:47AM +0200, Alexander Stein wrote:
> On Tuesday 13 June 2017 15:58:45, Dong Aisheng wrote:
> > diff --git a/drivers/clocksource/timer-imx-tpm.c
> > b/drivers/clocksource/timer-imx-tpm.c new file mode 100644
> > index 000..940a4f75
> &
Hi Stephen,
On Sat, Jun 3, 2017 at 6:40 AM, Stephen Boyd wrote:
> On 05/19, Dong Aisheng wrote:
>> These helper function allows drivers to get several clk consumers in
>> one operation. If any of the clk cannot be acquired then any clks
>> that were got will be put be
an issue
* add help information in Kconfig
* add more error checking
Dong Aisheng (2):
dt-bindings: timer: add nxp tpm timer binding doc
timer: imx-tpm: add imx tpm timer support
.../devicetree/bindings/timer/nxp,tpm-timer.txt| 28 +++
drivers/clocksource/Kconfig
Bergmann
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* change to readl/writel from __raw_readl/writel according to Arnd's
suggestion to avoid endian issue
* add help information in Kconfig
* add more error
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Bai Ping
Acked-by: Rob Herring
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* No chan
On Mon, May 15, 2017 at 09:59:14PM +0800, Dong Aisheng wrote:
> This patch series intends to add imx7ulp clk support.
>
> i.MX7ULP Clock functions are under joint control of the System
> Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
> modules, and Core Mode Co
On Mon, Jun 12, 2017 at 5:44 PM, jmondi wrote:
> Hi Linus,
>
> On Sun, Jun 11, 2017 at 11:45:49PM +0200, Linus Walleij wrote:
>> On Fri, Jun 9, 2017 at 9:50 AM, jmondi wrote:
>> > On Fri, Jun 09, 2017 at 03:26:57PM +0800, Dong Aisheng wrote:
>>
>> >> >
ah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Cc: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* No changes
v2->v3:
* use standard port->iotype to represent the endians.
v1->v2:
* remove lpuart_reg_off according to Stefan's suggest
-off-by: Dong Aisheng
---
Change Log:
v3->v4:
* No changes
v2->v3:
* use standard port->iotype to represent endians
v1->v2:
* updated due to lpuart_reg_off removed
---
drivers/tty/serial/fsl_lpuart.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/driver
instantiations.
Loop to find the best OSR value possible, one that generates minimum
baud diff iterate through the rest of the supported values of OSR.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog
also works with
earlycon.
v1->v2:
* Patch 2/4/5 chagned, other no changes.
See individuals for details.
Dong Aisheng (7):
tty: serial: lpuart: introduce lpuart_soc_data to represent SoC
property
tty: serial: lpuart: refactor lpuart32_{read|write} prototype
tty: serial: lp
Cc: Fugang Duan
Cc: Andy Shevchenko
Cc: Nikita Yushchenko
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* remove one duplicated blank line
v2->v3:
* use standard iotype flags instead of private is_32 member
v1->v2:
* make all soc_data const
---
drivers/tty/serial/fsl_lpua
kai Hu
Cc: Yangbo Lu
Cc: Fugang Duan
Cc: Andy Shevchenko
Cc: Nikita Yushchenko
Signed-off-by: Dong Aisheng
ChangeLog:
v3->v4:
* Removed unneeded semicolon catched by 0day Robot.
v2->v3:
* Instead of using global var, use standard port->iotype to distinguish
endian difference.
v
efan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Rob Herring
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
* No changes
---
Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/
Cc: Nikita Yushchenko
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* No changes
v2->v3:
* newly introduced
---
drivers/tty/serial/fsl_lpuart.c | 123
1 file changed, 62 insertions(+), 61 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart
Hi Fengguang,
On Tue, Jun 13, 2017 at 08:28:41AM +0800, kbuild test robot wrote:
> drivers/tty/serial/fsl_lpuart.c:305:2-3: Unneeded semicolon
>
>
> Remove unneeded semicolon.
>
> Generated by: scripts/coccinelle/misc/semicolon.cocci
>
> CC: Dong Aisheng
>
On Mon, Jun 12, 2017 at 08:49:36PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 12, 2017 at 6:37 PM, Dong Aisheng wrote:
> > This is used to dynamically check the SoC specific lpuart properies.
> > Currently only the iotype is added, it functions the same as before.
> > With
atch 2/4/5 chagned, other no changes.
See individuals for details.
Dong Aisheng (7):
tty: serial: lpuart: introduce lpuart_soc_data to represent SoC
property
tty: serial: lpuart: refactor lpuart32_{read|write} prototype
tty: serial: lpuart: add little endian 32 bit register support
ah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Cc: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* use standard port->iotype to represent the endians.
v1->v2:
* remove lpuart_reg_off according to Stefan's suggestion
---
drivers/tty/
efan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Rob Herring
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
b/Doc
-off-by: Dong Aisheng
---
Change Log:
v2->v3:
* use standard port->iotype to represent endians
v1->v2:
* updated due to lpuart_reg_off removed
---
drivers/tty/serial/fsl_lpuart.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/t
Cc: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* use standard iotype flags instead of private is_32 member
v1->v2:
* make all soc_data const
---
drivers/tty/serial/fsl_lpuart.c | 48 -
1 file changed, 28 insertions(+), 20 del
rgument
to make it be able to retrieve more port specific information.
This is a preparation for the later adding new chips support
more easily. No functions changes.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Cc: Fugang Duan
Signed-off-by: Do
kai Hu
Cc: Yangbo Lu
Cc: Fugang Duan
Signed-off-by: Dong Aisheng
ChangeLog:
v2->v3:
* Instead of using global var, use standard port->iotype to distinguish
endian difference.
v1->v2:
* No changes
---
drivers/tty/serial/fsl_lpuart.c | 43 +++--
instantiations.
Loop to find the best OSR value possible, one that generates minimum
baud diff iterate through the rest of the supported values of OSR.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog
quot;input-enable".
>
> I'll let you and DT people decide on this, as it's really an ABI definition
> problem and you have better judgment there.
>
What's the final decision of this?
I saw the following revert patch in pinctrl-next but did not see a successive
patch t
With struct uart_port's iotype member, the global lpuart_is_be can be
gone. We can update lpuart32_read/write API to take the reference of
of structure uart_port, then the API knows the endian information and
can use the correct further IO accessor accordingly.
And most importantly, it also works with earlycon.
> Another example is drivers/tty/serial/samsung.c, where
> port->private_data is initialized and used.
>
If using iotype, seems no need private_data anymore.
Will try and send the new series later with you CCed to help review.
Thanks for the advice.
Regards
Dong Aisheng
Hi Andy,
On Wed, May 17, 2017 at 12:55:59PM +0300, Andy Shevchenko wrote:
> On Wed, May 17, 2017 at 8:43 AM, Dong Aisheng wrote:
> > On Wed, May 17, 2017 at 08:37:41AM +0300, Nikita Yushchenko wrote:
> >>
> >>
> >> 17.05.2017 06:39, Dong Aisheng wrote:
>
Hi Daniel,
On Thu, May 25, 2017 at 10:54:55PM +0200, Daniel Lezcano wrote:
> On Sat, May 13, 2017 at 03:29:35PM +0800, Dong Aisheng wrote:
> > IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> > this patch only adds the timer support. PWM would be added late
Hi Arnd,
On Thu, May 25, 2017 at 11:02:22PM +0200, Arnd Bergmann wrote:
> On Sat, May 13, 2017 at 9:29 AM, Dong Aisheng wrote:
>
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 3356ab8..03dfd6a 100644
> > --- a/drivers/clocksource/K
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