>> pass those flags to pin controller).
>
> Sounds like a case for
>
> renesas,bi-directional;
> renesas,output-enable;
>
> following the Qualcomm pattern in that case.
>
> But let's see if something else comes out of this discussion.
>
I did not follow too much.
But it seems IMX7ULP/Vybrid to be also a fan of generic
output-enable/input-enable
property.
See:
Figure 5-2. GPIO PAD in Page 241
http://www.nxp.com/assets/documents/data/en/reference-manuals/VFXXXRM.pdf
It has separate register bits to control input buffer enable and
output buffer enable
and we need set it property for GPIO function.
Regards
Dong Aisheng
writel();
}
lpuart32_be_console_write() {
iowrite32be()
}
This also makes the driver a bit strange and ugly.
It looks to me both way are trade offs and the later one seems sacrifice
more. And i doubt if it's really necessary for probably a no real gain
purpose as the FPGA you menti
g
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3: no changes
v1->v2: only one minor comment change
---
drivers/clk/clk-devres.c | 36
include/linux/clk.h | 21 +
2 f
i Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v3: No changes
---
drivers/cpufreq/imx6q-cpufreq.c | 119 ++--
1 file changed, 53 insertions(+), 66 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufre
Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* release resource in reversed order in case an error according to
Geert Uytterhoeven's suggestion
v1->v2:
* fix comments of clk_bulk_get that only one dev is possible with the API.
* Comments 'bulk of clock s
DEV_LOOKUP platforms build break.
Other are comments fix, adding const annotation and etc.
Refer to individual patches for details.
[v1] https://lkml.org/lkml/2017/4/11/335
[v2] https://lkml.org/lkml/2017/5/8/276
Dong Aisheng (3):
clk: add clk_bulk_get accessories
clk: add managed version
On Wed, May 17, 2017 at 10:35:43AM -0700, Stefan Agner wrote:
> On 2017-05-16 20:47, Dong Aisheng wrote:
> > On Mon, May 15, 2017 at 10:06:41AM -0700, Stefan Agner wrote:
> >> On 2017-05-15 00:48, Dong Aisheng wrote:
> >> > On new LPUART versions, the oversampling
or earlycon.
It looks to me having the same issue with a separate write patch
for earlycon as we still need distinguish Little or Big endian
for Layerscape and IMX.
> At a glance, it is dozen lines of code.
Would you please show some sample code?
Then we probably may understand better with each other.
Anyway, thanks for detailed review.
Regards
Dong Aisheng
r code states, "force BE if lpuart_is_be, don't care otherwise".
> This semantics looks questionable for code reviewer.
> If driver handles endian, should't it be explicit in both cases?
> And if indeed driver means handling BE explicitly, but don't caring
> otherwise, maybe variable name should suggest that (i.e. "force_be")?
>
For lpuart32, only two cases that LS platforms is Big endian while
IMX is little endian.
It's SoC IP native property, i don't think force_be is better.
Regards
Dong Aisheng
> Although driver maintainer could think differently. I won't insist on this.
>
> Nikita
On Wed, May 17, 2017 at 08:37:41AM +0300, Nikita Yushchenko wrote:
>
>
> 17.05.2017 06:39, Dong Aisheng wrote:
> > On Tue, May 16, 2017 at 02:15:08PM +0300, Nikita Yushchenko wrote:
> >>> static u32 lpuart32_read(void __iomem *addr)
> >>> {
> >
On Mon, May 15, 2017 at 10:06:41AM -0700, Stefan Agner wrote:
> On 2017-05-15 00:48, Dong Aisheng wrote:
> > On new LPUART versions, the oversampling ratio for the receiver can be
> > changed from 4x (00011) to 32x (1) which could help us get a more
> > accurate baud rate
lpuart32_write(u32 val, void __iomem *addr)
> > {
> > - iowrite32be(val, addr);
> > + if (lpuart_is_be)
> > + iowrite32be(val, addr);
> > + else
> > + writel(val, addr);
> > }
>
> What if this is ever executed on big endian system?
>
Sorry, not catching the point...
What issues will meet?
Regards
Dong Aisheng
->is_be;
>
> Setting a global variable in per-device routine is quite bad design.
>
There is a reason for that we don't want to change the exist
lpuart32_read[write] API which is widely used in driver.
Making a global lpuart_is_be is the simplest way to do it.
Any strong blocking reason?
Regards
Dong Aisheng
On Mon, May 15, 2017 at 04:36:25PM +0300, Andy Shevchenko wrote:
> On Mon, May 15, 2017 at 10:48 AM, Dong Aisheng wrote:
> > It's based on the exist lpuart32 read/write implementation.
>
> Same as per previous comment (perhaps not in other UART driver, but
> some might
) from [<6000807c>] (0x6000807c)
[0.00] r10: r9:410fc075 r8:6000406a r7:c0e0c930 r6:c0d61a44
r5:c0e07918
[0.00] r4:c0e78294
[0.00] ---[ end trace ]---
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
d
- Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
drivers/clk/clk-fractional-divider.c | 10 ++
include/linux/clk-provider.h | 7 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c
uld be aware of
setting a correct rate before using.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
drivers/clk/clk-divider.c| 2 ++
include/linux/clk-provider.h | 4
2 files change
CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 171 ++
2 files changed
ENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-
Rutland
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
.../devicetree/bindings/clock/imx7ulp-clock.txt| 62
include/dt-bindings/clock/imx7ulp-clock.h | 108 +
2 files changed, 170
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
: Dong Aisheng
---
drivers/clk/imx/Makefile| 3 +-
drivers/clk/imx/clk-pfdv2.c | 199
drivers/clk/imx/clk.h | 3 +
3 files changed, 204 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx
, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this series only adds A7 clock domain support as M4 clock
domain will be handled by M4 seperately.
Dong Aisheng (9):
clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
clk: reparent orphans after
: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-pllv4.c | 196
drivers/clk/imx/clk.h | 3 +
3 files changed, 200 insertions(+)
create mode
earlycon is executed quite early before the device tree probe,
so we need configure the correct reg_off for imx7ulp during
early console setup.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
Change
: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* make all soc_data const
---
drivers/tty/serial/fsl_lpuart.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/ser
-off-by: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 85 ++---
1 file changed, 79 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 107d0911..bda4b0c 100644
--- a/drivers/tty/serial
efan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Rob Herring
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
b/Doc
It's based on the exist lpuart32 read/write implementation.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby (supporter:TTY LAYER)
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 12 ++--
1 file change
ah-Hartman
Cc: Jiri Slaby
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Acked-by: Fugang Duan
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* remove lpuart_reg_off according to Stefan's suggestion
---
drivers/tty/serial/fsl_lpuart.c | 13 +
1 file changed, 13 inserti
the old stuff.
ChangeLog:
v1->v2:
* Patch 2/4/5 chagned, other no changes.
See individuals for details.
Dong Aisheng (6):
tty: serial: lpuart: introduce lpuart_soc_data to represent SoC
property
tty: serial: lpuart: add little endian 32 bit register support
dt-bindings: serial: fsl-
Gleixner
Cc: Shawn Guo
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Dong Aisheng
---
drivers/clocksource/Kconfig | 5 +
drivers/clocksource/Makefile| 1 +
drivers/clocksource/timer-imx-tpm.c | 204
3 files changed
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Shawn Guo
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
.../devicetree/bindings/timer/nxp,tpm-timer.txt
On Wed, May 10, 2017 at 01:37:07PM -0700, Stefan Agner wrote:
> On 2017-05-09 23:14, Dong Aisheng wrote:
> > Hi Stefan,
> >
> > On Wed, May 10, 2017 at 12:10 PM, Stefan Agner wrote:
> >> On 2017-05-09 00:50, Dong Aisheng wrote:
> >>> The lpuart of imx7
On Wed, May 10, 2017 at 11:58 AM, Stefan Agner wrote:
> On 2017-05-09 00:50, Dong Aisheng wrote:
>> It's based on the exist lpuart32 read/write implementation.
>>
>> Cc: Greg Kroah-Hartman
>> Cc: Jiri Slaby (supporter:TTY LAYER)
>> Cc: Fugang Duan
>>
Hi Stefan,
On Wed, May 10, 2017 at 12:10 PM, Stefan Agner wrote:
> On 2017-05-09 00:50, Dong Aisheng wrote:
>> The lpuart of imx7ulp is basically the same as ls1021a. It's also
>> 32 bit width register, but unlike ls1021a, it's little endian.
>> Besides that, imx7u
Hi Stefan,
On Wed, May 10, 2017 at 11:50 AM, Stefan Agner wrote:
> On 2017-05-09 00:50, Dong Aisheng wrote:
>> This is used to dynamically check the SoC specific lpuart properies.
>> Currently only the checking of 32 bit register width is added which
>> functions the same as
Hi Geert,
On Mon, May 8, 2017 at 11:08 PM, Geert Uytterhoeven
wrote:
> Hi Dong,
>
> On Mon, May 8, 2017 at 4:03 PM, Dong Aisheng wrote:
>> --- /dev/null
>> +++ b/drivers/clk/clk-bulk.c
>> @@ -0,0 +1,165 @@
>
>> +int __must_check clk_bulk_
: Mingkai Hu
Cc: Yangbo Lu
Signed-off-by: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 15df1ba7..cd4e905 100644
--- a/drivers
: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 85 ++---
1 file changed, 79 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 5b485e8..6b2abb7 100644
--- a/drivers/tty/serial/fsl_lpuart.c
earlycon is executed quite early before the device tree probe,
so we need configure the correct reg_off for imx7ulp during
early console setup.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: Fugang Duan
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Signed-off-by: Dong Aisheng
---
drivers/tty
ah-Hartman
Cc: Jiri Slaby
Cc: Fugang Duan
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Signed-off-by: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/
It's based on the exist lpuart32 read/write implementation.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby (supporter:TTY LAYER)
Cc: Fugang Duan
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Signed-off-by: Dong Aisheng
---
drivers/tty/serial/fsl_lpuart.c | 12 ++--
1 file change
Jiri Slaby
Cc: Fugang Duan
Cc: Stefan Agner
Cc: Mingkai Hu
Cc: Yangbo Lu
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
b/Documentation/
As i don't have Layerscape boards, i can't test it, so i only enable it
for MX7ULP by default to avoid a potential break.
I copied LayerScape guys in this series and hope they can help test later.
If it works on Layerscape as well, then they can switch to the new setting
too and totally re
Huang
Cc: Robin Gong
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2: only one minor comment change
---
drivers/clk/clk-devres.c | 36
include/linux/clk.h | 21 +
2 file
Cc: Robin Gong
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2: No changes
---
drivers/cpufreq/imx6q-cpufreq.c | 119 ++--
1 file changed, 53 insertions(+), 66 deletions(-)
diff --git a/drivers/
ard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v2:
* fix comments of clk_bulk_get that only one dev is possible with the API.
* Comments 'bulk of clock source' replaced by 'set of clks'
* Mark clk_bulk_data structure as const for the foll
ARCH=m68k
make.cross ARCH=ia64
ChangeLog:
v1->v2:
Most significant change is introducing clk-bulk.c to centrally
handle bulk_clks and fix !CONFIG_CLKDEV_LOOKUP platforms build break.
Other are comments fix, adding const annotation and etc.
Refer to individual patches for details.
[v1] https://lkml
On Fri, Apr 21, 2017 at 07:58:37PM -0700, Stephen Boyd wrote:
> On 04/13, Dong Aisheng wrote:
> > On Wed, Apr 12, 2017 at 12:03:28PM +0800, Dong Aisheng wrote:
> >
> >drivers/built-in.o: In function `devm_clk_bulk_get':
> > >> (.text+0x1930e)
On Fri, Apr 21, 2017 at 07:55:47PM -0700, Stephen Boyd wrote:
> On 04/12, Dong Aisheng wrote:
> > diff --git a/include/linux/clk.h b/include/linux/clk.h
> > index 1d05b66..3fc6010 100644
> > --- a/include/linux/clk.h
> > +++ b/include/linux/clk.h
> > @@ -278,
On Fri, Apr 21, 2017 at 08:16:47PM -0700, Stephen Boyd wrote:
> On 04/12, Dong Aisheng wrote:
> >
> > #ifdef CONFIG_HAVE_CLK
> > @@ -230,6 +257,32 @@ static inline void clk_unprepare(struct clk *clk)
> > struct clk *clk_get(struct
On Fri, Apr 21, 2017 at 08:04:19PM -0700, Stephen Boyd wrote:
> On 04/12, Dong Aisheng wrote:
> >
> > Together with the err path handling for each clocks, it does make
> > things a bit ugly.
> >
> > Since we already have regulator_bulk_get accessories, i though
We actually can't allow the missing of the regualor name, thus update
the binding doc to make regulator-name property to be required.
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Mark Brown
Acked-by: Rob Herring
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bin
Hi Geert,
On Thu, Apr 13, 2017 at 09:56:31PM +0200, Geert Uytterhoeven wrote:
> On Wed, Apr 12, 2017 at 6:03 AM, Dong Aisheng wrote:
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -520,6 +520,23 @@ void clk_unprepare(struct clk *clk)
> > }
> >
gpio_spi@0 {
>
> gpio-expander might be a better node name?
>
> > + compatible = "fairchild,74hc595";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + reg = <0>;
> > + registers-number = <1>;
> > +/* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
> > + registers-default = /bits/ 8 <0x74>;
>
> I do not see this property is documented or supported by kernel.
It's FSL internal invented property to do some trick on register
intialization and should be dropped.
Regards
Dong Aisheng
gpr: iomuxc-gpr@3034 {
> - compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
> + compatible = "fsl,imx7d-iomuxc-gpr",
> + "fsl,imx6q-iomuxc-gpr"
t;;
> >> +
> >> + pgc_pcie_phy: pgc-pcie-phy-domain {
> >
> > The node name should be something generic and has a unit-address when
> > there is a 'reg' property in the node.
> >
>
> I'll change it to pgc-power-domain@0, let me know if you want
> something different.
>
I think just power-domain@0 is ok.
And also better replace unit-address by macro.
Regards
Dong Aisheng
anatop-max-voltage = <120>;
> - anatop-enable-bit = <31>;
> + anatop-enable-bit = <0>;
The change of this line seems already exist in patch 1.
Regards
Dong Aisheng
We actually can't allow the missing of the regualor name, thus update
the binding doc to make regulator-name property to be required.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Signed-off-by: Dong Aisheng
---
Documentation/devicetree/bindings/regulator/a
For anatop regulator we must have a name accordingly. Make sure the name
is properly checked before using it to avoid a possible kernel NULL
point crash.
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulator.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
On Thu, Apr 13, 2017 at 07:03:16PM +0100, Mark Brown wrote:
> Rather than just not resolving the supply when there is explicitly no
> supply mapping fall through and allow a dummy supply to be substituted.
>
> Signed-off-by: Mark Brown
Tested-by: Dong Aisheng
Reviewed-by:
lacks some of the voltage operations.
>
> Reported-by: Dong Aisheng
> Signed-off-by: Mark Brown
> ---
>
> Untested.
>
Thanks for the fix.
Tested-by: Dong Aisheng
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
On Wed, Apr 12, 2017 at 12:03:28PM +0800, Dong Aisheng wrote:
> This patch introduces the managed version of clk_bulk_get.
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: "Rafael J. Wysocki"
> Cc: Viresh Kumar
> Cc: Mark Brown
> Cc: Shawn Guo
> Cc: Fa
On Wed, Apr 12, 2017 at 12:03:27PM +0800, Dong Aisheng wrote:
...
> @@ -445,6 +543,12 @@ static inline struct clk *clk_get(struct device *dev,
> const char *id)
> return NULL;
> }
>
> +static inline int clk_bulk_get(struct device *dev, int num_clks,
> +
On Tue, Apr 11, 2017 at 08:48:28PM +0300, Leonard Crestez wrote:
> On Wed, 2017-04-12 at 12:03 +0800, Dong Aisheng wrote:
> > +static int num_clks;
> > +static struct clk_bulk_data clks[] = {
> > + { .id = "arm" },
> > + { .id = "pll1_sys" },
>
On Tue, Apr 11, 2017 at 08:19:19PM +0300, Leonard Crestez wrote:
> On Wed, 2017-04-12 at 12:03 +0800, Dong Aisheng wrote:
> > +/**
> > + * clk_bulk_enable - ungate a bulk of clocks
> > + * @num_clks: the number of clk_bulk_data
> > + * @clks: the clk_bu
CH_BRCMSTB platforms in our downstream tree with a concept of a
> "software" clock which has multiple parents (yikes), using the bulk
> accessors would essentially allow us to remove part of this hack, so I
> am all in favor of this!
Glad to see someone else has the same idea!
Ah, of course. That'll work but I don't think it's the best solution -
> there are some other regulators that also won't support setting voltages
> but might get used as supplies so we should do something based on the
> properties of the regulator rather than based specifically on the dummy
> regulator. Let me see..
Yes, i was also wondering that..
Let's waiting for you...
Thanks
Regards
Dong Aisheng
On Wed, Apr 12, 2017 at 11:49 PM, Mark Brown wrote:
> On Thu, Apr 13, 2017 at 03:41:03PM +0800, Dong Aisheng wrote:
>> On Tue, Apr 11, 2017 at 09:40:03PM +0100, Mark Brown wrote:
>
>> > Why is this the only anatop regulator which can have this problem and
>> > how d
On Wed, Apr 12, 2017 at 11:53 PM, Mark Brown wrote:
> On Thu, Apr 13, 2017 at 03:11:01PM +0800, Dong Aisheng wrote:
>
>> You're absolutely right!
>> I did this because there're some where else did the same thing.
>> e.g. drivers/regulator/fixed.c.
>
>&
On Tue, Apr 11, 2017 at 09:40:03PM +0100, Mark Brown wrote:
> On Wed, Apr 12, 2017 at 09:58:47AM +0800, Dong Aisheng wrote:
> > Set the initial voltage selector for vddpcie in case it's disabled
> > by default.
>
> Why is this the only anatop regulator which can have th
On Tue, Apr 11, 2017 at 09:38:18PM +0100, Mark Brown wrote:
> On Wed, Apr 12, 2017 at 09:58:46AM +0800, Dong Aisheng wrote:
> > rdesc->name/regulator-name is optional according to standard regulator
> > binding doc. Use it conditionally to avoid a kernel NULL point crash.
>
Hi Mark,
On Tue, Apr 11, 2017 at 09:31:24PM +0100, Mark Brown wrote:
> On Wed, Apr 12, 2017 at 09:58:43AM +0800, Dong Aisheng wrote:
> > Mandatorily set the initdata->supply_regulator while it actually not
> > exist will cause regulator core to resolve supply each time
: Octavian Purdila
Signed-off-by: Dong Aisheng
---
drivers/clk/clk-devres.c | 36
include/linux/clk.h | 22 +-
2 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
index 3a218c
an Purdila
Signed-off-by: Dong Aisheng
---
drivers/cpufreq/imx6q-cpufreq.c | 119 ++--
1 file changed, 53 insertions(+), 66 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 7719b02..6158910 100644
--- a/drivers/cpu
error reporting.
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: "Rafael J. Wysocki"
Cc: Viresh Kumar
Cc: Mark Brown
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Sascha Hauer
Cc: Anson Huang
Cc: Robin Gong
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
-
ally, if we handle clocks more than 3, then it might be
worthy to try, which there is quite many manay in kernel and
that probably could save a lot codes.
This is a RFC patch intending to bring up the idea to discuss.
Comments are welcome and appreciated!
Dong Aisheng (3):
clk: add clk_bulk_get
dwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Cc: Richard Zhu
Signed-off-by: Richard Zhu
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulator.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regu
rdesc->name/regulator-name is optional according to standard regulator
binding doc. Use it conditionally to avoid a kernel NULL point crash.
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulato
sreg->name is only used as an intermediate assign of rdesc->name, plus
another strcmp. Since we already have rdesc->name, no need it anymore.
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-re
sreg->name is a string, so use a more proper api to read back the string
instead of of_get_property.
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulator.c | 3 ++-
1 file changed, 2 inserti
SDB board booting up.
This patch adds the condition check for vin-supply to avoid the issue.
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulator.c | 4 +++-
1 file changed, 3 insertions(+), 1 delet
Should check the return value of of_get_regulator_init_data before
using it.
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Robin Gong
Signed-off-by: Dong Aisheng
---
drivers/regulator/anatop-regulator.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers
ince they
> are part of the i.MX 7 clock drivers init_on list. This might
> change in the future.
>
> Signed-off-by: Stefan Agner
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> ---
> This patch depends on "clk: imx7d: add the missing ipg_root_clk"
> which adds
On Mon, Apr 10, 2017 at 02:00:14PM -0700, Stefan Agner wrote:
> The USDHC NAND root clock is not gated by any CCM clock gate. Remove
> the bogus gate definition.
>
> Signed-off-by: Stefan Agner
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> ---
> drivers/clk/imx/clk-imx7d.c
On Fri, Mar 31, 2017 at 02:28:11PM +0200, Lucas Stach wrote:
> Hi Dong,
>
> Am Samstag, den 01.04.2017, 12:10 +0800 schrieb Dong Aisheng:
> [...]
> > > If we need the domains to be up before the consumers, the only
> > > way to deal with t
the parent ahb_root_clk got registered, the clk core
will reparent it to the newly found parent. (see __clk_core_init() function).
Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during
set_parent operation and then disabled after that.
Then system hang cause we still get no chance to run init_on clks.
I just send out a proper fix patch with correct register sequence.
Probably we can switch all imx clk driver to CLK_IS_CRITICAL for critical
clocks in the future, but that's another thing to do later.
Stefan,
I think you can just resend your series based on my patches.
Regards
Dong Aisheng
> --
> Stefan
Hi Lucas,
Thanks for the explaination.
On Wed, Mar 29, 2017 at 06:08:31PM +0200, Lucas Stach wrote:
> Hi Dong,
>
> Am Donnerstag, den 30.03.2017, 15:51 +0800 schrieb Dong Aisheng:
> > Hi Lucas,
> >
> > On Thu, Mar 23, 2017 at 03:35:49PM +0100, Lucas Stach wrote:
>
reg = <0x30b4 0x1>;
> interrupts = ;
> clocks = <&clks IMX7D_CLK_DUMMY>,
Would you please change the left ipg dummy to IMX7D_IPG_ROOT_CLK as well?
Otherwise,
Acked-by: Dong Aisheng
Regards
Dong Aisheng
he gate 0x4130 was actually the DRAM gate, hence disabling that
> clock lead to disabling this gate, and hence a crash before this
> fixes... Maybe that was the reason it landed in clks_init_on...?
>
Probably a history reason or mistake. :-)
Acked-by: Dong Aisheng
Regards
Dong Ais
Hi Lucas,
On Thu, Mar 23, 2017 at 03:35:49PM +0100, Lucas Stach wrote:
> Hi Dong,
>
> Am Freitag, den 24.03.2017, 14:24 +0800 schrieb Dong Aisheng:
> [...]
> > > +static struct platform_driver imx7_pgc_domain_driver = {
> > > + .driver = {
>
On Mon, Mar 27, 2017 at 11:42:51AM -0700, Andrey Smirnov wrote:
> On Thu, Mar 23, 2017 at 11:32 PM, Dong Aisheng wrote:
> > On Tue, Mar 21, 2017 at 07:50:03AM -0700, Andrey Smirnov wrote:
> >> Add DT bindings for power domain driver for GPCv2 IP block found in
> >> i.MX
On Thu, Mar 30, 2017 at 02:58:36PM +0800, Dong Aisheng wrote:
> On Mon, Mar 27, 2017 at 11:42:15AM -0700, Andrey Smirnov wrote:
> > On Thu, Mar 23, 2017 at 11:24 PM, Dong Aisheng wrote:
> > > On Tue, Mar 21, 2017 at 07:50:04AM -0700, Andrey Smirnov wrote:
> > >> Ad
On Mon, Mar 27, 2017 at 11:42:15AM -0700, Andrey Smirnov wrote:
> On Thu, Mar 23, 2017 at 11:24 PM, Dong Aisheng wrote:
> > On Tue, Mar 21, 2017 at 07:50:04AM -0700, Andrey Smirnov wrote:
> >> Add code allowing for control of various power domains managed by GPCv2
> >&
On Tue, Mar 28, 2017 at 02:16:50PM +0300, Leonard Crestez wrote:
> On Fri, 2017-03-24 at 14:43 +0800, Dong Aisheng wrote:
> > Hi Leonard,
> >
> > On Wed, Mar 22, 2017 at 04:27:37PM +0200, Leonard Crestez wrote:
> > >
> > > The imx6sl-evk board has a LAN8
don't know what's wrong. Toolchains difference?
Quite strange...
Regards
Dong Aisheng
> Signed-off-by: Leonard Crestez
> ---
>
> I also tried to do some debugging in the fec driver and it apparently receives
> corrupted packets when this happens. If I hack it to go into pr
On Tue, Mar 21, 2017 at 07:50:03AM -0700, Andrey Smirnov wrote:
> Add DT bindings for power domain driver for GPCv2 IP block found in
> i.MX7 SoCs.
>
> Cc: yurov...@gmail.com
> Cc: Lucas Stach
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: Fabio Estevam
> Cc:
gt;
> Testing of this code was done against a PCIe driver.
>
> Cc: yurov...@gmail.com
> Cc: Lucas Stach
> Cc: Fabio Estevam
> Cc: Dong Aisheng
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov
> ---
> d
On Mon, Mar 20, 2017 at 01:34:19PM -0700, Andrey Smirnov wrote:
> On Mon, Mar 20, 2017 at 12:03 AM, Dong Aisheng wrote:
> > On Thu, Mar 16, 2017 at 06:30:50AM -0700, Andrey Smirnov wrote:
> >> Add code allowing for control of various power domains managed by GPCv2
> >&
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