[PATCH] phy: rockchip-typec: Check for errors from tcphy_phy_init()

account for it. Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 4d2c57f21d76..38831eebc934 10064

[PATCH] ASoC: rockchip: Allocate enough memory so we don't overflow routes

make sure that we don't overrun memory even if we encounter some sort of weird device tree. Fixes: d9f9c167edae ("ASoC: rockchip: Init dapm routes dynamically") Signed-off-by: Douglas Anderson --- sound/soc/rockchip/rk3399_gru_sound.c | 12 +++- 1 file changed, 11 insertions

[PATCH 3/3] mmc: dw_mmc: Add locking to the CTO timer

h of PCIe traffic but it also (on my system) outputs some SELinux log spam. Fixes: 03de19212ea3 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme") Signed-off-by: Douglas Anderson --- drivers/mmc/host/dw_mmc.c | 92 +-- 1

[PATCH 0/3] mmc: dw_mmc: Fix the CTO timer patch

ed for the CTO timer on one of my devices and so I can confirm that part still works. As mentioned in the 3rd patch I also ran the mmc_test kernel module on this and did manage to see the 3rd patch doing something useful. Douglas Anderson (3): mmc: dw_mmc: cancel the CTO timer after a voltage sw

[PATCH 2/3] mmc: dw_mmc: Fix the CTO timeout calculation

19212ea3 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme") Signed-off-by: Douglas Anderson --- drivers/mmc/host/dw_mmc.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index f5b2bb4b4d9

[PATCH 1/3] mmc: dw_mmc: cancel the CTO timer after a voltage switch

switch was done. Let's promote the cancel into the dw_mci_cmd_interrupt() function to fix this. Fixes: 03de19212ea3 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme") Signed-off-by: Douglas Anderson --- drivers/mmc/host/dw_mmc.c | 3 ++- 1 file change

[RFC PATCH 2/2] kbuild: Cache a few more calls to the compiler

These are a few stragglers that I left out of the original patch to cache calls to the C compiler ("kbuild: Add a cache for generated variables") because they bleed out into the main Makefile and thus uglify things a little bit. The idea is the same here, though. Signed-off-by: Dougla

[RFC PATCH 1/2] kbuild: Add a cache for generated variables

already in our cache. The cache is stored in a format that it shouldn't need any invalidation since anything that might change should affect the "key" and any old cached value won't be used. The cache will be cleaned by virtue of the ".o" suffix by a "make cl

[RFC PATCH 0/2] kbuild: Cache exploratory calls to the compiler

ertain architectures you might need some extra escaping here and there. Douglas Anderson (2): kbuild: Add a cache for generated variables kbuild: Cache a few more calls to the compiler Documentation/kbuild/makefiles.txt | 21 ++ Makefile |

[PATCH v3 1/4] phy: rockchip-typec: Set the AUX channel flip state earlier

...so the type C PHY was always in default state. TX_ANA_CTRL_REG_1 is documented to be 0x0 after reset. This was also confirmed by printk. Suggested-by: Shawn Nematbakhsh Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v3: None Changes in v2: None drivers/phy/r

[PATCH v3 0/4] phy: rockchip-typec: Set "flip" properly; some cleanups; fix swing

g his tag. If folks would rather I didn't do that, please yell. Changes in v3: - Voltage swing patch now patch 2. Changes in v2: - Voltage swing patch new for v2. - Removed extra blank line. Douglas Anderson (4): phy: rockchip-typec: Set the AUX channel flip state earlier phy: rockchip-t

[PATCH v3 2/4] phy: rockchip-typec: Don't set the aux voltage swing to 400 mV

say whether this is a better or worse solution. Tightening signals to give cleaner waveforms can often have adverse affects, like increasing EMI or adding noise to other signals. I'd rather not tune things like this without a healthy application of expertise that I don't have.

[PATCH v3 4/4] phy: rockchip-typec: Do the calibration more correctly

tested the pullup and pulldown codes were nearly the same (0x23 and 0x24) and the adjustment codes were 0. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v3: None Changes in v2: - Removed extra blank line. drivers/phy/rockchip/phy-rockchip-ty

[PATCH v3 3/4] phy: rockchip-typec: Avoid magic numbers + add delays in aux calib

ion code. This will hopefully come in a followup change. This also doesn't attempt to document any of the other parts of the PHY--just the aux init which is all I got docs for. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v3: None Changes in v2: None driv

[PATCH v2 3/4] phy: rockchip-typec: Do the calibration more correctly

tested the pullup and pulldown codes were nearly the same (0x23 and 0x24) and the adjustment codes were 0. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v2: - Removed extra blank line drivers/phy/rockchip/phy-rockchip-typec.c | 27 ++- 1 file c

[PATCH v2 1/4] phy: rockchip-typec: Set the AUX channel flip state earlier

...so the type C PHY was always in default state. TX_ANA_CTRL_REG_1 is documented to be 0x0 after reset. This was also confirmed by printk. Suggested-by: Shawn Nematbakhsh Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v2: None drivers/phy/rockchip/phy-rockch

[PATCH v2 0/4] phy: rockchip-typec: Set "flip" properly; some cleanups; fix swing

g his tag. If folks would rather I didn't do that, please yell. Changes in v2: - Removed extra blank line - Voltage swing patch new for v2. Douglas Anderson (4): phy: rockchip-typec: Set the AUX channel flip state earlier phy: rockchip-typec: Avoid magic numbers + add delays in aux calib

[PATCH v2 4/4] phy: rockchip-typec: Don't set the aux voltage swing to 400 mV

say whether this is a better or worse solution. Tightening signals to give cleaner waveforms can often have adverse affects, like increasing EMI or adding noise to other signals. I'd rather not tune things like this without a healthy application of expertise that I don't have.

[PATCH v2 2/4] phy: rockchip-typec: Avoid magic numbers + add delays in aux calib

ion code. This will hopefully come in a followup change. This also doesn't attempt to document any of the other parts of the PHY--just the aux init which is all I got docs for. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- Changes in v2: None drivers/phy/rockchip/p

[RFC PATCH 3/3] usbnet: Fix memory leak when rx_submit() fails

If rx_submit() returns an error code then nobody calls usb_free_urb(). That means it's leaked. NOTE: This problem was found solely by code inspection and not due to any failing test cases. Signed-off-by: Douglas Anderson --- drivers/net/usb/usbnet.c | 9 ++--- 1 file changed, 6 inser

[RFC PATCH 2/3] usbnet: Avoid potential races in usbnet_deferred_kevent()

e is allocating much less than 4K worth of data and probably never fails. Signed-off-by: Douglas Anderson --- drivers/net/usb/usbnet.c | 50 +--- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/drivers/net/usb/usbnet.c b/drivers/net

[RFC PATCH 1/3] usbnet: Get rid of spammy usbnet "kevent X may have been dropped"

gged". ALSO NOTE: If somehow some of the types of work need to be repeated if usbnet_defer_kevent() is called multiple times then that should be quite easy to accomplish without dropping any work on the floor. We can just keep an atomic count for that type of work and add a loop into usb

[PATCH 1/3] phy: rockchip-typec: Set the AUX channel flip state earlier

...so the type C PHY was always in default state. TX_ANA_CTRL_REG_1 is documented to be 0x0 after reset. This was also confirmed by printk. Suggested-by: Shawn Nematbakhsh Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 62 +++

[PATCH 2/3] phy: rockchip-typec: Avoid magic numbers + add delays in aux calib

ion code. This will hopefully come in a followup change. This also doesn't attempt to document any of the other parts of the PHY--just the aux init which is all I got docs for. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 203

[PATCH 0/3] phy: rockchip-typec: Set "flip" at the right time; some cleanups

've added Chris Zhong's Reviewed-by tags since he gave a +1 to nearly identical patches on the Chrome OS gerrit and I didn't think he'd mind me carrying his tag. If folks would rather I didn't do that, please yell. Douglas Anderson (3): phy: rockchip-typec: Set the AUX ch

[PATCH 3/3] phy: rockchip-typec: Do the calibration more correctly

tested the pullup and pulldown codes were nearly the same (0x23 and 0x24) and the adjustment codes were 0. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-)

[PATCH] USB: core: Avoid race of async_completed() w/ usbdev_release()

=ffc0cc042080 mtpd-20553 13759487us : async_getcompleted before spin_lock_irqsave mtpd-20553 13759497us!: usbdev_release after kfree(ps): ps=ffc0cc042080 <...>-2104 0d.h2 13760294us : async_completed before wake_up(): as=ffc0cc638200 To fix this problem we can just

[PATCH] pstore: Fix leaked pstore_record in pstore_get_backend_records()

When the "if (record->size <= 0)" test is true in pstore_get_backend_records() it's pretty clear that nobody holds a reference to the allocated pstore_record, yet we don't free it. Let's free it. Fixes: 2a2b0acf768c ("pstore: Allocate records on heap inste

[RFC PATCH v2] ASoC: Intel: sst: Delete sst_shim_regs64; saved regs are never used

nefit of avoiding an error path in the init code. Note that the saving code that we're removing (and the comments talking about how important it is to do the save) has been around since commit 336cfbb05edf ("ASoC: Intel: mrfld- add ACPI module"). Signed-off-by: Douglas Anderson ---

[RFC PATCH] ASoC: Intel: sst: Delete sst_save_shim64(); saved regs are never used

rs we were storing data in. Note that the saving code (and the comments talking about how important it is to do the save) has been around since commit 336cfbb05edf ("ASoC: Intel: mrfld- add ACPI module"). Signed-off-by: Douglas Anderson --- This problem was found only by code inspection and

[PATCH 1/3] ASoC: rt5514: Mark rt5514_i2c_driver as static

There's no reason for rt5514_i2c_driver to be non-static. Signed-off-by: Douglas Anderson --- sound/soc/codecs/rt5514.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/rt5514.c b/sound/soc/codecs/rt5514.c index b281a46d769d..481e77763fe4 100644 --- a/

[PATCH 3/3] ASoC: rt5514: Unconfuse the rt5514 at probe / resume time

ently believed that this problem should be fixed in the rt5514 driver itself because it seems that the i2c controller in the rt5514 is easily confused. Most i2c devices wouldn't detect a start bit in this case. Signed-off-by: Douglas Anderson --- sound/soc/codecs/rt5

[PATCH 2/3] ASoC: rt5514: Avoid relying on uninitialized "val" value

e value do we're not passing a possibly uninitialized int to printk. Signed-off-by: Douglas Anderson --- sound/soc/codecs/rt5514.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/rt5514.c b/sound/soc/codecs/rt5514.c index 481e77763fe4..969a05620e04 1

[PATCH] mmc: dw_mmc: Don't allow Runtime PM for SDIO cards

mc: add runtime PM callback") Cc: Reported-by: Brian Norris Signed-off-by: Douglas Anderson --- drivers/mmc/host/dw_mmc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 249ded65192e..e45129f48

[RFC PATCH] binder: Don't require the binder lock when killed in binder_thread_read()

able to kill a task quickly when we want to. That means this patch has some merit. 2. Though this patch has merit, it isn't isn't actually all that critical because: 2a) On newer kernels the OOM reaper should keep us from getting deadlocked. 2b) Even on old kernels ther

[PATCH] clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399

as long as ARM Trusted Firmware isn't starting up the M0 at exactly the same time that the kernel is disabling unused clocks. ...but if the race happens then we go boom. Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk-rk3399.c | 8 1 file changed, 4 insertions(+), 4 deleti

[PATCH v2] serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt

resumably this problem is unique to that IP, so I have placed the workaround there to avoid possibly of accidentally triggering bad behavior on other IP. Also note the RX Timeout behaves very differently in the DMA case, for for now the workaround is only applied to the non-DMA case. Signed-off-by

[PATCH] drm/panel: simple: ensure Sharp lq123p1jx31 isn't turned off too soon

550 ms (50 for regulator, 500 to off=>on too quick) As you can see, even giving the regulator 10 ms (the max the panel spec allows) for ramping up we are sure that the regulator was on for 300 ms now. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-simple.c | 1 + 1 file ch

[PATCH] clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER

it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/rockchip/

[PATCH] serial: 8250: Avoid "too much work" from bogus rx timeout interrupt

UARTs and it's plausible some other UART could get into the same state. If these two extra lines of code are too much overhead, we can certainly move it into the DesignWare driver or even only do it for Rockchip UARTs. Signed-off-by: Douglas Anderson --- Testing and development done on a ker

[PATCH] RFC: dm: avoid the mutex lock in dm_bufio_shrink_count()

;t mean that any in-progress dm_bufio transactions are all done. Maybe the above argument would be obvious to someone wise in the ways of dm_bufio but it's a useful argument to make for those like me who are trying to make a small fix without full comprehension of all of dm_bufio's fine

[PATCH] dm: Avoid sleeping while holding the dm_bufio lock

o pass GFP_NOWAIT instead of GFP_NOIO to alloc_buffer() when holding a mutex that can be contended by a concurrent slab shrinker (if count_objects didn't use a trylock, this pattern would trivially deadlock). Suggested-by: David Rientjes Signed-off-by: Douglas Anderson --- Note that t

[tip:timers/core] timers: Fix documentation for schedule_timeout() and similar

Commit-ID: 4b7e9cf9c84b09adc428e0433cd376b91f9c52a7 Gitweb: http://git.kernel.org/tip/4b7e9cf9c84b09adc428e0433cd376b91f9c52a7 Author: Douglas Anderson AuthorDate: Fri, 21 Oct 2016 08:58:51 -0700 Committer: Thomas Gleixner CommitDate: Wed, 26 Oct 2016 13:14:47 +0200 timers: Fix

[tip:timers/core] timers: Fix usleep_range() in the context of wake_up_process()

Commit-ID: 6c5e9059692567740a4ee51530dffe51a4b9584d Gitweb: http://git.kernel.org/tip/6c5e9059692567740a4ee51530dffe51a4b9584d Author: Douglas Anderson AuthorDate: Fri, 21 Oct 2016 08:58:50 -0700 Committer: Thomas Gleixner CommitDate: Wed, 26 Oct 2016 13:14:46 +0200 timers: Fix

[PATCH v2] debug: More properly delay for secondary CPUs

afe enough to use to implement our timeout. We'll delay 1 ms for 1000 times, which should give us a full second of delay (just like the old code wanted) but allow us to notice that we're done every 1 ms. Signed-off-by: Douglas Anderson --- Changes in v2: - Use udelay, not __delay ke

[PATCH v5 1/2] timers: Fix usleep_range() in the context of wake_up_process()

of that but they were aware of many people relying on usleep_range() never returning before the minimum. Reported-by: Tao Huang Signed-off-by: Douglas Anderson --- Changes in v5: - Don't accidentally busy wait after first wakeup (Thomas Gleixner) - Removed Reviewed-by tags Changes in v4:

[PATCH v5 2/2] timers: Fix documentation for schedule_timeout() and similar

alculation cost that isn't needed in all cases. Suggested-by: Daniel Kurtz Signed-off-by: Douglas Anderson --- Changes in v5: None Changes in v4: - Fixed stray double quotes. - Updated wording as per Thomas Gleixner. Changes in v3: - Documentation fix new for v3. k

[PATCH v4 2/2] timers: Fix documentation for schedule_timeout() and similar

alculation cost that isn't needed in all cases. Suggested-by: Daniel Kurtz Signed-off-by: Douglas Anderson --- Changes in v4: - Fixed stray double quotes. - Updated wording as per Thomas Gleixner. Changes in v3: - Documentation fix new for v3. kernel/time/hrtimer.c | 20 ++--

[PATCH v4 1/2] timers: Fix usleep_range() in the context of wake_up_process()

of that but they were aware of many people relying on usleep_range() never returning before the minimum. Reported-by: Tao Huang Signed-off-by: Douglas Anderson Reviewed-by: Andreas Mohr Reviewed-by: Brian Norris Reviewed-by: Guenter Roeck --- Changes in v4: None Changes in v3: - Add Reviewed-by t

[PATCH v3 1/2] timers: Fix usleep_range() in the context of wake_up_process()

of that but they were aware of many people relying on usleep_range() never returning before the minimum. Reported-by: Tao Huang Signed-off-by: Douglas Anderson Reviewed-by: Andreas Mohr Reviewed-by: Brian Norris Reviewed-by: Guenter Roeck --- Changes in v3: - Add Reviewed-by tags - Add notes about

[PATCH v3 2/2] timers: Fix documentation for schedule_timeout() and similar

alculation cost that isn't needed in all cases. Suggested-by: Daniel Kurtz Signed-off-by: Douglas Anderson --- Changes in v3: - Documentation fix new for v3. kernel/time/hrtimer.c | 20 ++-- kernel/time/timer.c | 11 +++ 2 files changed, 21 insertions(+), 10 d

[PATCH] debug: More properly delay for secondary CPUs

ccurate timeout and the only penalty is that we might wait an extra 99 "loops" before we enter the debugger. Signed-off-by: Douglas Anderson --- kernel/debug/debug_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/debug/debug_core.c b/kernel/debu

[PATCH v2] timers: Fix usleep_range() in the context of wake_up_process()

usleep_range(). - There aren't lots of places that use usleep_range(), since many people call either msleep() or udelay(). Reported-by: Tao Huang Signed-off-by: Douglas Anderson --- Changes in v2: - Fixed stupid bug that snuck in before posting - Use ktime_before - Remove delta from th

[PATCH] timers: Fix usleep_range() in the context of wake_up_process()

usleep_range(). - There aren't lotsof places that use usleep_range(), since many people call either msleep() or udelay(). Reported-by: Tao Huang Signed-off-by: Douglas Anderson --- kernel/time/timer.c | 23 --- 1 file changed, 20 insertions(+), 3 deletions(-) diff

[PATCH] arm64: dts: rockchip: Add pinctrl entry for 32k clock on rk3399

On some rk3399 boards GPIO0_A0 is hooked up to a 32 kHz clock. This can be used as the source for various clocks in the system. Add a pinmux so boards can get this pin properly configured. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++ 1 file changed

[PATCH v3 1/2] regulator: pwm: Add support for a fixed delay after duty cycle changes

the device tree property "settle-time-up-us" which allows us to specify a fixed delay after a voltage increase. We don't add an option of a fixed delay on the way down for now because the way down is probably modelled best with a ramp rate, not a fixed delay. Signed-off-by: Matthias Ka

[PATCH v3 2/2] regulator: pwm: Prevent falling too fast

e() call until we've finished delaying. A future patch atop this one might choose to return more immediately and let the voltages fall in the background. That would possibly to allow us to cancel a slow downward decay if there was a request to go back up. Signed-off-by: Douglas Anderson ---

[PATCH] i2c: rk3x: Restore clock settings at resume time

i2c_adapt_div() at resume time and be done with it. NOTE: On rk3399 on ports whose power was lost, I put printouts in at resume time. I saw things like: before: con=0x00010300, div=0x00060006 after: con=0x00010200, div=0x00180025 Signed-off-by: Douglas Anderson --- Tested on chromeos-

[PATCH] arm64: dts: rockchip: Explicitly set pclk_pmu_src on rk3399

cit in our request so we're not relying on the firmware. With the current firmware I tested with this patch has no expected impact but it's probably good to do anyway. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 1 file changed, 2 insertions(+),

[PATCH] clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399

t;clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399"). Before that change we were presumably not actually gating any of these clocks because we were setting the wrong gate. Signed-off-by: Xing Zheng Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk-rk3399.c

[PATCH v2] mmc: sdhci-of-arasan: Don't power PHY w/ slow/no clock

I believe this brings some resolution to the problems reported before. See the commit 6fc09244d74d ("mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes"). Signed-off-by: Douglas Anderson Acked-by: Adrian Hunter Reviewed-by: Shawn Lin --- Tested on chromeos kern

[PATCH] soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts

egister for the "big" cores in the "GPU" slot. It was never initting the GPU counts. Note: this change assumes that ATF will actually set these values at boot, as I'm proposing in <http://crosreview.com/372381>. Signed-off-by: Douglas Anderson --- drivers/soc/roc

[PATCH] mmc: sdhci-of-arasan: Don't power PHY w/ slow/no clock

I believe this brings some resolution to the problems reported before. See the commit 6fc09244d74d ("mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes"). Signed-off-by: Douglas Anderson --- Tested on chromeos kernel-4.4 with backports. dr

[PATCH v2] regulator: pwm: Fix regulator ramp delay for continuous mode

get yourself a reliable and glitch-free regulator. Fixes: 4773be185a0f ("regulator: pwm-regulator: Add support for continuous-voltage") Signed-off-by: Douglas Anderson --- Note: I don't have a board that works against mainline and can use the PWM regulator in continuous mode without B

[PATCH] Input: Add SW_PEN_INSERTED define

neral the pen switch could be used by the software on the device to kick off any number of actions when the pen is inserted or removed. Signed-off-by: Douglas Anderson --- include/uapi/linux/input-event-codes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/input-event-co

[PATCH] regulator: pwm: Fix regulator ramp delay for continuous mode

tens of uS. 1000 is way too much. We'll try to be dynamic and use 10% Signed-off-by: Douglas Anderson --- Note that this patch is atop Boris's recent PWM regulator fixes. If desired it wouldn't be too hard to write it atop the old code, though quite honestly anyone using a PWM reg

[PATCH 1/3] mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes

e 150 MHz series should still work fine even without this one. Signed-off-by: Douglas Anderson --- drivers/mmc/host/sdhci-of-arasan.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasa

[PATCH 3/3] phy: rockchip-emmc: Wait even longer for the DLL to lock

Two times out of 2000 reboots I ran into the error message "rockchip_emmc_phy_power: dllrdy timeout". Presumably there is some corner case where the DLL just takes a little longer to timeout. Let's give it even more time to handle these corner cases. Signed-off-by: D

[PATCH 0/3] mmc: Fixes for 150 MHz Rockchip eMMC series

ous) with Kishon's Ack as appropriate. Douglas Anderson (3): mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes phy: rockchip-emmc: Be tolerant to card clock of 0 in power on phy: rockchip-emmc: Wait even longer for the DLL to lock drivers/mmc/host/sdhci-of-arasan.c

[PATCH 2/3] phy: rockchip-emmc: Be tolerant to card clock of 0 in power on

cycle the PHY. Note: this patch should help with suspend/resume where the system will try to turn the PHY back on when the clock is 0. Signed-off-by: Douglas Anderson --- drivers/phy/phy-rockchip-emmc.c | 59 ++--- 1 file changed, 37 insertions(+), 22 deleti

[PATCH v3 07/15] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs

et the corecfg also include a reference to the syscon. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Heiko Stuebner Reviewed-by: Shawn Lin --- Changes in v3: - Add collected tags Changes in v2: -

[PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions

From: Brian Norris Some of the spacing was wrong (spaces instead of tabs), and due to longer entries added later, the columns weren't aligned. Let's get everything consistent. Signed-off-by: Brian Norris Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Reviewed

[PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock

xport the SDHCI card clock using a standard device tree mechanism so that the PHY can get access to it and query the card clock frequency. Signed-off-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - Adjust commit me

[PATCH v3 01/15] phy: rockchip-emmc: give DLL some extra time to be ready

Norris Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Tested-by: Heiko Stuebner --- Changes in v3: - Add Brian's PHY patches into my series Changes in v2: None drivers/phy/phy-rockchip-emmc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/driver

[PATCH v3 02/15] phy: rockchip-emmc: configure frequency range and drive impedance

From: Shawn Lin Signal integrity analysis has suggested we set these values. Do this in power_on(), so that they get reconfigured after suspend/resume. Signed-off-by: Shawn Lin Signed-off-by: Brian Norris Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Tested-by: Heiko

[PATCH v3 13/15] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off()

There's no reason to store the return value of rockchip_emmc_phy_power() in a variable nor to check it. Just return it. Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Reviewed-by: Shawn Lin Tested-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes

[PATCH v3 09/15] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399

On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson Tested-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399

[PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock

s series, since performance is still good but signal integrity problems are less prevelant at 150 MHz. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I --- Changes in v3: - Use phy_init / phy_exit (Heiko)

[PATCH v3 08/15] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399

r SoCs. Note that a specific compatible string for rk3399 is already in use and so we add that to the table to match rk3399. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Reviewed-by: Heiko Stuebner Reviewed-by: Shawn Lin Tested-

[PATCH v3 12/15] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

the idea is the same. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - List out clocks and cloc

[PATCH v3 15/15] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399

Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson Tested-by: Heiko Stuebner --- Changes in v3: - Add collected

[PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399

wn) Brian Norris (2): phy: rockchip-emmc: configure default output tap delay phy: rockchip-emmc: reindent the register definitions Douglas Anderson (11): phy: rockchip-emmc: Increase lock time allowance mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Documentation: m

[PATCH v3 11/15] mmc: sdhci-of-arasan: Add ability to export card clock

s the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changes in v3: - Add dependency on COMMON_CLK (actually in v2.1) (Guenter Roeck) - Add collected tags Changes in v2: None drivers/mmc/host/Kconfig

[PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes

nd will cause problems if picked without that change. Signed-off-by: Douglas Anderson Reviewed-by: Shawn Lin Tested-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: None drivers/mmc/host/sdhci-of-arasan.c | 23 --- 1 file changed, 8 insertions(+), 1

[PATCH v3 05/15] phy: rockchip-emmc: Increase lock time allowance

ck was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abraham I Rev

[PATCH v3 03/15] phy: rockchip-emmc: configure default output tap delay

's bump up to 4 (approx 90 degree phase?). If we need to configure this any further (e.g., based on board or speed factors), we may need to consider a device tree representation. Suggested-by: Shawn Lin Signed-off-by: Brian Norris Signed-off-by: Douglas Anderson Acked-by: Kishon Vijay Abrah

[PATCH v2.1 07/11] mmc: sdhci-of-arasan: Add ability to export card clock

s the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson --- Note: just sending the one quick fix as v2.1. If further spins are needed I'll send out a full v3. Changes in v2.1: - Add dependency on COMMON_CLK (Guenter Roeck) Changes in v2: None drivers/mmc/ho

[PATCH] arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399

ctually route from rk3288 back to rk3288. Presumably on rk3399 this is simply not needed since the pins don't appear to exist there. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dt

[PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance

ck was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson --- Changes in v2: - Indicate

[PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs

et the corecfg also include a reference to the syscon. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Rob Herring --- Changes in v2: - Clean up description of rk3399 PHY (Shawn) - Add Rob Herring's Ack. .../devicetree/

[PATCH v2 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399

On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/

[PATCH v2 10/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock

s series, since performance is still good but signal integrity problems are less prevelant at 150 MHz. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson --- Changes in v2: - Warn if we're more than 15 MHz from ideal rate (Shawn) - Mo

[PATCH v2 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock

xport the SDHCI card clock using a standard device tree mechanism so that the PHY can get access to it and query the card clock frequency. Signed-off-by: Douglas Anderson Acked-by: Rob Herring --- Changes in v2: - Adjust commit message wording (Rob) - Add Rob Herring's Ack. Documentation/

[PATCH v2 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399

Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399

[PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

the idea is the same. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson --- Changes in v2: - List out clocks and clock names (Rob) Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 + 1 file changed, 9 insertions(

[PATCH v2 09/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off()

There's no reason to store the return value of rockchip_emmc_phy_power() in a variable nor to check it. Just return it. Signed-off-by: Douglas Anderson --- Changes in v2: - Move code cleanup before set phyctrl_frqsel based on card clock (Shawn) drivers/phy/phy-rockchip-emmc.c

[PATCH v2 07/11] mmc: sdhci-of-arasan: Add ability to export card clock

s the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson --- Changes in v2: None drivers/mmc/host/sdhci-of-arasan.c | 125 - 1 file changed, 122 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc

[PATCH v2 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399

r SoCs. Note that a specific compatible string for rk3399 is already in use and so we add that to the table to match rk3399. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson --- Changes in v2: - Reorder includes (Shawn) drivers

[PATCH v2 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes

nd will cause problems if picked without that change. Signed-off-by: Douglas Anderson --- Changes in v2: None drivers/mmc/host/sdhci-of-arasan.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/

[PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399

Shawn) - Fix typo USB => SDHCI (Shawn) Douglas Anderson (11): phy: rockchip-emmc: Increase lock time allowance mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs mmc: sdhci-of-arasan: Properly

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