Hi Pramod,
On Wed, May 8, 2019 at 10:56 AM Pramod Kumar wrote:
> + {
> + ethernet@e {
You have passed @e without a corresponfing reg entry.
This causes dtc build warnings with W=1.
Please make sure you don't introduce new W=1 warnings.
Hi Andy,
On Sun, May 5, 2019 at 5:15 AM Andy Duan wrote:
> Nack the patch !
>
> Firstly, i.MX6SX has ENET AHB bus clock for MAC, and currently it is set
> 200Mhz like clock tree:
> IMX6SX_CLK_ENET_PODF 200Mhz -> IMX6SX_CLK_ENET_SEL ->
> IMX6SX_CLK_ENET_AHB
>
> IMX6SX_CLK_ENET the
On Tue, May 7, 2019 at 4:47 AM Guido Günther wrote:
>
> Add support for the MIXEL DPHY IP as found on NXP's i.MX8MQ SoCs.
>
> Signed-off-by: Guido Günther
> Reviewed-by: Sam Ravnborg
> Reviewed-by: Rob Herring
Reviewed-by: Fabio Estevam
Hi Angus,
On Mon, May 6, 2019 at 11:10 AM Angus Ainslie (Purism) wrote:
>
> If the fault status register doesn't get cleared then
> the ptn5110 interrupt gets stuck on. As the fault register gets
> set everytime the ptn5110 powers on the interrupt is always stuck.
>
> Signed-off-by: Angus
< IMX6SX_CLK_ENET_AHB>,
> +< IMX6SX_CLK_ENET>,
Yes, there is really no IMX6SX_CLK_ENET_AHB as per the Refernce Manual
and it is the same we do on imx6qdl.dtsi:
Reviewed-by: Fabio Estevam
x6sx.c, and modify fec device’s clocks in
> the dts file, point ‘ahb’ from IMX6SX_CLK_ENET_AHB to
> IMX6SX_CLK_ENET
>
> Signed-off-by: Kay-Liu
This matches the mx6sx reference manual:
Reviewed-by: Fabio Estevam
[Adding Rui]
On Tue, Apr 30, 2019 at 4:47 AM Sébastien Szymanski
wrote:
>
> Add csi node for i.MX6UL SoC.
>
> Signed-off-by: Sébastien Szymanski
> ---
> arch/arm/boot/dts/imx6ul.dtsi | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi
On Thu, May 2, 2019 at 10:07 AM Guido Günther wrote:
>
> It's defined in imx8mq-clock.h but wasn't assigned yet. It's used as
> clk_tx_esc in the nwl dsi host controller (i.MX8MQ RM, Rev. 0, 01/2018
> Sect. 13.5.3.7.4).
>
> Signed-off-by: Guido Günther
Reviewed-by: Fabio Estevam
vicetree/bindings/media/imx7-csi.txt:
Reviewed-by: Fabio Estevam
Hi Guido,
On Tue, Apr 30, 2019 at 1:18 PM Guido Günther wrote:
>
> i.MX8 needs soc_device_register, otherwise the build fails like:
>
> aarch64-linux-gnu-ld: drivers/soc/imx/soc-imx8.o: in function
> `imx8_soc_init':
> soc-imx8.c:(.init.text+0x130): undefined reference to
On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue
wrote:
>
>
> On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> > Implement ARM errata 814220 for Cortex A7.
> >
> > This patch has been wroten by Jason Liu years ago but never send upstream.
> > I have tried to contact the author on multiple email
On Tue, Apr 23, 2019 at 10:51 AM Robin Gong wrote:
>
> ECSPI issue fixed from i.mx6ul at hardware level, no need
> ERR009165 anymore on those chips such as i.mx8mq. Add i.mx6sx
> from where i.mx6ul source.
>
> Signed-off-by: Robin Gong
> ---
> drivers/dma/imx-sdma.c | 43
On Tue, Apr 23, 2019 at 10:50 AM Robin Gong wrote:
>
> This reverts commit dd4b487b32a3571fdcc66062e661e3a3e360e35b.
Same here.
Hi Robin,
On Tue, Apr 23, 2019 at 10:50 AM Robin Gong wrote:
>
> This reverts commit df07101e1c4a29e820df02f9989a066988b160e6.
You need to provide a detailed explanation in the commit log as to why
the revert is needed.
On Tue, Apr 23, 2019 at 7:48 AM Clark Wang wrote:
>
> Add "fsl,spi-num-chipselects" check to support multi SS function in PIO
> mode.
This custom property does not seem to be needed as the number of chip
selects can be parsed from the devicetree file directly.
We got rid of
Hi Clark,
On Tue, Apr 23, 2019 at 7:47 AM Clark Wang wrote:
>
> Add a NULL check for device node and lpspi_platform_info when lpspi
> device probe.
Please explain why you are adding such check.
On Mon, Apr 22, 2019 at 7:45 PM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the imx-mxs tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> arch/arm/boot/dts/imx7d-zii-rpu2.dts:46.12-50.4: Warning
> (io_channels_property): /iio-hwmon: Missing property
Hi Andrey,
On Wed, Apr 17, 2019 at 5:46 AM Andrey Smirnov wrote:
>
> Add bindings for Microchip UCS1002 Programmable USB Port Power
> Controller with Charger Emulation.
>
> Signed-off-by: Andrey Smirnov
> Cc: Chris Health
It seems there is a typo in Chris' last name.
On Sat, Apr 13, 2019 at 4:30 AM Nicholas Mc Guire wrote:
>
> The header clearly identifies this code as GPL V2 or later - so pop
> in the SPDX license identifier.
>
> Signed-off-by: Nicholas Mc Guire
> ---
> arch/arm/mach-imx/mach-mx27ads.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Sat, Apr 13, 2019 at 10:20 AM Markus Kueffner
wrote:
>
> Add Pincfgs to enable the i.MX6's OTG feature for UDOO
>
> Signed-off-by: Markus Kueffner
Reviewed-by: Fabio Estevam
Hi Kay,
On Wed, Apr 10, 2019 at 5:43 AM root wrote:
>
> From: Kay-Liu
>
> The imx6-solox's enet clk config would cause CPU hang in a special
> environment.The BUG was accepted by yoctoproject, they will process
> platform related code,only submit dts part here.
>
On Wed, Apr 10, 2019 at 8:55 AM Fabio Estevam wrote:
> Please check if this patch fixes the problem on your case:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20190410=728e096dd70889c2e80dd4153feee91afb1daf72
Also, just confirmed that this commit r
Hi Robert,
On Wed, Apr 10, 2019 at 7:57 AM Robert Foss wrote:
> # dmesg
> imx-drm display-subsystem: failed to bind disp0 (ops imx_pd_ops): -517
> imx-drm display-subsystem: master bind failed: -517
>
> This dmesg log is failing to bind disp0 at another point than what I
> was seeing before,
On Tue, Apr 9, 2019 at 10:47 PM Anson Huang wrote:
> #include "imx7ulp.dtsi"
> +#include
This inclusion is not needed here as PWM_POLARITY_INVERTED is not used
in this dts.
Hi Robert,
[Adding Gary]
On Mon, Apr 8, 2019 at 2:54 PM Robert Foss wrote:
>
> If a LVDS device is not connected, having the LVDS channels
> enabled will prevent imx-ldb from probing correctly even
> if other CRTCs are connected.
>
> Signed-off-by: Robert Foss
> ---
>
On Sun, Mar 31, 2019 at 11:25 PM Andrey Smirnov
wrote:
>
> Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
>
> Signed-off-by: Andrey Smirnov
> Reviewed-by: Lucas Stach
Reviewed-by: Fabio Estevam
; time. Account for that quirk by combining PCIE power domains into a
> single 'pgc_pcie' power domain.
>
> Signed-off-by: Andrey Smirnov
> Reviewed-by: Lucas Stach
Reviewed-by: Fabio Estevam
On Sun, Mar 31, 2019 at 11:25 PM Andrey Smirnov
wrote:
>
> Add nodes for two PCIe controllers found on i.MX8MQ.
>
> Signed-off-by: Andrey Smirnov
> Reviewed-by: Lucas Stach
Reviewed-by: Fabio Estevam
On Sun, Mar 31, 2019 at 11:25 PM Andrey Smirnov
wrote:
>
> Add a node for reset controller IP block found on i.MX8MQ.
>
> Signed-off-by: Andrey Smirnov
> Reviewed-by: Lucas Stach
> Cc: Shawn Guo
> Cc: Fabio Estevam
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Leo
On Sun, Mar 31, 2019 at 11:24 PM Andrey Smirnov
wrote:
>
> Mark iomuxc_gpr as compatible with "fsl,imx6q-iomuxc-gpr" in order for
> to allow i.MX6 PCIe driver to use it.
>
> Signed-off-by: Andrey Smirnov
> Acked-by: Lucas Stach
Reviewed-by: Fabio Estevam
s = <1>;
> + #size-cells = <1>;
> + };
> +};
> +
> + {
> + clock-frequency = <10>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c1>;
> + status = "okay";
> +
> + pmic: pfuze3000@8 {
pmic@8
Reviewed-by: Fabio Estevam
Hi Steve,
On Mon, Apr 1, 2019 at 5:38 AM Steve Twiss
wrote:
> This patch looks surprisingly similar to this one ;)
> https://lore.kernel.org/patchwork/patch/1052588/
>
> Link:
> https://lkml.kernel.org/r/1397569821-5530-4-git-send-email-thomas.petazz...@free-electrons.com
> Tested-by: Steve
Hi Angus,
On Thu, Mar 28, 2019 at 10:39 AM Angus Ainslie (Purism) wrote:
>
> On imx8mq B0 chip, AHB/SDMA clock ratio 2:1 can't be supported,
> since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
> to 500Mhz, so use 1:1 instead.
>
> To limit this change to the imx8mq for now
Hi Andrey,
On Tue, Mar 26, 2019 at 11:52 PM Andrey Smirnov
wrote:
> I think it is worth fixing in DT, regardless if we do anything about
> SDMA driver or not. I'll add fixes for 6SX and 7D in v2.
What about imx25, imx31, imx50, imx51, imx53, imx6sl, imx6ul, imx6sll,
imx6ull, etc?
If we plan
Hi Andrey,
On Mon, Mar 25, 2019 at 2:01 AM Andrey Smirnov wrote:
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 9f9aa6e7ed0e..354feba077b2 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -949,7 +949,7 @@
>
Hi Abel,
On Fri, Mar 22, 2019 at 12:37 PM Abel Vesa wrote:
>
> This work is part of the effort of switching the entire imx clock drivers
> towards clk_hw based API. In order to do that, we have to keep the old
Maybe I missed some earlier discussions on this topic, but let me ask
a fundamental
On Thu, Mar 21, 2019 at 11:15 PM Shawn Guo wrote:
> > Unfortunately, just by looking at the dts files we do not know if a
> > board uses an AR803x PHY or not, so I am afraid we can not do an
> > automatic conversion.
>
> At least for those we already know?
Yes, I can help preparing a patch that
Hi Shawn,
On Thu, Mar 21, 2019 at 10:12 PM Shawn Guo wrote:
> > So yes, we currently have lots of broken dtb's in mainline and I am
> > wondering what is the proper fix here.
>
> So can we have a single patch fixing all broken i.MX DTBs?
Unfortunately, just by looking at the dts files we do
Hi Abel,
On Thu, Mar 21, 2019 at 5:42 AM Abel Vesa wrote:
> > It seems we have other boards that need to be fixed and we can not
> > have an old dtb with functional Ethernet with a new kernel.
> >
> > Does anyone know if this issue is AR8031 specific?
>
> I can confirm the same fix is works on
Hi Steve,
[Adding Andrew]
On Wed, Mar 20, 2019 at 1:03 PM Steve Twiss
wrote:
>
> Hi Fabio,
>
> On 20 March 2019 12:17, Fabio Estevam wrote:
> > Subject: Re: [PATCH] ARM: dts: imx6qdl-sabresd: change phy-mode to use
> > rgmii-id
> >
> > Hi Steve,
> >
Hi Steve,
On Wed, Mar 20, 2019 at 9:06 AM Steve Twiss
wrote:
>
> The PHY used on the Freescale i.MX6Q/DL SABRE boards is qualified as
> 'rgmii' instead of 'rgmii-id'. Meaning the RX and TX delays that were
This patch declares it as 'rgmii-id', which contradicts the commit log.
> previously
On Tue, Mar 19, 2019 at 12:10 PM Angus Ainslie (Purism) wrote:
>
> Add the imx8mq TMU (Thermal management unit) nodes for CPU,
> GPU, and VPU.
>
> Changes since v2:
>
> Updated alert and critical temps for commercial parts.
> Fixed node names.
>
> Changes since v1:
>
> Removed references to multi
Hi Peng,
On Tue, Mar 19, 2019 at 9:31 AM Peng Fan wrote:
> > Looks good, please put it in the patch system, thanks. Details in my
> > signature.
>
> Would you apply this patch? I do not find this patch in your tree.
Have you put it in Russell's patch system
On Mon, Mar 18, 2019 at 1:05 PM Angus Ainslie (Purism) wrote:
>
> Add the imx8mq TMU (Thermal mannagement unit) nodes for CPU,
> GPU, and VPU.
>
> This patch requires that the multi sensor patch is already applied
>
>
Hi Lucas,
On Wed, Mar 13, 2019 at 2:22 PM Lucas Stach wrote:
> Unfortunately this change causes a regression on systems with MC13xxx
> regulators. The desc.name field is filled with an uppercase name of the
> regulator, while the existing DTs (as far as I know) all use lowercase
> node names,
On Wed, Mar 13, 2019 at 4:02 AM Andrey Smirnov wrote:
>
> Add Device Tree for VF610 based Zodiac Seat Power Box.
>
> Signed-off-by: Andrey Smirnov
Reviewed-by: Fabio Estevam
On Sat, Mar 2, 2019 at 7:33 PM Pierre-Jean Texier wrote:
>
> PMIC swbst regulator is used for the MikroBUS socket (pin +5V).
>
> We have to set the regulator to "boot-on" and "always-on"
> to output a voltage of 5V on this socket.
>
> Signed-off-by: Pierre-Jean Texier
Reviewed-by: Fabio Estevam
Hi Angus,
On Tue, Mar 12, 2019 at 5:19 PM Angus Ainslie wrote:
> I tried applying those to linux-next. They don't apply very cleanly
> there so I gave up.
You need to apply this commit first:
Hi Andrey,
On Tue, Mar 12, 2019 at 3:47 PM Andrey Smirnov wrote:
> OK, will do. Although, "flash" seem to be more popular in ZII files
> (used by RDU1 and RDU2), so I am inclined to use that instead, if you
> don't mind.
That's fine.
> I am sure you've noticed that already, but just in case
Hi Andrey,
On Mon, Mar 11, 2019 at 3:49 PM Andrey Smirnov wrote:
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4f5aeaf3298..035ad9fc49f3 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -607,7 +607,8 @@ dtb-$(CONFIG_SOC_VF610)
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) wrote:
>
> Signed-off-by: Angus Ainslie (Purism)
No commit log?
Not sure if we want to add a new defconfig for a single board.
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) wrote:
>
> Compile the Librem5 devkit device tree
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
>
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) wrote:
> +/ {
> + model = "Purism Librem 5 devkit 1.0";
> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
This board is not manufactured by FSL/NXP, so it should be
"purism,librem5-devkit", "fsl,imx8mq" instead.
You should
On Mon, Mar 11, 2019 at 1:02 PM Eric Nelson wrote:
>
> Since we removed the PLL4_AUDIO_DIV clock, we need to replace
> any references to it in the device tree with PLL4_POST_DIV to
> keep the proper parents.
>
> Signed-off-by: Eric Nelson
Reviewed-by: Fabio Estevam
ost_div clock.
>
> Signed-off-by: Eric Nelson
Reviewed-by: Fabio Estevam
Hi Daniel,
On Fri, Mar 8, 2019 at 1:09 PM Daniel Baluta wrote:
>
> From: Shengjiu Wang
>
> Write initial words into SAI FIFO to reduce the underrun
> error.
Please provide a better explanation.
Why does performing these writes help?
Also, the commit message says "reduce", so it seems this is
SAI2 pinctrl configuration
> * clock hierarchy
> * wm8960 codec
>
> Then uses simple-card machine driver to connect them
> into a sound card.
>
> Signed-off-by: Daniel Baluta
Reviewed-by: Fabio Estevam
On Fri, Mar 8, 2019 at 9:02 AM Daniel Baluta wrote:
>
> SAI2 is part of AIPS-3 memory region.
>
> Signed-off-by: Daniel Baluta
Reviewed-by: Fabio Estevam
On Fri, Mar 8, 2019 at 9:02 AM Daniel Baluta wrote:
>
> Add imx8mq sdma support.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Daniel Baluta
Reviewed-by: Fabio Estevam
Hi Daniel,
On Fri, Mar 1, 2019 at 12:53 PM Daniel Baluta wrote:
> They are used by simple-card.c machine driver.
>
> asoc_simple_card_parse_clk
> -> /* Parse dai->sysclk come from "clocks = <>" */
> clk = devm_get_clk_from_child(dev, node, NULL);
The simple-card looks for the "clocks"
this implements it much like the others.
>
> Signed-off-by: Adam Ford
Reviewed-by: Fabio Estevam
On Thu, Feb 28, 2019 at 10:24 PM Anson Huang wrote:
>
> Freescale MMDC (Multi Mode DDR Controller) driver is supported
> since i.MX6Q, but not yet documented, this patch adds binding
> doc for MMDC module driver.
>
> Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
On Wed, Feb 27, 2019 at 3:38 AM Daniel Baluta wrote:
> +
> + wm8524: audio-codec-0 {
This -0 is not needed as we have a single codec on this board.
> + #sound-dai-cells = <0>;
> + compatible = "wlf,wm8524";
> + clocks = < IMX8MQ_CLK_SAI2_ROOT>;
>
On Wed, Feb 27, 2019 at 3:38 AM Daniel Baluta wrote:
> + sai2: sai@308b {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mq-sai",
> +"fsl,imx6sx-sai";
> +
On Wed, Feb 27, 2019 at 3:38 AM Daniel Baluta wrote:
>
> SDMA1 is part of AIPS-3 region and SDMA2 is part
> of AIPS-1 region.
>
> Signed-off-by: Anson Huang
> [initial submit in i.MX internal tree]
> Signed-off-by: Daniel Baluta
> [adaptation for linux-next]
Reviewed-by: Fabio Estevam
On Wed, Feb 27, 2019 at 11:48 PM Anson Huang wrote:
>
> i.MX7ULP has a MMDC module to control DDR, it reuses
> i.MX6Q's MMDC module, add support for it.
>
> Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
ng
> ---
> Changes since V2:
> - remove "mmdc" label for single MMDC node.
Reviewed-by: Fabio Estevam
Hi Anson,
On Wed, Feb 27, 2019 at 11:48 PM Anson Huang wrote:
> +Required properties :
> +- compatible : should be one of following:
> + for i.MX6Q/i.MX6DL:
> + - "fsl,imx6q-mmdc";
You missed the entry for imx6qp.
Hi Anson,
On Wed, Feb 27, 2019 at 10:54 PM Anson Huang wrote:
> If so, should I change other i.MX6 SoCs with single MMDC node as well?
> Remove them as well?
Only imx6qp needs the mmdc label.
I can send a patch removing it from the other i.MX SoCs, so don't need
to worry about it in your
Hi Anson,
On Wed, Feb 27, 2019 at 10:23 PM Anson Huang wrote:
>
> i.MX7ULP has a MMDC module to control DDR, it reuses
> i.MX6Q's MMDC module, add support for it.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V1:
> - use "memory-controller" as MMDC node name to make it more
On Wed, Feb 27, 2019 at 7:08 AM Anson Huang wrote:
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> index fca6e50..fca4a01 100644
> --- a/arch/arm/boot/dts/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -286,6 +286,12 @@
> status
Hi Anson,
On Wed, Feb 27, 2019 at 7:08 AM Anson Huang wrote:
> +Example :
> + mmdc0: mmdc@21b { /* MMDC0 */
Node names should be generic, so:
memory-controller@21b
On Tue, Feb 26, 2019 at 10:29 PM Anson Huang wrote:
>
> i.MX8MQ has clock gate for each GPIO bank, add clock info
> to GPIO node for clock management.
>
> Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
On Tue, Feb 26, 2019 at 10:28 PM Anson Huang wrote:
>
> i.MX8MQ has clock gate for each GPIO bank, add them
> into clock tree for GPIO driver to manage.
>
> Signed-off-by: Anson Huang
Reviewed-by: Fabio Estevam
On Tue, Feb 26, 2019 at 10:37 AM Fabio Estevam wrote:
>
> On Tue, Feb 26, 2019 at 7:53 AM Abel Vesa wrote:
>
> > + magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
> > + if (magic == IMX8MQ_SW_MAGIC_B1)
> > + rev = REV_B1;
>
> Don
On Tue, Feb 26, 2019 at 7:53 AM Abel Vesa wrote:
> + magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
> + if (magic == IMX8MQ_SW_MAGIC_B1)
> + rev = REV_B1;
Don't you mean rev == REV_B1; ?
On Tue, Feb 26, 2019 at 10:05 AM Daniel Baluta wrote:
> I get your point here. But for the moment it is identical with
> "fsl,imx7d-sdma" so there is no need to add it now!
>
> See the discussion here, and comment from Lucas:
>
> https://lkml.org/lkml/2019/1/28/194
Lucas' suggestion was not
On Tue, Feb 26, 2019 at 4:08 AM Daniel Baluta wrote:
>
> SAI2 is part of AIPS-3 memory region and it's the DAI through
> which the wm8524 codec gets its data.
Please do not mention wm8524 in a SoC dtsi file commit message.
It is the imx8mq-evk board that uses this codec and this information
is
Hi Daniel,
On Tue, Feb 26, 2019 at 4:08 AM Daniel Baluta wrote:
>
> On i.MX8MQ we can start the party using the wm8524 codec
> which gets it's data through the SAI2 interface.
>
> In order to make it work this patch series enables the SDMA nodes,
> sets the correct pinctrl configuration and uses
On Tue, Feb 12, 2019 at 10:07 PM Trent Piepho wrote:
> Tried SDMA firmware 4.2. Still broken. No apparent change.
>
> Get 4 cycle pause after each byte.
>
> And crash while/after using DMA. Clearly some sort of memory
> corruption going on. Fortunately, it's very reliable that using DMA
>
On Mon, Feb 11, 2019 at 8:22 PM Trent Piepho wrote:
> > Just trying to understand if the SDMA firmware plays a role on this
> > behavior or not.
>
> The ROM firmware only.
Does the problem also happen if the external SDMA firmware is used?
Just trying to narrow it down.
Hi Abel,
On Tue, Feb 12, 2019 at 10:13 AM Abel Vesa wrote:
>
> From: Anson Huang
>
> Add i.MX8MQ cpu OPP table info for cpu-freq driver.
Has the imx8m cpufreq driver already been submitted?
Hi Trent,
On Mon, Feb 11, 2019 at 6:44 PM Trent Piepho wrote:
> I've had more time to test.
>
> Without DMA, I can reload my FPGA hundreds of times and get days of
> uptime using linux-next.
>
> With DMA, loading is unreliable. The higher the SPI speed, the less
> reliable it is.
On Sat, Feb 9, 2019 at 2:25 PM Jonathan Neuschäfer
wrote:
>
> On Thu, Feb 07, 2019 at 10:50:28PM -0200, Fabio Estevam wrote:
> > On Thu, Feb 7, 2019 at 8:52 PM Jonathan Neuschäfer
> [...]
> > > I tried to compare the CCM's clocks between i.MX50 and i.MX53, but
> &g
chäfer
> Cc: Dong Aisheng
> Cc: Shawn Guo
Reviewed-by: Fabio Estevam
> +Required properties:
> +- compatible: "fsl,imx50-iomuxc"
> +- fsl,pins: two integers array, represents a group of pins mux and config
> + setting. The format is fsl,pins = , PIN_FUNC_ID is a
&
Hi Jonathan,
On Thu, Feb 7, 2019 at 8:52 PM Jonathan Neuschäfer
wrote:
>
> Hi,
>
> I'm currently porting mainline Linux to an i.MX507-based board
> (preliminary DT here[1]). Recently I've enabled esdhc1 in the
> devicetree.
>
> However, as soon as the mmc driver (sdhci-esdhc-imx.c) disables
roblems")
>
> Do you want me to add this and CC stable?
That would be nice. You can also add:
Reviewed-by: Fabio Estevam
Thanks
On Tue, Feb 5, 2019 at 11:00 AM Miquel Raynal wrote:
>
> Hi Martin,
>
> Martin Kepplinger wrote on Tue, 29 Jan 2019
> 16:37:00 +0100:
>
> > From: Martin Kepplinger
> >
> > Disable BCH soft reset according to MX23 erratum #2847 ("BCH soft
> > reset may cause bus master lock up") for MX28 too. It
On Thu, Jan 31, 2019 at 1:03 PM Abel Vesa wrote:
>
> Add RTC support for i.MX8MQ.
>
> Signed-off-by: Abel Vesa
Reviewed-by: Fabio Estevam
Hi Andrey
On Thu, Jan 31, 2019 at 7:11 PM Andrey Smirnov wrote:
>
> Now that the GPCv2 driver supports i.MX8MQ, make GPC default interrupt
> parent.
>
> Signed-off-by: Andrey Smirnov
Lucas has already submitted this same change and another one that
selects the GPC driver as part of a series.
compatible = "atmel,24c64";
> + pagesize = <32>;
> + read-only; /* Manufacturing EEPROM programmed at factory
> */
> + reg = <0x51>;
> + };
> +
> + at24@52 {
eeprom@52
With these changes you can add:
Reviewed-by: Fabio Estevam
Hi Vinod,
On Sun, Jan 20, 2019 at 8:54 AM Vinod Koul wrote:
> This looks reasonable to me and I think should go to stable as well.
> Fabio can we get some testing done on this patch
I currently don't have access to a mx25pdk board. Will probably get
access to it next week.
Patch looks good
Hi Adam,
On Tue, Jan 22, 2019 at 12:07 PM Adam Ford wrote:
> + reg_audio: regulator-audio {
> + pinctrl-names = "default";
> + pinctrl-0 = <_reg_audio>;
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_aud";
> +
On Mon, Jan 21, 2019 at 5:43 AM Arthur Demchenkov wrote:
>
> Wrong polarity of card detect GPIO pin leads to the system not
> booting from external mmc, if the back cover of N900 is closed.
> When the cover is open the system boots fine.
>
> This wasn't noticed before, because of a bug, which was
RS232, I2C, SPI, CAN headers
> * Further I/O options via A/V and Expansion headers
>
> Signed-off-by: Martyn Welch
Reviewed-by: Fabio Estevam
Hi Steve,
On Sat, Jan 19, 2019 at 7:19 PM Steve Longerbeam wrote:
>
> Add video capture support from the OV5642 to IPU CSI0 on
> the i.MX53 SMD.
>
> Signed-off-by: Steve Longerbeam
Looks good, thanks:
Reviewed-by: Fabio Estevam
Only one minor nit below that perhaps Shawn cou
Looks good, thanks:
Reviewed-by: Fabio Estevam
Hi Martyn,
On Fri, Jan 18, 2019 at 5:49 PM Martyn Welch wrote:
> + /*
> +* Set the minimum memory size here and
> +* let the bootloader set the real size.
> +*/
> + memory {
Need to pass device_type = "memory";
> + reg = <0x8000
Hi Michael,
On Fri, Jan 18, 2019 at 10:41 AM Michael Ellerman wrote:
> Yeah "one line summary" is referring to the subject of the commit.
>
> So it doesn't explicitly say not to split it across lines, it probably
> should.
>
> eg: ?
>
> diff --git a/Documentation/process/submitting-patches.rst
On Fri, Jan 18, 2019 at 7:07 AM Stefan Agner wrote:
>
> Probe deferral is to be expected during normal operation, so avoid
> printing an error when it is encountered.
>
> Signed-off-by: Stefan Agner
> Reviewed-by: Daniel Baluta
> Acked-by: Nicolin Chen
Reviewed-by: Fabio Estevam
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