Hi,
On Sat, Mar 11, 2017 at 03:07:55PM +0100, Quentin Schulz wrote:
> Hi Icenowy,
>
> On 10/03/2017 20:25, Icenowy Zheng wrote:
> >
> >
> > 10.03.2017, 18:56, "Quentin Schulz" <quentin.sch...@free-electrons.com>:
> >> This patch adds docum
> >
> > Maxime Ripard wants to base H3/H5/A64 thermal driver on this patchset, and
> > for H5/A64 there's 2/3 thermal sensors.
>
> Yes, that'll require a specific DT node for those thermal sensors. Then
> since we would update the possible compatibles in the docu
On Thu, Mar 02, 2017 at 11:13:53PM +0800, Icenowy Zheng wrote:
>
>
> 02.03.2017, 22:09, "Maxime Ripard" <maxime.rip...@free-electrons.com>:
> > On Wed, Mar 01, 2017 at 08:22:13PM +0800, Icenowy Zheng wrote:
> >> > I'm a bit worried by that to be honest
; >
> > What do you mean by dedicated clocks?
>
> The legacy form of clocks.
Which itself creates another form of issues. What happens if we get
something wrong on those clocks (as it is likely to happen)?
We potentially can't fix it at all, that's what happens.
And that's l
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rst);
> > + }
> > +
> I think you do not need the compatible.
> You can just detect whether the reset is present.
That would weaken the error check. If we're running on the A31 and are
missing our reset property, it would go unnoticed.
Maxime
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Embedded Linux and Kernel engineering
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rst);
> > + }
> > +
> I think you do not need the compatible.
> You can just detect whether the reset is present.
That would weaken the error check. If we're running on the A31 and are
missing our reset property, it would go unnoticed.
Maxime
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actually supporting those PMICs, but having some axp22x variables
right in the middle. And that's awfully inconsistent.
I'd rather have you add the AXP20x driver directly, and then add the
needed stuff for the AXP22x.
Maxime
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PMICs, but having some axp22x variables
right in the middle. And that's awfully inconsistent.
I'd rather have you add the AXP20x driver directly, and then add the
needed stuff for the AXP22x.
Maxime
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but we hadn't figure that
out at the time. So what we ended up doing is disabling the interrupts
by default and then enable it only on the CPU meant to receive the
queue interrupts.
What we found out doing so was that the per-cpu interrupts were
enabled on the cpu calling request_percpu_irq, and so t
but we hadn't figure that
out at the time. So what we ended up doing is disabling the interrupts
by default and then enable it only on the CPU meant to receive the
queue interrupts.
What we found out doing so was that the per-cpu interrupts were
enabled on the cpu calling request_percpu_irq, and so t
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l lines of
> > NAND chip etc), but it doesn't mean NAND chip itself has completed
> > command execution. That's why "waitfunc" is not direct replacement here.
> >
> > 2. NAND_ISR_{RX|TX}DMACOMPLETE - this flag indicates completion of DMA
> > transfer to/fro
now to provide
further feedback.
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t.
> My working uboot code is in https://github.com/linux-sunxi/u-boot-sunxi.git
> Note this is only test patch. I have not commit it formally for uboot.
Please do so. I'd like very much to avoid ending up in a situation where
we would break the mainline kernel for the A20, without any bootloader
we can point the users to to fix the issues.
Maxime
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, without any bootloader
we can point the users to to fix the issues.
Maxime
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ader don't set it?
From what you're saying, it's will be set by the kernel if it's booted
in hypervisor mode, but what if it's not?
The ARM documentation says that the CNTVOFF register will hold an
undefined value, how would that affect the kernel?
Thanks,
Maxime
--
Maxime Ripard, Free Electro
booted
in hypervisor mode, but what if it's not?
The ARM documentation says that the CNTVOFF register will hold an
undefined value, how would that affect the kernel?
Thanks,
Maxime
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Embedded Linux, Kernel and Android engineering
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On Wed, Jul 03, 2013 at 10:55:05AM +0200, maxime.rip...@free-electrons.com
wrote:
> Hi Jean-Christophe,
>
> On Tue, Jun 18, 2013 at 10:44:17AM +0200, Hector Palacios wrote:
> > For a combination of 18bit LCD data bus width and a color
> > mode of 32bpp, the driver was sett
On Wed, Jul 03, 2013 at 10:55:05AM +0200, maxime.rip...@free-electrons.com
wrote:
Hi Jean-Christophe,
On Tue, Jun 18, 2013 at 10:44:17AM +0200, Hector Palacios wrote:
For a combination of 18bit LCD data bus width and a color
mode of 32bpp, the driver was setting the color mapping
Hi Hector,
On Thu, Jul 11, 2013 at 10:56:42AM +0200, Hector Palacios wrote:
> On 07/11/2013 10:24 AM, maxime.rip...@free-electrons.com wrote:
> >>I haven't seen this is supported upstream. Is anybody working on that?
> >>Where would such a driver fit?
> >
> >C
put such a driver, I started a discussion about
this last week. Mostly, that would be part of MTD, from what is out of
the discussion so far.
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/182002.html
Maxime
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started a discussion about
this last week. Mostly, that would be part of MTD, from what is out of
the discussion so far.
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/182002.html
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
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Hi Hector,
On Thu, Jul 11, 2013 at 10:56:42AM +0200, Hector Palacios wrote:
On 07/11/2013 10:24 AM, maxime.rip...@free-electrons.com wrote:
I haven't seen this is supported upstream. Is anybody working on that?
Where would such a driver fit?
Christoph Baumann recently started porting
on't see this patch in your for-next branch.
It would be really great to have it for 3.11 if possible.
Could you take a look at this patch please?
Thanks,
Maxime
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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is using it and high level applications like Qt5 cannot work
with it either.
Reference: https://lkml.org/lkml/2013/5/23/220
Signed-off-by: Hector Palacios hector.palac...@digi.com
Acked-by: Juergen Beisert j...@pengutronix.de
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
I don't
Hi Hector,
On Fri, Jun 07, 2013 at 11:02:28AM +0200, maxime.rip...@free-electrons.com
wrote:
> On Fri, Jun 07, 2013 at 10:10:39AM +0200, Hector Palacios wrote:
> > For a combination of 18bit LCD data bus width and a color
> > mode of 32bpp, the driver was setting the color mappin
Hi Hector,
On Fri, Jun 07, 2013 at 11:02:28AM +0200, maxime.rip...@free-electrons.com
wrote:
On Fri, Jun 07, 2013 at 10:10:39AM +0200, Hector Palacios wrote:
For a combination of 18bit LCD data bus width and a color
mode of 32bpp, the driver was setting the color mapping to
rgb666, which
Hi Hector,
On Fri, Jun 07, 2013 at 10:10:39AM +0200, Hector Palacios wrote:
> For a combination of 18bit LCD data bus width and a color
> mode of 32bpp, the driver was setting the color mapping to
> rgb666, which is wrong, as the color in memory realy has an
> rgb888 layout.
>
> This patch also
bit data bus width and 32bpp.
We (Free Electrons) are doing the bring up for the Crystalfontz boards,
so it's fine :)
Thanks!
Maxime
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Hi Hector,
On Fri, May 24, 2013 at 03:33:19PM +0200, Juergen Beisert wrote:
> Someone told me, Qt5 cannot handle this special RGB666 mode (even not the
> def_rgb666_shift memory layout mentioned above). My test are based on Qt4.
> Qt5 needs a regular RGB888 mode, which should silently be
Hi Hector,
On Fri, May 24, 2013 at 03:33:19PM +0200, Juergen Beisert wrote:
Someone told me, Qt5 cannot handle this special RGB666 mode (even not the
def_rgb666_shift memory layout mentioned above). My test are based on Qt4.
Qt5 needs a regular RGB888 mode, which should silently be converted
and 32bpp.
We (Free Electrons) are doing the bring up for the Crystalfontz boards,
so it's fine :)
Thanks!
Maxime
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it and high level applications like Qt5 cannot work
with it either.
Reference: https://lkml.org/lkml/2013/5/23/220
Signed-off-by: Hector Palacios hector.palac...@digi.com
Acked-by: Juergen Beisert j...@pengutronix.de
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Please also note
Hi Juergen,
On Thu, May 23, 2013 at 03:31:31PM +0200, Juergen Beisert wrote:
> Hi Maxime,
>
> maxime.rip...@free-electrons.com wrote:
> > On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
> > > I'm using an i.MX28 based board with lcd connected with 1
Hi Juergen,
On Thu, May 23, 2013 at 03:31:31PM +0200, Juergen Beisert wrote:
Hi Maxime,
maxime.rip...@free-electrons.com wrote:
On Thu, May 23, 2013 at 01:55:28PM +0200, Hector Palacios wrote:
I'm using an i.MX28 based board with lcd connected with 18bits data bus.
My platform uses 32
ch, it was not a bug in the driver.
While this is correct, I wonder, now that since we had that same problem
in a very short amount of time, if we couldn't set this behaviour
dependant of some (dt? kernel argument?) property so that one could
customise it anyway he want.
Maxime
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Maxime Ripard,
customise it anyway he want.
Maxime
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A 32-bit kernel on a legacy (or even new) system in 2017 will still
need
> regular kernel updates (not \"long term\" un0maintained kernels)
> in order to work with new USB devices, new 4KB+ sector hard drives,
> newer generations of SSDs, etc..
12-years-old machine is trash. If someone can buy
A 32-bit kernel on a legacy (or even new) system in 2017 will still
need
regular kernel updates (not \long term\ un0maintained kernels)
in order to work with new USB devices, new 4KB+ sector hard drives,
newer generations of SSDs, etc..
12-years-old machine is trash. If someone can buy e.g.
eases:
http://www.mail-archive.com/[EMAIL PROTECTED]/msg00353.html
I'm going to test the patch on other amd64 machines as well, thanks a
lot and keep up goo the work!
Ciao,
Free
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://www.mail-archive.com/[EMAIL PROTECTED]/msg00353.html
I'm going to test the patch on other amd64 machines as well, thanks a
lot and keep up goo the work!
Ciao,
Free
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config I used:
http://people.64studio.com/~free/config-2.6.21-rt1
Ciao,
Free
[0] http://people.64studio.com/~free/udev
[1] http://www.mail-archive.com/[EMAIL PROTECTED]/msg00332.html
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/~free/config-2.6.21-rt1
Ciao,
Free
[0] http://people.64studio.com/~free/udev
[1] http://www.mail-archive.com/[EMAIL PROTECTED]/msg00332.html
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