Add more algorithm support for the driver.
Add support for ecb(aes), cfb(aes) and ecb(des3_ede).
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/cptvf_algs.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/d
Add more algorithm support for the driver.
Add support for ecb(aes), cfb(aes) and ecb(des3_ede).
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_algs.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/drivers/crypto/cavium/cpt
Remove the individual encrypt/decrypt function for easch algorithm.
This is in prepration of adding more crypto algorithms supported by
hardware. While at that simplify create_ctx_hdr/create_input_list
function interfaces.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
d
Remove the individual encrypt/decrypt function for easch algorithm.
This is in prepration of adding more crypto algorithms supported by
hardware. While at that simplify create_ctx_hdr/create_input_list
function interfaces.
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_algs.c
Mailbox interrupt is common and it is not an error interrupt.
So downgrade the print from dev_err to dev_dbg.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/cptvf_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
Mailbox interrupt is common and it is not an error interrupt.
So downgrade the print from dev_err to dev_dbg.
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c
b
This series adds more algorithem support for CPT.
Add support for
-ecb(aes)
-cfb(aes)
-ecb(des3_ede)
Some cleanups too.
George Cherian (3):
crypto: cavium: Downgrade the annoying misc interrupt print from
dev_err to dev_dbg
crypto: cavium: Remove the individual
This series adds more algorithem support for CPT.
Add support for
-ecb(aes)
-cfb(aes)
-ecb(des3_ede)
Some cleanups too.
George Cherian (3):
crypto: cavium: Downgrade the annoying misc interrupt print from
dev_err to dev_dbg
crypto: cavium: Remove the individual
Remove the individual encrypt/decrypt function for easch algorithm.
This is in prepration of adding more crypto algorithms supported by
hardware. While at that simplify create_ctx_hdr/create_input_list
function interfaces.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
d
Remove the individual encrypt/decrypt function for easch algorithm.
This is in prepration of adding more crypto algorithms supported by
hardware. While at that simplify create_ctx_hdr/create_input_list
function interfaces.
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_algs.c
Mailbox interrupt is common and it is not an error interrupt.
So downgrade the print from dev_err to dev_dbg.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/cptvf_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
Mailbox interrupt is common and it is not an error interrupt.
So downgrade the print from dev_err to dev_dbg.
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c
b
This series adds more algorithem support for CPT.
Add support for
-ecb(aes)
-cfb(aes)
-ecb(des3_ede)
Some cleanups too.
George Cherian (3):
crypto: cavium: Downgrade the annoying misc interrupt print from
dev_err to dev_dbg
crypto: cavium: Remove the individual
This series adds more algorithem support for CPT.
Add support for
-ecb(aes)
-cfb(aes)
-ecb(des3_ede)
Some cleanups too.
George Cherian (3):
crypto: cavium: Downgrade the annoying misc interrupt print from
dev_err to dev_dbg
crypto: cavium: Remove the individual
Add more algorithm support for the driver.
Add support for ecb(aes), cfb(aes) and ecb(des3_ede).
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/cptvf_algs.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/d
Add more algorithm support for the driver.
Add support for ecb(aes), cfb(aes) and ecb(des3_ede).
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/cptvf_algs.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/drivers/crypto/cavium/cpt
num_vfs is always calculated as zero.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 1 +
drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/cavium/t
num_vfs is always calculated as zero.
Signed-off-by: George Cherian
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 1 +
drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
b/drivers
Hi Hoan/Prashanth,
On 04/03/2017 11:20 PM, Hoan Tran wrote:
Hi George,
On Mon, Apr 3, 2017 at 9:44 AM, Prakash, Prashanth
<pprak...@codeaurora.org> wrote:
Hi George,
On 3/31/2017 12:24 AM, George Cherian wrote:
The current cppc acpi driver works with only one pcc subspace id.
It mai
Hi Hoan/Prashanth,
On 04/03/2017 11:20 PM, Hoan Tran wrote:
Hi George,
On Mon, Apr 3, 2017 at 9:44 AM, Prakash, Prashanth
wrote:
Hi George,
On 3/31/2017 12:24 AM, George Cherian wrote:
The current cppc acpi driver works with only one pcc subspace id.
It maintains and registers only one
Hi Alexey,
On 04/03/2017 11:07 PM, Alexey Klimov wrote:
(adding Prashanth to c/c)
Hi George,
On Fri, Mar 31, 2017 at 06:24:02AM +, George Cherian wrote:
Based on Section 14.1 of ACPI specification, it is possible to have a
maximum of 256 PCC subspace ids. Add support of multiple PCC
Hi Alexey,
On 04/03/2017 11:07 PM, Alexey Klimov wrote:
(adding Prashanth to c/c)
Hi George,
On Fri, Mar 31, 2017 at 06:24:02AM +, George Cherian wrote:
Based on Section 14.1 of ACPI specification, it is possible to have a
maximum of 256 PCC subspace ids. Add support of multiple PCC
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to
add subspace id support for cppc_acpi driver.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/mailbox/pcc.c | 1 -
include/acpi/pcc.h| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to
add subspace id support for cppc_acpi driver.
Signed-off-by: George Cherian
---
drivers/mailbox/pcc.c | 1 -
include/acpi/pcc.h| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox
: In preparation to share the MAX_PCC_SUBSPACE definition with cppc acpi
driver
Patch 2 : Make the cppc acpi driver aware of multiple pcc subspace ids.
George Cherian (2):
mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file
ACPI / CPPC: Make cppc acpi driver aware of pcc
is initialized properly. Also maintain a global total_mpar_count
which is a sum of per subspace id mpar value.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/acpi/cppc_acpi.c | 189 ++-
1 file changed, 105 insertions(+), 84 del
: In preparation to share the MAX_PCC_SUBSPACE definition with cppc acpi
driver
Patch 2 : Make the cppc acpi driver aware of multiple pcc subspace ids.
George Cherian (2):
mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file
ACPI / CPPC: Make cppc acpi driver aware of pcc
is initialized properly. Also maintain a global total_mpar_count
which is a sum of per subspace id mpar value.
Signed-off-by: George Cherian
---
drivers/acpi/cppc_acpi.c | 189 ++-
1 file changed, 105 insertions(+), 84 deletions(-)
diff --git a/drivers/acpi
Fix the following smatch errors
cptvf_reqmanager.c:333 do_post_process() warn: variable dereferenced
before check 'cptvf'
cptvf_main.c:825 cptvf_remove() error: we previously assumed 'cptvf'
could be null
Reported-by: Dan Carpenter <dan.carpen...@oracle.com>
Signed-off-by: George C
Fix the following smatch errors
cptvf_reqmanager.c:333 do_post_process() warn: variable dereferenced
before check 'cptvf'
cptvf_main.c:825 cptvf_remove() error: we previously assumed 'cptvf'
could be null
Reported-by: Dan Carpenter
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt
.
Can you please test it and make sure it goes in before the end of the
merge window so that no more users of the old API hit mainline?
Yes the changes works well.
Acked-by: George Cherian <george.cher...@cavium.com>
for the series.
.
Can you please test it and make sure it goes in before the end of the
merge window so that no more users of the old API hit mainline?
Yes the changes works well.
Acked-by: George Cherian
for the series.
ed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/cptpf_mbox.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/cavium/cpt/cptpf_mbox.c
b/drivers/crypto/cavium/cpt/cptpf_mbox.c
index 5818b41..20f2c6e 100644
--- a/drivers/c
cpt_bind_vq_to_grp() could return an error code. However, it currently
returns a u8. This produce the static checker warning.
drivers/crypto/cavium/cpt/cptpf_mbox.c:70 cpt_bind_vq_to_grp() warn: signedness
bug returning '(-22)'
Reported-by: Dan Carpenter
Signed-off-by: George Cherian
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Update the MAINTAINERS file too.
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
MAINTAINERS | 7 +++
drivers/crypto/Kconfig |
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Update the MAINTAINERS file too.
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
MAINTAINERS | 7 +++
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
3 files changed, 9 insertions
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypt
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 135
drivers/crypto
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian <george.cher...@cavium.
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian
Reviewed-by: David Daney
cro definitions
-- Remove the redundant ROUNDUP* macros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3):
drivers: cryp
cro definitions
-- Remove the redundant ROUNDUP* macros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3):
drivers: cryp
On Friday 03 February 2017 11:02 PM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
<george.cher...@cavium.com> wrote:
This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT)
CPT is available in Cavium's Octeon-Tx SoC series.
The series was
On Friday 03 February 2017 11:02 PM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
wrote:
This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT)
CPT is available in Cavium's Octeon-Tx SoC series.
The series was tested with ecryptfs and dm-crypt
Hi Sasha,
Thanks for the reveiw.
On Friday 03 February 2017 12:24 AM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
<george.cher...@cavium.com> wrote:
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c
b/drivers/crypto/cavium/cpt/cptvf_main.c
new file mode
Hi Sasha,
Thanks for the reveiw.
On Friday 03 February 2017 12:24 AM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
wrote:
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c
b/drivers/crypto/cavium/cpt/cptvf_main.c
new file mode 100644
index 000..4cf466d
--- /dev
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypt
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 135
drivers/crypto
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian <george.cher...@cavium.
definitions
-- Remove the redundant ROUNDUP* macros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian
Reviewed-by: David Daney
definitions
-- Remove the redundant ROUNDUP* macros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3
Hi Stephan,
Thank you for the clarification.
Regards,
-George
On 01/12/2017 04:49 PM, Stephan Müller wrote:
Am Donnerstag, 12. Januar 2017, 16:40:32 CET schrieb George Cherian:
Hi George,
Sure, please do not forget to invoke xts_verify_key.
Should I be using xts_check_key
Hi Stephan,
Thank you for the clarification.
Regards,
-George
On 01/12/2017 04:49 PM, Stephan Müller wrote:
Am Donnerstag, 12. Januar 2017, 16:40:32 CET schrieb George Cherian:
Hi George,
Sure, please do not forget to invoke xts_verify_key.
Should I be using xts_check_key
Hi Stephan,
On 01/11/2017 06:09 PM, Stephan Müller wrote:
Am Mittwoch, 11. Januar 2017, 16:58:17 CET schrieb George Cherian:
Hi George,
I will add a seperate function for xts setkey and make changes as following.
...
+
+struct crypto_alg algs[] = { {
+ .cra_flags
Hi Stephan,
On 01/11/2017 06:09 PM, Stephan Müller wrote:
Am Mittwoch, 11. Januar 2017, 16:58:17 CET schrieb George Cherian:
Hi George,
I will add a seperate function for xts setkey and make changes as following.
...
+
+struct crypto_alg algs[] = { {
+ .cra_flags
Hi Stephan,
Thanks for pointing it out!!
On 01/11/2017 04:42 PM, Stephan Müller wrote:
Am Mittwoch, 11. Januar 2017, 10:56:50 CET schrieb George Cherian:
Hi George,
+int cvm_enc_dec_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
+ u32 keylen)
+{
+ struct
Hi Stephan,
Thanks for pointing it out!!
On 01/11/2017 04:42 PM, Stephan Müller wrote:
Am Mittwoch, 11. Januar 2017, 10:56:50 CET schrieb George Cherian:
Hi George,
+int cvm_enc_dec_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
+ u32 keylen)
+{
+ struct
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian <george.cher...@cavium.
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypt
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 135
drivers/crypto
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian
Reviewed-by: David Daney
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian <george.cher...@cavium.com>
Reviewed-by: David Daney <david.da...@cavium.com>
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index
s Cleanup
George Cherian (3):
drivers: crypto: Add Support for Octeon-tx CPT Engine
drivers: crypto: Add the Virtual Function driver for CPT
drivers: crypto: Enable CPT options crypto for build
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile
s Cleanup
George Cherian (3):
drivers: crypto: Add Support for Octeon-tx CPT Engine
drivers: crypto: Add the Virtual Function driver for CPT
drivers: crypto: Enable CPT options crypto for build
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile
Hi Corentin,
On 12/21/2016 07:31 PM, Corentin Labbe wrote:
Hello
I have some comment inline
On Wed, Dec 21, 2016 at 11:56:12AM +, george.cher...@cavium.com wrote:
From: George Cherian <george.cher...@cavium.com>
Enable the CPT VF driver. CPT is the cryptographic Accelaratio
Hi Corentin,
On 12/21/2016 07:31 PM, Corentin Labbe wrote:
Hello
I have some comment inline
On Wed, Dec 21, 2016 at 11:56:12AM +, george.cher...@cavium.com wrote:
From: George Cherian
Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit
typo acceleration
will fix
:
From: George Cherian <george.cher...@cavium.com>
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
typo driver
okay
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asym
:
From: George Cherian
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
typo driver
okay
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off
Hi,
I got few review comments for this series from David Daney.
I am reworking on this series and will sent v3 once it is done.
So,kindly ignore this series
Regards,
-George
On 12/13/2016 07:33 PM, George Cherian wrote:
This series adds the support for Cavium Cryptographic Accelerarion Unit
Hi,
I got few review comments for this series from David Daney.
I am reworking on this series and will sent v3 once it is done.
So,kindly ignore this series
Regards,
-George
On 12/13/2016 07:33 PM, George Cherian wrote:
This series adds the support for Cavium Cryptographic Accelerarion Unit
ros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3):
drivers: crypto: Add Support for Octeon-tx CPT Engine
driv
ros and use kernel function
-- Select proper config option in Kconfig file.
-- Removed some of the unwanted header file inclusions
-- Miscellaneous Cleanup
George Cherian (3):
drivers: crypto: Add Support for Octeon-tx CPT Engine
driv
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian <george.cher...@cavium.
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian
---
drivers/crypto/cavium
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4d2b81f..15f9040 100644
Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian <george.cher...@cavium.com>
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 145
drivers/
Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 145
drivers/crypto/cavium/cpt/cptvf_algs.c
Hi David,
Thanks for the review.
On Saturday 19 November 2016 12:25 AM, David Daney wrote:
On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote:
From: George Cherian <george.cher...@cavium.com>
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx
Hi David,
Thanks for the review.
On Saturday 19 November 2016 12:25 AM, David Daney wrote:
On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote:
From: George Cherian
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT
Hi Robert,
+Roger
On Thu, Mar 19, 2015 at 5:37 PM, Robert Baldyga wrote:
> Hi George,
>
> On 03/19/2015 09:50 AM, George Cherian wrote:
>> Hi Robert,
>>
>> This looks like a extcon driver based on gpio for USB.
>>
>> Roger posted a generic one a while back
Hi Robert,
This looks like a extcon driver based on gpio for USB.
Roger posted a generic one a while back.
https://lkml.org/lkml/2015/2/2/187
Doesn't this serve the purpose rather than adding this driver?
-George
On Wed, Mar 18, 2015 at 7:34 PM, Robert Baldyga wrote:
> This patch adds extcon
Hi Robert,
On Wed, Mar 18, 2015 at 7:34 PM, Robert Baldyga wrote:
>
> This patch introduces OTG support in DWC3 driver. OTG feature is responsible
> for dynamic USB role switching (between host and peripheral modes) based
> on detected cable type.
>
> Each role switch causes complete core
Hi Robert,
On Wed, Mar 18, 2015 at 7:34 PM, Robert Baldyga r.bald...@samsung.com wrote:
This patch introduces OTG support in DWC3 driver. OTG feature is responsible
for dynamic USB role switching (between host and peripheral modes) based
on detected cable type.
Each role switch causes
Hi Robert,
This looks like a extcon driver based on gpio for USB.
Roger posted a generic one a while back.
https://lkml.org/lkml/2015/2/2/187
Doesn't this serve the purpose rather than adding this driver?
-George
On Wed, Mar 18, 2015 at 7:34 PM, Robert Baldyga r.bald...@samsung.com wrote:
Hi Robert,
+Roger
On Thu, Mar 19, 2015 at 5:37 PM, Robert Baldyga r.bald...@samsung.com wrote:
Hi George,
On 03/19/2015 09:50 AM, George Cherian wrote:
Hi Robert,
This looks like a extcon driver based on gpio for USB.
Roger posted a generic one a while back.
https://lkml.org/lkml/2015/2
On 02/12/2015 11:52 PM, Felipe Balbi wrote:
On Thu, Feb 12, 2015 at 11:13:16AM +0530, George Cherian wrote:
>In the wrapper the IRQ disable should be done by writing 1's to the
>IRQ*_CLR register. Existing code is broken because it instead writes
>zeros to IRQ*_SET registe
: 72246da40f37 ("usb: Introduce DesignWare USB3 DRD Driver")
Cc: # v3.2+
Signed-off-by: George Cherian
---
drivers/usb/dwc3/dwc3-omap.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-om
: 72246da40f37 (usb: Introduce DesignWare USB3 DRD Driver)
Cc: sta...@vger.kernel.org # v3.2+
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/dwc3-omap.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-omap.c b
On 02/12/2015 11:52 PM, Felipe Balbi wrote:
On Thu, Feb 12, 2015 at 11:13:16AM +0530, George Cherian wrote:
In the wrapper the IRQ disable should be done by writing 1's to the
IRQ*_CLR register. Existing code is broken because it instead writes
zeros to IRQ*_SET register.
Fix this by adding
-by: George Cherian
---
drivers/usb/dwc3/dwc3-omap.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 172d64e..52e0c4e 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3
-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/dwc3-omap.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 172d64e..52e0c4e 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
to preserve the already allocated xhci struct for the subsequent
call of usb_add_hcd() from the DRD library.
A new quirk flag XHCI_DRD_SUPPORT is added to differentiate between
normal usb_remove_hcd and drd specific call.
Signed-off-by: George Cherian
---
drivers/usb/host/xhci.c | 22
() or IP specific low level start/stop
defined in ll_start/stop
Signed-off-by: George Cherian
---
drivers/usb/Kconfig | 15 ++
drivers/usb/common/Makefile | 1 +
drivers/usb/common/drd-lib.c | 346 +++
include/linux/usb/drd.h | 77 ++
4
Adapt the xhci-plat driver to use drd library functions.
In prepration to support DRD on dwc3.
Signed-off-by: George Cherian
---
drivers/usb/host/xhci-plat.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index
Extend the platform data to pass XHCI_NEEDS_LHC_RESET quirk to
the xhci driver.
Signed-off-by: George Cherian
---
drivers/usb/host/xhci-plat.c | 3 +++
include/linux/usb/xhci_pdriver.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci
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