--- Original Message ---
Sender : Jerome Glisse
Date : Aug 03, 2015 17:26 (GMT+05:30)
Title : Re: [PATCH 05/15] HMM: introduce heterogeneous memory management v4.
On Mon, Aug 03, 2015 at 01:20:13PM +0530, Girish KS wrote:
> On 18-Jul-2015 12:47 am, "J��e Glisse"
--- Original Message ---
Sender : Jerome Glissej.gli...@gmail.com
Date : Aug 03, 2015 17:26 (GMT+05:30)
Title : Re: [PATCH 05/15] HMM: introduce heterogeneous memory management v4.
On Mon, Aug 03, 2015 at 01:20:13PM +0530, Girish KS wrote:
On 18-Jul-2015 12:47 am,
;txtimer.function = sxgbe_tx_timer;
add_timer(>txtimer);
}
}
Looks good to me.
Acked by: Girish K S
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= sxgbe_tx_timer;
add_timer(p-txtimer);
}
}
Looks good to me.
Acked by: Girish K S ks.g...@samsung.com
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0¶ìh®å’i
This patch series is based on the mailbox framework prepared by jassi
and others.
Girish K S (2):
mailbox: samsung: added support for samsung mailbox
arm64: dts: exynos: added mailbox node
.../bindings/mailbox/samsung-mailbox.txt | 24 ++
arch/arm64/boot/dts/samsung-gh7.dtsi
This patch adds the dt node for the mailbox IP
Signed-off-by: Girish K S
Change-Id: I35e45e9a62592887a84a909aee54f259a2f731fa
---
.../bindings/mailbox/samsung-mailbox.txt | 24 +++
arch/arm64/boot/dts/samsung-gh7.dtsi | 66
arch/arm64/boot
This patch adds support to the samsung mailbox driver.
Signed-off-by: Girish K S
---
drivers/mailbox/Kconfig |8 +
drivers/mailbox/Makefile |2 +
drivers/mailbox/mailbox-samsung.c | 354 +
include/linux/mailbox-samsung.h | 112
This patch adds support to the samsung mailbox driver.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/mailbox/Kconfig |8 +
drivers/mailbox/Makefile |2 +
drivers/mailbox/mailbox-samsung.c | 354 +
include/linux/mailbox
This patch adds the dt node for the mailbox IP
Signed-off-by: Girish K S ks.g...@samsung.com
Change-Id: I35e45e9a62592887a84a909aee54f259a2f731fa
---
.../bindings/mailbox/samsung-mailbox.txt | 24 +++
arch/arm64/boot/dts/samsung-gh7.dtsi | 66
This patch series is based on the mailbox framework prepared by jassi
and others.
Girish K S (2):
mailbox: samsung: added support for samsung mailbox
arm64: dts: exynos: added mailbox node
.../bindings/mailbox/samsung-mailbox.txt | 24 ++
arch/arm64/boot/dts/samsung-gh7.dtsi
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index d170cc0..ea82baa 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -434,6 +434,9 @@
-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index d170cc0..ea82baa 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -434,6 +434,9 @@ static int
This patch series adds support for the dedicated cs pin and
support for exynos5440 spi controller. The first patch
"Polling support for s3c64xx spi controller" in the previous
serias is already applied to Mark's spi-next branch. So created
a new series with remaining 2 patches.
Gir
From: Girish K S
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin
From: Girish K S
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
This patch series adds support for the dedicated cs pin and
support for exynos5440 spi controller. The first patch
Polling support for s3c64xx spi controller in the previous
serias is already applied to Mark's spi-next branch. So created
a new series with remaining 2 patches.
Girish K S (2
From: Girish K S girishks2...@gmail.com
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted
From: Girish K S girishks2...@gmail.com
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
From: Girish K S
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
From: Girish K S
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin
From: Girish K S
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives
This patch series adds support for the polling mode only. Also 2nd patch
in the series adds support for dedicated cs pin. After Thomas's patch for
using default gpio is merged(commit id: 00ab539), one of the patch in this
series is dropped and new series is generated.
Girish K S (3):
spi
This patch series adds support for the polling mode only. Also 2nd patch
in the series adds support for dedicated cs pin. After Thomas's patch for
using default gpio is merged(commit id: 00ab539), one of the patch in this
series is dropped and new series is generated.
Girish K S (3):
spi
From: Girish K S girishks2...@gmail.com
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling
From: Girish K S girishks2...@gmail.com
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted
From: Girish K S girishks2...@gmail.com
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
From: Girish K S
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
From: Girish K S
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives
From: Girish K S
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin
This patch series adds support for the polling mode only. Also 2nd patch
in the series adds support for dedicated cs pin. After Thomas's patch for
using default gpio is merged(commit id: 00ab539), one of the patch in this
series is dropped and new series is generated.
Girish K S (3):
spi
This patch series adds support for the polling mode only. Also 2nd patch
in the series adds support for dedicated cs pin. After Thomas's patch for
using default gpio is merged(commit id: 00ab539), one of the patch in this
series is dropped and new series is generated.
Girish K S (3):
spi
From: Girish K S girishks2...@gmail.com
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling
From: Girish K S girishks2...@gmail.com
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted
From: Girish K S girishks2...@gmail.com
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
This patch adds dts support for the sata controller
Signed-off-by: Girish K S
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 7c5dc38..2dc4ffa
This patch adds the compatible string of the exynos5440 sata controller
compliant with the ahci 1.3 and sata 3.0 specification.
Signed-off-by: Girish K S
changes in v2:
changed the compatible string by adding the actual IP
owners name instead of the SoC vendor name
This patch adds the compatible string of the exynos5440 sata controller
compliant with the ahci 1.3 and sata 3.0 specification.
Signed-off-by: Girish K S
---
drivers/ata/ahci_platform.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/ahci_platform.c b
This patch adds dts support for the sata controller
Signed-off-by: Girish K S
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 7c5dc38..2dc4ffa
This patch enables the SPI in EXYNOS5440 SoC. The NOR
Flash can be accessed by enabling the spi interface
Signed-off-by: Girish K S
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 39 +++-
arch/arm/boot/dts/exynos5440.dtsi | 16 +++
2 files changed
This patch enables the SPI in EXYNOS5440 SoC. The NOR
Flash can be accessed by enabling the spi interface
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 39 +++-
arch/arm/boot/dts/exynos5440.dtsi | 16
This patch adds dts support for the sata controller
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index
This patch adds the compatible string of the exynos5440 sata controller
compliant with the ahci 1.3 and sata 3.0 specification.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/ata/ahci_platform.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/ata
This patch adds the compatible string of the exynos5440 sata controller
compliant with the ahci 1.3 and sata 3.0 specification.
Signed-off-by: Girish K S ks.g...@samsung.com
changes in v2:
changed the compatible string by adding the actual IP
owners name instead of the SoC vendor
This patch adds dts support for the sata controller
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index
From: Girish K S
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The decision is made by parsing the "gpios" property in th
From: Girish K S
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
From: Girish K S
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives
From: Girish K S
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin
From: Girish K S girishks2...@gmail.com
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling
From: Girish K S girishks2...@gmail.com
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted
From: Girish K S girishks2...@gmail.com
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
From: Girish K S girishks2...@gmail.com
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The decision is made by parsing the gpios property
From: Girish K S
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
From: Girish K S
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling mode
and gives
From: Girish K S
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt handler to read the status register and
clear
From: Girish K S
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted/deasserted using gpio pin
of generic dma
patch. resolved the merge conflicts and tested for the functionality
Girish K S (5):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi: s3c64xx: Added provision for non-gpio i/o's
spi: s3c64xx: Added provision
From: Girish K S
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The decision is made by parsing the "gpios" property in th
of generic dma
patch. resolved the merge conflicts and tested for the functionality
Girish K S (5):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi: s3c64xx: Added provision for non-gpio i/o's
spi: s3c64xx: Added provision
From: Girish K S girishks2...@gmail.com
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The decision is made by parsing the gpios property
From: Girish K S girishks2...@gmail.com
The existing driver supports gpio based /cs signal.
For controller's that have one device per controller,
the slave device's /cs signal might be internally controlled
by the chip select bit of slave select register. They are not
externally asserted
From: Girish K S girishks2...@gmail.com
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt handler to read the status register
From: Girish K S girishks2...@gmail.com
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
Some SoC's that adopt this controller might not have have dma
interface. This patch adds support for complete polling
From: Girish K S girishks2...@gmail.com
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
]: provision to support dedicated cs pin
[PATCH 5/5]: support exynos5440 SoC in polling mode
Tested this patch on exynos5250 in dma mode, and exynos5440 in
polling mode.
Girish K S (5):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi
by: Girish K S
---
changes in v2:
Removed the gpio quirk. Parse the "gpios" property
to decide whether gpio / dedicated i/o lines should
be used.
drivers/spi/spi-s3c64xx.c |8
1 file changed, 8 insertions(+)
diff --g
support for controllers with dedicated /cs pin.
if "cs-gpio" property doesnt exist in a spi dts node, the controller
would treat the /cs pin as dedicated.
Signed-off-by: Girish K S
---
changes in v2:
added provision to use either gpio/dedicated pins as chip
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
changes in v2:
the fifo mask modified
to select poll/dma mode.
Signed-off-by: Girish K S
---
changes in v2:
Added quirk to force polling mode. Modified the
wait_for_zfer function, to handle the polling mode
support. Before reading the data from the Rx fifo,
no. of iterations
in the clear pending register.
Modified the hwInit function to clear all the pending interrupts.
Signed-off-by: Girish K S
---
changes in v2:
Modified the interrupt handler to clear the pending
register after setting to value 1.
drivers/spi/spi-s3c64xx.c | 41
in the clear pending register.
Modified the hwInit function to clear all the pending interrupts.
Signed-off-by: Girish K S ks.g...@samsung.com
---
changes in v2:
Modified the interrupt handler to clear the pending
register after setting to value 1.
drivers/spi/spi
to select poll/dma mode.
Signed-off-by: Girish K S ks.g...@samsung.com
---
changes in v2:
Added quirk to force polling mode. Modified the
wait_for_zfer function, to handle the polling mode
support. Before reading the data from the Rx fifo
support for controllers with dedicated /cs pin.
if cs-gpio property doesnt exist in a spi dts node, the controller
would treat the /cs pin as dedicated.
Signed-off-by: Girish K S ks.g...@samsung.com
---
changes in v2:
added provision to use either gpio/dedicated pins as chip
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
---
changes in v2:
the fifo
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The decision is made by parsing the gpios property in the spi
node.
Signed-off-by: Girish K
]: provision to support dedicated cs pin
[PATCH 5/5]: support exynos5440 SoC in polling mode
Tested this patch on exynos5250 in dma mode, and exynos5440 in
polling mode.
Girish K S (5):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi
in the clear pending register.
Modified the hwInit function to clear all the pending interrupts.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 41 +
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 12
1 file
to select poll/dma mode.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 65 +
1 file changed, 30 insertions(+), 35 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b770f88..90770bd 100644
--- a/drivers/spi
This patch adds support for spi controllers with
dedicated clk/miso/mosi/cs pins. It skips the gpio
parsing and initialization for controllers that
have dedicated pins.
Signed-off-by: Girish K S
---
drivers/spi/spi-s3c64xx.c | 39 +++
1 file changed, 31
]: Adds the support for exynos5440 SoC, this SoC has
no support for dma transfer and consists of dedicated
i/o pins.
Girish K S (4):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi: s3c64xx: add gpio quirk
]: Adds the support for exynos5440 SoC, this SoC has
no support for dma transfer and consists of dedicated
i/o pins.
Girish K S (4):
spi: s3c64xx: modified error interrupt handling and init
spi: s3c64xx: added support for polling mode
spi: s3c64xx: add gpio quirk
This patch adds support for spi controllers with
dedicated clk/miso/mosi/cs pins. It skips the gpio
parsing and initialization for controllers that
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 39 +++
1
to select poll/dma mode.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 65 +
1 file changed, 30 insertions(+), 35 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b770f88..90770bd
This patch adds support for the exynos5440 spi controller.
The integration of the spi IP in exynos5440 is different from
other SoC's. The I/O pins are no more configured via gpio, they
have dedicated pins.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 12
in the clear pending register.
Modified the hwInit function to clear all the pending interrupts.
Signed-off-by: Girish K S ks.g...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 41 +
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi
On 16 July 2012 09:45, Girish K S wrote:
> On 12 July 2012 18:24, Thomas Abraham wrote:
>> Add device tree based discovery support.
>>
>> Signed-off-by: Thomas Abraham
>> ---
>> .../devicetree/bindings/mmc/synposis-dw-mshc.txt | 108 +++
&g
On 16 July 2012 09:45, Girish K S girish.shivananja...@linaro.org wrote:
On 12 July 2012 18:24, Thomas Abraham thomas.abra...@linaro.org wrote:
Add device tree based discovery support.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw
On 12 July 2012 18:24, Thomas Abraham wrote:
> Some platforms allow for clock gating and control of bus interface unit clock
> and card interface unit clock. Add support for clock lookup of optional biu
> and ciu clocks for clock gating and clock speed determination.
>
> Signed-off-by: Abhilash
On 12 July 2012 18:24, Thomas Abraham thomas.abra...@linaro.org wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
On 28 June 2012 14:02, Yaniv Gardi wrote:
> Adding a new ioctl to support sanitize operation in eMMC
> cards version 4.5.
> The sanitize ioctl support helps performing this operation
> via user application.
>
> Signed-off-by: Yaniv Gardi
>
> ---
> block/blk-core.c | 15 ++--
>
On 28 June 2012 14:02, Yaniv Gardi wrote:
> Adding a new ioctl to support sanitize operation in eMMC
> cards version 4.5.
> The sanitize ioctl support helps performing this operation
> via user application.
>
> Signed-off-by: Yaniv Gardi
>
> ---
> block/blk-core.c | 15 ++--
>
On 28 June 2012 14:02, Yaniv Gardi wrote:
> Adding a new ioctl to support sanitize operation in eMMC
> cards version 4.5.
> The sanitize ioctl support helps performing this operation
> via user application.
>
> Signed-off-by: Yaniv Gardi
>
> ---
> block/blk-core.c | 15 ++--
>
On 28 June 2012 14:02, Yaniv Gardi yga...@codeaurora.org wrote:
Adding a new ioctl to support sanitize operation in eMMC
cards version 4.5.
The sanitize ioctl support helps performing this operation
via user application.
Signed-off-by: Yaniv Gardi yga...@codeaurora.org
---
On 28 June 2012 14:02, Yaniv Gardi yga...@codeaurora.org wrote:
Adding a new ioctl to support sanitize operation in eMMC
cards version 4.5.
The sanitize ioctl support helps performing this operation
via user application.
Signed-off-by: Yaniv Gardi yga...@codeaurora.org
---
On 28 June 2012 14:02, Yaniv Gardi yga...@codeaurora.org wrote:
Adding a new ioctl to support sanitize operation in eMMC
cards version 4.5.
The sanitize ioctl support helps performing this operation
via user application.
Signed-off-by: Yaniv Gardi yga...@codeaurora.org
---
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