Re: [PATCH 1/3] nds32: Cleanup deprecated function strlen_user

st_check long strnlen_user(const char __user * str, long n); > extern unsigned long __arch_copy_from_user(void *to, const void __user * > from, > unsigned long n); Thank you, Guo. Acked-by: Greentime Hu

Re: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Greentime Hu 於 2021年4月19日 週一 上午10:43寫道： > > Palmer Dabbelt 於 2021年3月31日 週三 上午8:24寫道： > > > > On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime...@sifive.com wrote: > > > Signed-off-by: Greentime Hu > > > --- > > > ar

Re: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Palmer Dabbelt 於 2021年3月31日 週三 上午8:24寫道： > > On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime...@sifive.com wrote: > > Signed-off-by: Greentime Hu > > --- > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++ > > 1 file changed, 34 in

Re: [PATCH v5 0/6] Add SiFive FU740 PCIe host controller driver support

Lorenzo Pieralisi 於 2021年4月9日 週五 下午4:54寫道： > > On Tue, 6 Apr 2021 17:26:28 +0800, Greentime Hu wrote: > > This patchset includes SiFive FU740 PCIe host controller driver. We also > > add pcie_aux clock and pcie_power_on_reset controller to prci driver for >

Re: [PATCH v5 0/6] Add SiFive FU740 PCIe host controller driver support

Lorenzo Pieralisi 於 2021年4月9日 週五 上午12:25寫道： > > On Tue, Apr 06, 2021 at 05:26:28PM +0800, Greentime Hu wrote: > > This patchset includes SiFive FU740 PCIe host controller driver. We also > > add pcie_aux clock and pcie_power_on_reset controller to prci driver for >

[PATCH v5 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Signed-off-by: Greentime Hu Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 33 ++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920

[PATCH v5 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver

-by: Greentime Hu Signed-off-by: Greentime Hu --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 308 3 files changed, 318 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie

[PATCH v5 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 113 ++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git

[PATCH v5 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver

Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S

[PATCH v5 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu Reviewed-by: Philipp Zabel Acked-by: Stephen Boyd --- drivers/clk/sifive

[PATCH v5 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu Acked-by: Stephen Boyd --- drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740

[PATCH v5 0/6] Add SiFive FU740 PCIe host controller driver support

ful define - Remove fu740_pcie_pm_ops - Use builtin_platform_driver Greentime Hu (5): clk: sifive: Add pcie_aux clock in prci driver for PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver dt-bindings: PCI: Add Si

Re: [PATCH v2 0/6] Add SiFive FU740 PCIe host controller driver support

Stephen Boyd 於 2021年3月30日 週二 上午3:12寫道： > > Quoting Greentime Hu (2021-03-17 23:08:07) > > This patchset includes SiFive FU740 PCIe host controller driver. We also > > add pcie_aux clock and pcie_power_on_reset controller to prci driver for > > PCIe driver to use it

[PATCH v4 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Signed-off-by: Greentime Hu Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 33 ++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920

[PATCH v4 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver

-by: Greentime Hu Signed-off-by: Greentime Hu --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 3 files changed, 334 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie

[PATCH v4 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 109 ++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git

[PATCH v4 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu Reviewed-by: Philipp Zabel Acked-by: Stephen Boyd --- drivers/clk/sifive

[PATCH v4 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver

Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S

[PATCH v4 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu Acked-by: Stephen Boyd --- drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740

[PATCH v4 0/6] Add SiFive FU740 PCIe host controller driver support

code logic to remove possible infinite loop - Replace magic number with meaningful define - Remove fu740_pcie_pm_ops - Use builtin_platform_driver Greentime Hu (5): clk: sifive: Add pcie_aux clock in prci driver for PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver MAINTA

[PATCH v3 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Signed-off-by: Greentime Hu --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 33 ++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920..b2317c8e3a80 100644 --- a/arch/riscv

[PATCH v3 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver

-by: Greentime Hu Signed-off-by: Greentime Hu --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 3 files changed, 334 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie

[PATCH v3 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver

Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S

[PATCH v3 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 109 ++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git

[PATCH v3 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Reviewed-by: Philipp Zabel Signed-off-by: Greentime Hu --- drivers/clk/sifive/Kconfig | 2 ++ drivers

[PATCH v3 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu --- drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740-prci.h | 2

[PATCH v3 0/6] Add SiFive FU740 PCIe host controller driver support

meaningful define - Remove fu740_pcie_pm_ops - Use builtin_platform_driver Greentime Hu (5): clk: sifive: Add pcie_aux clock in prci driver for PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver dt-bindings: PCI:

Re: [PATCH] nds32: flush_dcache_page: use page_mapping_file to avoid races with swapoff

Greentime Hu 於 2021年3月31日 週三 下午3:30寫道： > > Matthew Wilcox 於 2021年3月31日 週三 上午2:14寫道： > > > > On Tue, Mar 30, 2021 at 08:51:26PM +0300, Mike Rapoport wrote: > > > From: Mike Rapoport > > > > > > Commit cb9f753a3731 ("mm: fix races between swapoff

Re: [PATCH] nds32: flush_dcache_page: use page_mapping_file to avoid races with swapoff

Matthew Wilcox 於 2021年3月31日 週三 上午2:14寫道： > > On Tue, Mar 30, 2021 at 08:51:26PM +0300, Mike Rapoport wrote: > > From: Mike Rapoport > > > > Commit cb9f753a3731 ("mm: fix races between swapoff and flush dcache") > > updated flush_dcache_page implementations on several architectures to use > >

Re: [PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

Stephen Boyd 於 2021年3月30日 週二 上午3:14寫道： > > Quoting Greentime Hu (2021-03-17 23:08:09) > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > > index 71ab75a46491..f094df93d911 100644 > > --- a/drivers/reset/Kconfig > > +++ b/drivers/reset/Kconfig

Re: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Rob Herring 於 2021年3月24日 週三 上午4:35寫道： > > On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote: > > Add PCIe host controller DT bindings of SiFive FU740. > > > > Signed-off-by: Greentime Hu > > --- > > .../bindings/pci/sifive,fu740-pcie.yaml

[PATCH v2 0/6] Add SiFive FU740 PCIe host controller driver support

efine code logic to remove possible infinite loop - Replace magic number with meaningful define - Remove fu740_pcie_pm_ops - Use builtin_platform_driver Greentime Hu (5): clk: sifive: Add pcie_aux clock in prci driver for PCIe driver clk: sifive: Use reset-simple in prci driver for P

[PATCH v2 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver

Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S

[PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Signed-off-by: Greentime Hu --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920..d0839739b425 100644 --- a/arch/riscv

[PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git

[PATCH v2 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver

-by: Greentime Hu Signed-off-by: Greentime Hu --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 3 files changed, 334 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie

[PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Reviewed-by: Philipp Zabel Signed-off-by: Greentime Hu --- drivers/clk/sifive/Kconfig | 2 ++ drivers

[PATCH v2 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu --- drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740-prci.h | 2

Re: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

Philipp Zabel 於 2021年3月4日 週四 下午7:58寫道： > > On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote: > > We use reset-simple in this patch so that pcie driver can use > > devm_reset_control_get() to get this reset data structure and use > > reset_control_deassert() to deas

[RFC PATCH 5/6] PCI: designware: Add SiFive FU740 PCIe host controller driver

From: Paul Walmsley Add driver for the SiFive FU740 PCIe host controller. This controller is based on the DesignWare PCIe core. Co-developed-by: Henry Styles Signed-off-by: Henry Styles Co-developed-by: Erik Danie Signed-off-by: Erik Danie Co-developed-by: Greentime Hu Signed-off

[RFC PATCH 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Signed-off-by: Greentime Hu --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920..d0839739b425 100644 --- a/arch/riscv

[RFC PATCH 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller

Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git

[RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c

[RFC PATCH 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver

Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S

[RFC PATCH 0/6] Add SiFive FU740 PCIe host controller driver support

This patchset includes SiFive FU740 PCIe host controller driver. We also add pcie_aux clock and pcie_power_on_reset controller to prci driver for PCIe driver to use it. This is tested with e1000e: Intel(R) PRO/1000 Network Card and SP M.2 PCIe Gen 3 SSD in SiFive Unmatched. Greentime Hu (5

[RFC PATCH 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu --- drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740-prci.h | 2

[GIT PULL] nds32 patches for 5.12-rc1

Hi Linus Please pull the arch/nds32 updates for v5.12-rc1. Thank you. The following changes since commit f40ddce88593482919761f74910f42f4b84c004b: Linux 5.11 (2021-02-14 14:32:24 -0800) are available in the Git repository at:

Re: [PATCH 2/2] nds32: use get_kernel_nofault in dump_mem

t; not short-term dependencies on them. > > > > It seems like these patches are still sitting in linux-next and never > > made it to Linus/ > > ping? Sorry for late. Acked-by: Greentime Hu

Re: [PATCH v3 0/5] Improve kernel section protections

iscv/kernel/setup.c | 19 +++-- > arch/riscv/kernel/vmlinux.lds.S | 63 +++++---- > arch/riscv/mm/init.c| 21 +++--- > arch/riscv/mm/pageattr.c| 6 +++ > 7 files changed, 80 insertions(+), 36 deletions(-) > Test this series in v5.10-rc3 in Qemu and it works. Tested-by: Greentime Hu Thank you. :)

Re: [PATCH v3] gpio: sifive: To get gpio irq offset from device tree data

Bartosz Golaszewski 於 2020年11月13日 週五 下午5:00寫道： > > On Fri, Nov 13, 2020 at 3:34 AM Greentime Hu wrote: > > > > We can get hwirq number of the gpio by its irq_data->hwirq so that we don't > > need to add more macros for different platforms. This patch is tested in

[PATCH v3] gpio: sifive: To get gpio irq offset from device tree data

We can get hwirq number of the gpio by its irq_data->hwirq so that we don't need to add more macros for different platforms. This patch is tested in SiFive Unleashed board and SiFive Unmatched board. Signed-off-by: Greentime Hu --- drivers/gpio/gpio-sifive.c | 14 ++ 1 file chan

[PATCH] gpio: sifive: To get gpio irq offset from device tree data

We can get hwirq number of the gpio by its irq_data->hwirq so that we don't need to add more macros for different platforms. This patch is tested in SiFive Unleashed board and SiFive Unmatched board. Signed-off-by: Greentime Hu --- drivers/gpio/gpio-sifive.c | 12 1 file changed

Re: [PATCH v8 1/7] RISC-V: Move DT mapping outof fixmap

Atish Patra 於 2020年9月18日 週五 上午6:37寫道： > > From: Anup Patel > > Currently, RISC-V reserves 1MB of fixmap memory for device tree. However, > it maps only single PMD (2MB) space for fixmap which leaves only < 1MB space > left for other kernel features such as early ioremap which requires fixmap >

Re: [RFC PATCH 1/1] gpio: sifive: To get gpio irq offset from device tree data

Andy Shevchenko 於 2020年11月6日 週五 下午5:25寫道： > > On Fri, Nov 6, 2020 at 4:59 AM Greentime Hu wrote: > > > > We can get hwirq number of the gpio by its irq_data->hwirq so that we don't > > need to add more macros for different platforms. This patch is tested in > >

[RFC PATCH 1/1] gpio: sifive: To get gpio irq offset from device tree data

We can get hwirq number of the gpio by its irq_data->hwirq so that we don't need to add more macros for different platforms. This patch is tested in SiFive Unleashed board and SiFive Unmatched board. Signed-off-by: Greentime Hu Reviewed-by: Yash Shah --- drivers/gpio/gpio-sifive.c |

[tip: irq/urgent] irqchip/sifive-plic: Fix broken irq_set_affinity() callback

The following commit has been merged into the irq/urgent branch of tip: Commit-ID: a7480c5d725c4ecfc627e70960f249c34f5d13e8 Gitweb: https://git.kernel.org/tip/a7480c5d725c4ecfc627e70960f249c34f5d13e8 Author:Greentime Hu AuthorDate:Tue, 20 Oct 2020 16:15:32 +08:00

[tip: irq/urgent] irqchip/sifive-plic: Fix chip_data access within a hierarchy

The following commit has been merged into the irq/urgent branch of tip: Commit-ID: f9ac7bbd6e4540dcc6df621b9c9b6eb2e26ded1d Gitweb: https://git.kernel.org/tip/f9ac7bbd6e4540dcc6df621b9c9b6eb2e26ded1d Author:Greentime Hu AuthorDate:Thu, 29 Oct 2020 10:37:38 +08:00

[RFC PATCH] irqchip/sifive-plic: Fix getting wrong chip_data when interrupt is hierarchy

tiple PLICs") Signed-off-by: Greentime Hu --- drivers/irqchip/irq-sifive-plic.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 4048657ece0a..6f432d2a5ceb 100644 --- a/drivers/irqchip/i

[PATCH] irqchip/sifive-plic: Fix broken irq_set_affinity() callback

: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow") Signed-off-by: Greentime Hu --- drivers/irqchip/irq-sifive-plic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index eaa3e9fe54e9..4048657ec

Re: [PATCH 4/5] RISC-V: Protect .init.text & .init.data

Atish Patra 於 2020年10月13日 週二 上午9:28寫道： > > On Mon, Oct 12, 2020 at 4:26 PM Atish Patra wrote: > > > > On Mon, Oct 12, 2020 at 6:15 AM Greentime Hu > > wrote: > > > > > > Atish Patra 於 2020年10月10日 週六 上午5:13寫道： > > > > > > >

[PATCH 1/2] irqchip/sifive-plic: Enable or disable interrupt based on its previous setting

: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow") Signed-off-by: Greentime Hu --- drivers/irqchip/irq-sifive-plic.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index eaa3e9fe54e9..4c

[PATCH 2/2] irqchip/sifive-plic: Fix the interrupt was enabled accidentally issue.

can be fixed. Signed-off-by: Greentime Hu --- drivers/irqchip/irq-sifive-plic.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 4cc8a2657a6d..8a673d9cff69 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/dr

Re: [PATCH 4/5] RISC-V: Protect .init.text & .init.data

Atish Patra 於 2020年10月10日 週六 上午5:13寫道： > > Currently, .init.text & .init.data are intermixed which makes it impossible > apply different permissions to them. .init.data shouldn't need exec > permissions while .init.text shouldn't have write permission. > > Keep them in separate sections so that

Re: [PATCH] riscv: Add sfence.vma after page table changed

Palmer Dabbelt 於 2020年8月5日 週三 上午10:03寫道： > > On Mon, 03 Aug 2020 20:29:32 PDT (-0700), a...@brainfault.org wrote: > > On Tue, Aug 4, 2020 at 8:32 AM Greentime Hu wrote: > >> > >> This patch addes local_flush_tlb_page(addr) to use sfence.vma after the > >

Re: [RFC/RFT PATCH v2 3/5] riscv: Separate memory init from paging init

void __init paging_init(void) > { > setup_vm_final(); > - sparse_init(); > setup_zero_page(); > +} > + > +void __init misc_mem_init(void) > +{ > + sparse_init(); > zone_sizes_init(); > resource_init(); > } Thank you, Atish. Reviewed-by: Greentime Hu

[RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S

It should use the same logic here in both m-mode and s-mode. Signed-off-by: Greentime Hu --- arch/riscv/kernel/vector.S | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S index 4c880b1c32aa..4f0c5a166e4e 100644

[RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector

This patch replacees 2 instructions with 1 instruction to do the same thing . rs1=x0 with rd != x0 is a special form of the instruction that sets vl to MAXVL. Suggested-by: Andrew Waterman Signed-off-by: Greentime Hu --- arch/riscv/kernel/vector.S | 9 +++-- 1 file changed, 3 insertions

[RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread()

It allocates memory space for vector registers in start_thread() instead of allocating in vstate_restore() in this patch. We can allocate memory here so that it will be more readable. Signed-off-by: Greentime Hu Signed-off-by: Vincent Chen --- arch/riscv/include/asm/switch_to.h | 7

[RFC PATCH v7 18/21] riscv: Optimize vector registers initialization

This patch optimizes the initialization or invalidation of vector registers. It can reduce the code sizes of vector_flush_cpu_state() and reset_regs(). Signed-off-by: Greentime Hu Signed-off-by: Han-Kuan Chen --- arch/riscv/kernel/head.S | 30 +--- arch/riscv

[RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first

It triggered an illegal instruction exception when accessing vlenb CSR without enable vector first. To fix this issue, we should enable vector before using it and disable vector after using it. Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h| 2 ++ arch/riscv/kernel

[RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation

: 8regs (2911.000 MB/sec) Signed-off-by: Han-Kuan Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/xor.h | 74 arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 3 files changed, 156 insertions

[RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally

It may cause an illegal instruction exception if it doesn't use vsetvli before vmv.v.i v0, 0. Signed-off-by: Han-Kuan Chen Signed-off-by: Greentime Hu --- arch/riscv/kernel/head.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index

[RFC PATCH v7 14/21] riscv: Add support for kernel mode vector

Add containing kernel_rvv_begin()/kernel_rvv_end() function declarations and corresponding definitions in kernel_mode_vector.c These are needed to wrap uses of vector in kernel mode. Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h| 16 +++ arch/riscv/kernel/Makefile

[RFC PATCH v7 11/21] riscv: Add ptrace vector support

ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. [guo...@linux.alibaba.com: Add the first version porting to support vector of ptrace] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/ptrace.h | 18

[RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv

From: Vincent Chen The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the

[RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions

...@linux.alibaba.com: first version vector porting] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 13 + arch/riscv/kernel/asm-offsets.c | 8 3 files changed, 22 insertions(+) diff --git

[RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector

in the signal handler stack. [guo...@linux.alibaba.com: add the first porting for vector signal and sigcontext support] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/sigcontext.h | 2 + arch/riscv/kernel/signal.c | 92

[RFC PATCH v7 10/21] riscv: Add task switch support for vector

, xlen and code refine] [vincent.c...@sifive.co: Fix the might_sleep issue in vstate_save, vstate_restore] Signed-off-by: Nick Knight Signed-off-by: Greentime Hu Signed-off-by: Guo Ren Signed-off-by: Vincent Chen --- arch/riscv/include/asm/switch_to.h | 1 + 1 file changed, 1 insertion(+) diff

[RFC PATCH v7 09/21] riscv: Add task switch support for vector

, xlen and code refine] [vincent.c...@sifive.co: Fix the might_sleep issue in vstate_save, vstate_restore] Signed-off-by: Nick Knight Signed-off-by: Greentime Hu Signed-off-by: Guo Ren Signed-off-by: Vincent Chen --- arch/riscv/include/asm/switch_to.h | 65 +++ arch/riscv/kernel

[RFC PATCH v7 07/21] riscv: Reset vector register

From: Guo Ren Reset vector registers at boot-time and disable vector instructions execution for kernel mode. [greentime...@sifive.com: add comments] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/entry.S | 6 ++--- arch/riscv/kernel/head.S | 49

[RFC PATCH v7 05/21] riscv: Add vector feature to compile

From: Guo Ren This patch adds a new config option which could enable assembler's vector feature. Signed-off-by: Guo Ren Reviewed-by: Greentime Hu --- arch/riscv/Kconfig | 9 + arch/riscv/Makefile | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv

[RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features.

This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guo...@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren

[RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension

Follow the riscv vector spec to add new csr numbers. [guo...@linux.alibaba.com: first porting for new vector related csr] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren Acked-by: Guo Ren --- arch/riscv/include/asm/csr.h | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions

[RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension

From: Guo Ren Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it. Signed-off-by: Guo Ren Reviewed-by: Anup Patel Reviewed-by: Greentime Hu --- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cp

[RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags

From: Guo Ren From: Guo Ren Use "subst fd" in Makefile is a hack way and it's not convenient to add new ISA feature. Just separate them into riscv-march-cflags and riscv-march-aflags. Signed-off-by: Guo Ren --- arch/riscv/Makefile | 18 -- 1 file changed, 12 insertions(+), 6

[RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu

From: Guo Ren From: Guo Ren The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren Reviewed-by: Anup Patel Reviewed-by: Greentime Hu --- arch/riscv/include/asm/switch_to.h | 6

[RFC PATCH v7 00/21] riscv: Add vector ISA support

- Fixup typo "vecotr, fstate_save->vstate_save". - Fixup wrong saved registers' length in vector.S. - Seperate unrelated patches from this one. Greentime Hu (16): riscv: Extending cpufeature.c to detect V-extension riscv: Add new csr defines related to vector extension riscv: A

Re: [PATCH] arch: vdso: add vdso linker script to 'targets' instead of extra-y

le > @@ -25,7 +25,7 @@ $(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = > $(KBUILD_CFLAGS_64) > $(targets:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_64) > > obj-y += vdso64_wrapper.o > -extra-y += vdso64.lds > +targets += vdso64.lds > CPPFLAGS_vdso64.lds += -P -C -U$(ARCH) > > # Disable gcov profiling, ubsan and kasan for VDSO code For nds32: Acked-by: Greentime Hu

Re: [PATCH v2 12/23] nds32: use asm-generic/mmu_context.h for no-op implementations

Nicholas Piggin 於 2020年8月26日 週三 下午10:53寫道： > > Cc: Nick Hu > Cc: Greentime Hu > Cc: Vincent Chen > Signed-off-by: Nicholas Piggin > --- > arch/nds32/include/asm/mmu_context.h | 10 ++ > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff

Re: [PATCH] nds32: Fix bogus reference to

> + * which is defined above > */ > static const char *hwcap_str[] = { > "mfusr_pc", Thank you, Geert. Acked-by: Greentime Hu I'll put it in the next branch.

[PATCH] riscv: Add sfence.vma after page table changed

fixed mappings") Reported-by: Syven Wang Signed-off-by: Syven Wang Signed-off-by: Greentime Hu --- arch/riscv/mm/init.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index f4adb3684f3d..29b0f7108054 100644 --- a/arch/riscv

Re: [PATCH 5/6] uaccess: add force_uaccess_{begin,end} helpers

6) & 0x, regs); > else > ret = do_32(inst, regs); > - set_fs(seg); > + force_uaccess_end(seg); > > return ret; > } Hi Christoph, Thank you. Acked-by: Greentime Hu

Re: [PATCH 4/6] uaccess: remove segment_eq

.h > @@ -44,7 +44,7 @@ static inline void set_fs(mm_segment_t fs) > current_thread_info()->addr_limit = fs; > } > > -#define segment_eq(a, b) ((a) == (b)) > +#define uaccess_kernel() (get_fs() == KERNEL_DS) > > #define __range_ok(addr, size) (size <= get_fs() && addr <= (get_fs() -size)) > Hi Christoph, Thank you. Acked-by: Greentime Hu

Re: [PATCH 2/6] nds32: use uaccess_kernel in show_regs

>uregs[1], > regs->uregs[0]); > pr_info(" IRQs o%s Segment %s\n", > interrupts_enabled(regs) ? "n" : "ff", > - segment_eq(get_fs(), KERNEL_DS)? "kernel" : "user"); > + uaccess_kernel() ? "kernel" : "user"); > } > > EXPORT_SYMBOL(show_regs); Hi Christoph, Thank you. Acked-by: Greentime Hu

[PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

, then it can use t0 and s1 to do and operation. Reported-by: kernel test robot Signed-off-by: Greentime Hu --- arch/riscv/kernel/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 6ed579fc1073..000984695cd6 100644

[PATCH 2/2] riscv: Simplify the checking for SR_PP

This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the code flow for both m-mode and s-mode then we can remove the ifdef here. Signed-off-by: Greentime Hu --- arch/riscv/kernel/entry.S | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/riscv

Re: [PATCH v2 2/2] riscv: Enable context tracking

hrtimer=2eda5fab function=tick_sched_timer now=604180133400 > > user_loop-273 [001] d..1 604.189050: tick_stop: success=1 > > dependency=NONE > > user_loop-273 [001] d..2 614.251386: sched_switch: prev_comm=user_loop > > prev_pid=273 prev_prio=120 prev_sta

Re: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive

OK 999 MHz OK 700 MHz OK 350 MHz .... OK Overall result : PASSED Tested-by: Greentime Hu

Re: [PATCH 2/2] riscv: Enable context tracking

guoren 於 2020年6月27日 週六 上午12:29寫道： > > Hi Greentime, > > On 2020/6/23 9:28 下午, Greentime Hu wrote: > > This patch implements and enables context tracking for riscv (which is a > > prerequisite for CONFIG_NO_HZ_FULL support) > > > > It adds checking for

Re: [PATCH 12/26] mm/nds32: Use general page fault accounting

page fault retries, by > moving it before taking mmap_sem. > > CC: Nick Hu > CC: Greentime Hu > CC: Vincent Chen > Signed-off-by: Peter Xu > --- > arch/nds32/mm/fault.c | 19 +++ > 1 file changed, 3 insertions(+), 16 deletions(-) > > diff --git a/ar

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