Re: [PATCH] PCI: mediatek: get optional clock by devm_clk_get_optional()

slot); > - port->pipe_ck = devm_clk_get(dev, name); > - if (IS_ERR(port->pipe_ck)) { > - if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER) > - return -EPROBE_DEFER; > - > - port->pipe_ck = NULL; > - }

Re: [PATCH 7/8] PCI: mediatek: fix a leaked reference by adding missing of_node_put

ct mtk_pcie_port > *port, > > port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, >_domain_ops, port); > + of_node_put(pcie_intc_node); > if (!port->irq_domain) { > dev_err(dev, "failed to get INTx IRQ domain\n"); > return -ENODEV; Thanks for fix this. Acked-by: Honghui Zhang

Re: [PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

On Thu, 2019-02-28 at 17:42 +, Lorenzo Pieralisi wrote: > On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The PCIE_AXI_WINDOW0 defines the translate window size for the request > > from EP side. Req

Re: [RFC PATCH] PCI/portdrv: Support for subtractive decode bridge

On Thu, 2019-02-07 at 13:52 -0600, Bjorn Helgaas wrote: > On Thu, Feb 07, 2019 at 09:18:16AM -0600, Bjorn Helgaas wrote: > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > The Class Code for

Re: [RFC PATCH] PCI/portdrv: Support for subtractive decode bridge

On Thu, 2019-02-07 at 09:18 -0600, Bjorn Helgaas wrote: > Hi Honghui, > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > cha

Re: [PATCH v2 1/2] PCI: mediatek: Use resource_size function on resource object

On Thu, 2019-01-31 at 15:36 -0600, Bjorn Helgaas wrote: > On Thu, Jan 31, 2019 at 04:01:52PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > scripts/coccinelle/api/resource_size.cocci complain about the > > following warning: > > >

Re: [v1] PCI: mediatek: Remove MSI inner domain

On Tue, 2019-01-22 at 17:37 +0800, Jianjun Wang wrote: > There is no need to create the inner domain as a parent for MSI domian, > some feature has been implemented by MSI framework. > > Remove the inner domain and its irq chip, it will be more closer to > hardware implementation. > Hi, jianjun,

Re: [PATCH] PCI: Mediatek: Use resource_size function on resource object

On Thu, 2019-01-31 at 11:03 +0800, Honghui Zhang wrote: > On Wed, 2019-01-30 at 09:49 -0600, Bjorn Helgaas wrote: > > On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > drivers/pci/pcie-mediatek.c

Re: [PATCH] PCI: Mediatek: Use resource_size function on resource object

On Wed, 2019-01-30 at 09:49 -0600, Bjorn Helgaas wrote: > On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code. > > resource_size is maybe missing

Re: [PATCH] PCI: Mediatek: Use resource_size function on resource object

t; > wrote: > > > > From: Honghui Zhang > > > > > > > > drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code. > > > > resource_size is maybe missing with mem > > > > > > > > Generated by: scripts/coccinelle/api/

Re: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629

On Fri, 2018-12-07 at 20:56 +0800, Jianjun Wang wrote: > On Thu, 2018-12-06 at 13:53 +0800, Honghui Zhang wrote: > > On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote: > > > MT7629 is an arm platform SoC which has the same PCIe IP with MT7622. > > > > > > T

Re: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629

On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote: > MT7629 is an arm platform SoC which has the same PCIe IP with MT7622. > > The read value of BAR0 is 0x_, it's size will be calculated as 4GB > in arm64 but bogus alignment values at arm32, the pcie device and devices :s /the pcie

Re: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629

On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote: > MT7629 is an arm platform SoC which has the same PCIe IP with MT7622. > > The read value of BAR0 is 0x_, it's size will be calculated as 4GB > in arm64 but bogus alignment values at arm32, the pcie device and devices :s /the pcie

Re: [PATCH v2] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Thu, 2018-11-29 at 11:33 +, Lorenzo Pieralisi wrote: > On Thu, Nov 08, 2018 at 10:56:55AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. >

Re: [PATCH v2] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Thu, 2018-11-29 at 11:33 +, Lorenzo Pieralisi wrote: > On Thu, Nov 08, 2018 at 10:56:55AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. >

Re: [PATCH] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Wed, 2018-11-07 at 12:03 +, Lorenzo Pieralisi wrote: > On Thu, Oct 18, 2018 at 11:23:34AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. >

Re: [PATCH] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Wed, 2018-11-07 at 12:03 +, Lorenzo Pieralisi wrote: > On Thu, Oct 18, 2018 at 11:23:34AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. >

Re: [PATCH] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Fri, 2018-11-02 at 14:36 +0800, Ryder Lee wrote: > On Thu, 2018-10-18 at 11:23 +0800, Honghui Zhang (张洪辉) wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. > >

Re: [PATCH] PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT

On Fri, 2018-11-02 at 14:36 +0800, Ryder Lee wrote: > On Thu, 2018-10-18 at 11:23 +0800, Honghui Zhang (张洪辉) wrote: > > From: Honghui Zhang > > > > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF > > DT parser. > >

Re: [PATCH v8 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support

On Wed, 2018-10-17 at 16:19 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 15, 2018 at 04:08:51PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > This patchset includes misc patchs: > > > > The patch 1 fixup the mtk_pcie_find_port logic

Re: [PATCH v8 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support

On Wed, 2018-10-17 at 16:19 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 15, 2018 at 04:08:51PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > This patchset includes misc patchs: > > > > The patch 1 fixup the mtk_pcie_find_port logic

Re: [PATCH v9 2/9] PCI: Using PCI configuration space header type instead of class type to assign resource

On Wed, 2018-10-17 at 08:22 -0500, Bjorn Helgaas wrote: > On Tue, Oct 16, 2018 at 03:53:55PM +0100, Lorenzo Pieralisi wrote: > > On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > The PCI con

Re: [PATCH v9 2/9] PCI: Using PCI configuration space header type instead of class type to assign resource

On Wed, 2018-10-17 at 08:22 -0500, Bjorn Helgaas wrote: > On Tue, Oct 16, 2018 at 03:53:55PM +0100, Lorenzo Pieralisi wrote: > > On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > The PCI con

Re: [PATCH v7 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support

On Mon, 2018-10-15 at 14:05 +0800, Ryder Lee wrote: > On Mon, 2018-10-15 at 13:44 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > This patchset includes misc patchs: > > > > The patch 1 fixup the mtk_pcie_find_port logic which will

Re: [PATCH v7 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support

On Mon, 2018-10-15 at 14:05 +0800, Ryder Lee wrote: > On Mon, 2018-10-15 at 13:44 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > This patchset includes misc patchs: > > > > The patch 1 fixup the mtk_pcie_find_port logic which will

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Fri, 2018-10-12 at 09:12 -0500, Bjorn Helgaas wrote: > On Fri, Oct 12, 2018 at 11:22:30AM +0100, Lorenzo Pieralisi wrote: > > On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote: > >> On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > >>> On T

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Fri, 2018-10-12 at 09:12 -0500, Bjorn Helgaas wrote: > On Fri, Oct 12, 2018 at 11:22:30AM +0100, Lorenzo Pieralisi wrote: > > On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote: > >> On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > >>> On T

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Fri, 2018-10-12 at 11:22 +0100, Lorenzo Pieralisi wrote: > On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote: > > On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > > > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote: > > > &g

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Fri, 2018-10-12 at 11:22 +0100, Lorenzo Pieralisi wrote: > On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote: > > On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > > > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote: > > > &g

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote: > > On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote: > > > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com > &g

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote: > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote: > > On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote: > > > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com > &g

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The PCIe controller of MT7622 has TYPE 1 configuration space type, but > > the HW default c

Re: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI

On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The PCIe controller of MT7622 has TYPE 1 configuration space type, but > > the HW default c

Re: [PATCH v6 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, module support

On Mon, 2018-10-08 at 12:31 -0500, Bjorn Helgaas wrote: > On Mon, Oct 08, 2018 at 11:24:39AM +0800, honghui.zh...@mediatek.com wrote: > > > Honghui Zhang (9): > > PCI: mediatek: Using slot's devfn for compare to fix > > mtk_pcie_find_port logic > > PCI: media

Re: [PATCH v6 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, module support

On Mon, 2018-10-08 at 12:31 -0500, Bjorn Helgaas wrote: > On Mon, Oct 08, 2018 at 11:24:39AM +0800, honghui.zh...@mediatek.com wrote: > > > Honghui Zhang (9): > > PCI: mediatek: Using slot's devfn for compare to fix > > mtk_pcie_find_port logic > > PCI: media

Re: [PATCH v5 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic

On Tue, 2018-10-02 at 11:59 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 01, 2018 at 03:36:41PM +0100, Lorenzo Pieralisi wrote: > > On Fri, Sep 28, 2018 at 06:04:32PM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > The Medi

Re: [PATCH v5 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic

On Tue, 2018-10-02 at 11:59 +0100, Lorenzo Pieralisi wrote: > On Mon, Oct 01, 2018 at 03:36:41PM +0100, Lorenzo Pieralisi wrote: > > On Fri, Sep 28, 2018 at 06:04:32PM +0800, honghui.zh...@mediatek.com wrote: > > > From: Honghui Zhang > > > > > > The Medi

Re: [PATCH v5 4/9] PCI: mediatek: Convert to use pci_host_probe()

On Fri, 2018-09-28 at 23:41 +0800, Ryder Lee wrote: > On Fri, 2018-09-28 at 18:04 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Part of mtk_pcie_register_host is an open-coded version of > > pci_host_probe(). So instead of duplicating this c

Re: [PATCH v5 4/9] PCI: mediatek: Convert to use pci_host_probe()

On Fri, 2018-09-28 at 23:41 +0800, Ryder Lee wrote: > On Fri, 2018-09-28 at 18:04 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Part of mtk_pcie_register_host is an open-coded version of > > pci_host_probe(). So instead of duplicating this c

Re: [PATCH v4 2/4] PCI: mediatek: enable msi after clock enabled

On Fri, 2018-09-21 at 17:46 +0100, Lorenzo Pieralisi wrote: > On Mon, Sep 10, 2018 at 05:50:21PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The clocks was not enabled when enable MSI. This patch fix this > > issue by

Re: [PATCH v4 2/4] PCI: mediatek: enable msi after clock enabled

On Fri, 2018-09-21 at 17:46 +0100, Lorenzo Pieralisi wrote: > On Mon, Sep 10, 2018 at 05:50:21PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The clocks was not enabled when enable MSI. This patch fix this > > issue by

Re: [PATCH v4 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Fri, 2018-09-21 at 17:07 +0100, Lorenzo Pieralisi wrote: > On Mon, Sep 10, 2018 at 05:50:20PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The Mediatek's host controller has two slots, each with it's own control > > registers. The host dr

Re: [PATCH v4 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Fri, 2018-09-21 at 17:07 +0100, Lorenzo Pieralisi wrote: > On Mon, Sep 10, 2018 at 05:50:20PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The Mediatek's host controller has two slots, each with it's own control > > registers. The host dr

Re: [PATCH v3 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Wed, 2018-07-18 at 10:49 +0100, Lorenzo Pieralisi wrote: > On Wed, Jul 18, 2018 at 02:02:41PM +0800, Honghui Zhang wrote: > > > > > > > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) > > > > +{ > > > > +

Re: [PATCH v3 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Wed, 2018-07-18 at 10:49 +0100, Lorenzo Pieralisi wrote: > On Wed, Jul 18, 2018 at 02:02:41PM +0800, Honghui Zhang wrote: > > > > > > > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) > > > > +{ > > > > +

Re: [PATCH] PCI: mediatek: Fix unchecked return value

gt; Signed-off-by: Gustavo A. R. Silva > --- > drivers/pci/controller/pcie-mediatek.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Hi, Gustavo, thanks for your help. Acked-by: Honghui Zhang > diff --git a/drivers/pci/controller/pcie-mediatek.c > b/drivers/pci/co

Re: [PATCH] PCI: mediatek: Fix unchecked return value

gt; Signed-off-by: Gustavo A. R. Silva > --- > drivers/pci/controller/pcie-mediatek.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Hi, Gustavo, thanks for your help. Acked-by: Honghui Zhang > diff --git a/drivers/pci/controller/pcie-mediatek.c > b/drivers/pci/co

Re: [PATCH v3 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Tue, 2018-07-17 at 18:15 +0100, Lorenzo Pieralisi wrote: > [+Rafael, Kevin, Ulf] > > On Mon, Jul 02, 2018 at 03:57:43PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when

Re: [PATCH v3 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Tue, 2018-07-17 at 18:15 +0100, Lorenzo Pieralisi wrote: > [+Rafael, Kevin, Ulf] > > On Mon, Jul 02, 2018 at 03:57:43PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when

Re: [PATCH v3 0/4] PCI: mediatek: fixup find_port, enable_msi and add pm, module support

Hi, Bjorn, Lorenzo, could you kindly take a look at this serial? thanks. On Mon, 2018-07-02 at 15:57 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang > > This patchset includes misc patchs: > > The first patch fixup the mtk_pcie_find_port logical which will cause

Re: [PATCH v3 0/4] PCI: mediatek: fixup find_port, enable_msi and add pm, module support

Hi, Bjorn, Lorenzo, could you kindly take a look at this serial? thanks. On Mon, 2018-07-02 at 15:57 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang > > This patchset includes misc patchs: > > The first patch fixup the mtk_pcie_find_port logical which will cause

Re: [PATCH 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Thu, 2018-06-28 at 08:07 -0500, Bjorn Helgaas wrote: > On Wed, Jun 27, 2018 at 05:21:35PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Mediatek's host controller have two slots, each have it's own control > > registers. The host driver

Re: [PATCH 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Thu, 2018-06-28 at 08:07 -0500, Bjorn Helgaas wrote: > On Wed, Jun 27, 2018 at 05:21:35PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Mediatek's host controller have two slots, each have it's own control > > registers. The host driver

Re: [PATCH 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Wed, 2018-06-27 at 19:45 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system > > suspend, and all the internal control register will be re

Re: [PATCH 3/4] PCI: mediatek: Add system pm support for MT2712 and MT7622

On Wed, 2018-06-27 at 19:45 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system > > suspend, and all the internal control register will be re

Re: [PATCH 4/4] PCI: mediatek: Add loadable kernel module support

On Wed, 2018-06-27 at 19:39 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > Implement remove callback function for Mediatek PCIe driver to add > > loadable kernel module support. > > > +static void m

Re: [PATCH 4/4] PCI: mediatek: Add loadable kernel module support

On Wed, 2018-06-27 at 19:39 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > Implement remove callback function for Mediatek PCIe driver to add > > loadable kernel module support. > > > +static void m

Re: [PATCH 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Wed, 2018-06-27 at 19:35 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > Mediatek's host controller have two slots, each have it's own control > > registers. The host driver need to identify which slot

Re: [PATCH 1/4] PCI: mediatek: fixup mtk_pcie_find_port logical

On Wed, 2018-06-27 at 19:35 +0300, Andy Shevchenko wrote: > On Wed, Jun 27, 2018 at 12:21 PM, wrote: > > From: Honghui Zhang > > > > Mediatek's host controller have two slots, each have it's own control > > registers. The host driver need to identify which slot

Re: [PATCH v3] PCI: mediatek: Add system pm support for MT2712

On Fri, 2018-06-01 at 13:52 +0300, Andy Shevchenko wrote: > On Fri, Jun 1, 2018 at 1:49 PM, Honghui Zhang > wrote: > > On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote: > >> On Fri, Jun 1, 2018 at 6:04 AM, wrote: > >> > From: Honghui Zhang &g

Re: [PATCH v3] PCI: mediatek: Add system pm support for MT2712

On Fri, 2018-06-01 at 13:52 +0300, Andy Shevchenko wrote: > On Fri, Jun 1, 2018 at 1:49 PM, Honghui Zhang > wrote: > > On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote: > >> On Fri, Jun 1, 2018 at 6:04 AM, wrote: > >> > From: Honghui Zhang &g

Re: [PATCH v3] PCI: mediatek: Add system pm support for MT2712

On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote: > On Fri, Jun 1, 2018 at 6:04 AM, wrote: > > From: Honghui Zhang > > > +#ifdef CONFIG_PM_SLEEP > > +static int mtk_pcie_suspend_noirq(struct device *dev) > > __maybe_unused > Hi, Andy, thanks for your

Re: [PATCH v3] PCI: mediatek: Add system pm support for MT2712

On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote: > On Fri, Jun 1, 2018 at 6:04 AM, wrote: > > From: Honghui Zhang > > > +#ifdef CONFIG_PM_SLEEP > > +static int mtk_pcie_suspend_noirq(struct device *dev) > > __maybe_unused > Hi, Andy, thanks for your

Re: [PATCH] PCI: mediatek: Add system pm support for MT2712

On Wed, 2018-05-30 at 23:20 -0500, Bjorn Helgaas wrote: > On Wed, May 30, 2018 at 10:35:36AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all > > the internel control r

Re: [PATCH] PCI: mediatek: Add system pm support for MT2712

On Wed, 2018-05-30 at 23:20 -0500, Bjorn Helgaas wrote: > On Wed, May 30, 2018 at 10:35:36AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all > > the internel control r

Re: [PATCH] PCI: mediatek: Add system pm support for MT2712

On Thu, 2018-05-31 at 10:05 +0800, Ryder Lee wrote: > On Wed, 2018-05-30 at 10:35 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all > > the internel control register

Re: [PATCH] PCI: mediatek: Add system pm support for MT2712

On Thu, 2018-05-31 at 10:05 +0800, Ryder Lee wrote: > On Wed, 2018-05-30 at 10:35 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all > > the internel control register

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Thu, 2018-05-03 at 14:05 +0100, Marc Zyngier wrote: > On 03/05/18 10:41, Honghui Zhang wrote: > > On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote: > >> On 02/05/18 10:41, Honghui Zhang wrote: > >>> On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > &

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Thu, 2018-05-03 at 14:05 +0100, Marc Zyngier wrote: > On 03/05/18 10:41, Honghui Zhang wrote: > > On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote: > >> On 02/05/18 10:41, Honghui Zhang wrote: > >>> On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > &

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote: > On 02/05/18 10:41, Honghui Zhang wrote: > > On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > >> Hi Zhang, > >> > >> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote: > >>>

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote: > On 02/05/18 10:41, Honghui Zhang wrote: > > On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > >> Hi Zhang, > >> > >> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote: > >>> From: Ho

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > Hi Zhang, > > On 20/04/18 06:25, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > Using irq_chip solution to setup IRQs for the consistent with IRQ framework

Re: [PATCH 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle

On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote: > Hi Zhang, > > On 20/04/18 06:25, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Using irq_chip solution to setup IRQs for the consistent with IRQ framework. > > > > Signed-off-

Re: [PATCH v5 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry

On Thu, 2018-01-04 at 19:04 +, Marc Zyngier wrote: > On 04/01/18 18:40, Lorenzo Pieralisi wrote: > > [+Marc] > > > > On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.com wrote: > >> From: Honghui Zhang <honghui.zh...@mediatek.com> >

Re: [PATCH v5 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry

On Thu, 2018-01-04 at 19:04 +, Marc Zyngier wrote: > On 04/01/18 18:40, Lorenzo Pieralisi wrote: > > [+Marc] > > > > On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.com wrote: > >> From: Honghui Zhang > >> > >> There mayb

Re: [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Tue, 2018-01-02 at 10:56 +, Lorenzo Pieralisi wrote: > On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote: > > On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote: > > > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com > > > w

Re: [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Tue, 2018-01-02 at 10:56 +, Lorenzo Pieralisi wrote: > On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote: > > On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote: > > > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com > > > w

Re: [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote: > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > The hardware default value of IDs and class type is not correct, > &

Re: [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote: > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The hardware default value of IDs and class type is not correct, > > fix that by setup the cor

Re: [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Mon, 2017-12-25 at 18:27 +0800, Ryder Lee wrote: > On Fri, 2017-12-22 at 13:39 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > The hardware default value of IDs and class type is not correct, > > fix that b

Re: [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622

On Mon, 2017-12-25 at 18:27 +0800, Ryder Lee wrote: > On Fri, 2017-12-22 at 13:39 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The hardware default value of IDs and class type is not correct, > > fix that by setup the correct values befor

Re: [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622

On Thu, 2017-12-21 at 18:27 -0600, Bjorn Helgaas wrote: > On Thu, Dec 21, 2017 at 03:01:12PM +0800, Honghui Zhang wrote: > > On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote: > > > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote: > > > > F

Re: [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622

On Thu, 2017-12-21 at 18:27 -0600, Bjorn Helgaas wrote: > On Thu, Dec 21, 2017 at 03:01:12PM +0800, Honghui Zhang wrote: > > On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote: > > > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote: > >

Re: [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622

On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote: > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > The host bridge of MT7622 has hardware code the class code to an > >

Re: [PATCH v2 2/2] PCI: mediatek: Fixup class type for MT7622

On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote: > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > The host bridge of MT7622 has hardware code the class code to an > > arbitrary, meaningless value, fix that. >

Re: [PATCH v2 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code

On Thu, 2017-12-21 at 10:08 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang <honghui.zh...@mediatek.com> > > Two fixups for mediatek's host bridge: > The first patch fixup the IRQ handle routine to avoid IRQ reentry which > may exist for both MT2712 and MT762

Re: [PATCH v2 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code

On Thu, 2017-12-21 at 10:08 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang > > Two fixups for mediatek's host bridge: > The first patch fixup the IRQ handle routine to avoid IRQ reentry which > may exist for both MT2712 and MT7622. > The second patch fixup cla

Re: [PATCH] PCI: Mediatek: clear irq status after irq dispathed to avoid reentry

+0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > There maybe a same irq reentry scenario after irq received in current > > irq handle flow: > > EP device PCIe host driverEP driver > &g

Re: [PATCH] PCI: Mediatek: clear irq status after irq dispathed to avoid reentry

+0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > There maybe a same irq reentry scenario after irq received in current > > irq handle flow: > > EP device PCIe host driverEP driver > > 1. issue an ir

Re: [PATCH] PCI: mediatek: take use of PCI_NUM_INTX

On Wed, 2017-08-30 at 09:19 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang <honghui.zh...@mediatek.com> > > Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX > definition for the number of INTx interrupts. > > Signed-off-by: H

Re: [PATCH] PCI: mediatek: take use of PCI_NUM_INTX

On Wed, 2017-08-30 at 09:19 +0800, honghui.zh...@mediatek.com wrote: > From: Honghui Zhang > > Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX > definition for the number of INTx interrupts. > > Signed-off-by: Honghui Zhang > --- > drivers/pci/

Re: [RESEND PATCH 1/2] dt-bindings: i2c: Add MediaTek MT7622 i2c binding

On Fri, 2017-08-11 at 09:37 +0800, Jun Gao wrote: > On Thu, 2017-08-10 at 16:19 +0800, Honghui Zhang wrote: > > On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote: > > > From: Jun Gao <jun@mediatek.com> > > > > > > Add MT7622 i2c binding to binding fi

Re: [RESEND PATCH 1/2] dt-bindings: i2c: Add MediaTek MT7622 i2c binding

On Fri, 2017-08-11 at 09:37 +0800, Jun Gao wrote: > On Thu, 2017-08-10 at 16:19 +0800, Honghui Zhang wrote: > > On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote: > > > From: Jun Gao > > > > > > Add MT7622 i2c binding to binding file. Compare to MT8173 i2c >

Re: [RESEND PATCH 1/2] dt-bindings: i2c: Add MediaTek MT7622 i2c binding

On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote: > From: Jun Gao > > Add MT7622 i2c binding to binding file. Compare to MT8173 i2c > controller, MT7622 limits message numbers to 255, and does not > support 4GB DMA mode. > > Signed-off-by: Jun Gao >

Re: [RESEND PATCH 1/2] dt-bindings: i2c: Add MediaTek MT7622 i2c binding

On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote: > From: Jun Gao > > Add MT7622 i2c binding to binding file. Compare to MT8173 i2c > controller, MT7622 limits message numbers to 255, and does not > support 4GB DMA mode. > > Signed-off-by: Jun Gao > --- >

Re: [PATCH v2 4/5] PCI: mediatek: Add new generation controller support

On Tue, 2017-08-08 at 15:19 -0500, Bjorn Helgaas wrote: > On Fri, Aug 04, 2017 at 08:18:09AM -0500, Bjorn Helgaas wrote: > > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote: > > > On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote: > > > &

Re: [PATCH v2 4/5] PCI: mediatek: Add new generation controller support

On Tue, 2017-08-08 at 15:19 -0500, Bjorn Helgaas wrote: > On Fri, Aug 04, 2017 at 08:18:09AM -0500, Bjorn Helgaas wrote: > > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote: > > > On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote: > > > &

Re: [PATCH] memory: mtk-smi: Handle return value of clk_prepare_enable

g. And please send this one to Joerg and iommu mail list. otherwise: Acked-by: Honghui Zhang <honghui.zh...@mediatek.com> [1]https://lkml.org/lkml/2017/8/3/968 Thanks. > drivers/memory/mtk-smi.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drive

Re: [PATCH] memory: mtk-smi: Handle return value of clk_prepare_enable

rg and iommu mail list. otherwise: Acked-by: Honghui Zhang [1]https://lkml.org/lkml/2017/8/3/968 Thanks. > drivers/memory/mtk-smi.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > in

Re: [PATCH v3 5/6] PCI: mediatek: Add new generation controller support

On Sun, 2017-08-06 at 10:06 +0800, Ryder Lee wrote: > Hi Honghui, > > If you plan to send next version, then I would suggest some minor > changes. > > On Fri, 2017-08-04 at 20:06 +0800, honghui.zh...@mediatek.com wrote: > > +#define PCIE_CRSTB BIT(3) > > +#define PCIE_PERSTB

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