From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
adds USB host ports support.
Icenowy Zheng (5):
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
ARM: sun8i: v40: enable
sions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.
Add binding for this.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-
Currently the rtl8723bs driver will print "nolinked power save enter"
and "nolinked power save leave" per minute if it's not connected to any
network.
These messages are meaningless and annoying to regular users.
Hide them when it's not debugging.
Signed-off-b
The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).
Add the device tree node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
于 2017年10月10日 GMT+08:00 上午5:04:07, Maxime Ripard
写到:
>On Sun, Oct 08, 2017 at 04:29:03AM +0000, Icenowy Zheng wrote:
>> On newer revisions of the Banana Pi M2 Ultra boards, the 5V power
>output
>> (used by HDMI, SATA and USB) is controller via a GPIO.
>>
>>
于 2017年10月10日 GMT+08:00 上午5:03:40, Maxime Ripard
写到:
>On Sun, Oct 08, 2017 at 04:29:02AM +0000, Icenowy Zheng wrote:
>> From: Icenowy Zheng
>>
>> Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
>>
>> Add support for the host ports
于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard
写到:
>On Fri, Oct 06, 2017 at 06:33:31AM +0000, Icenowy Zheng wrote:
>> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration
>register,
>> which is intended to be accessed by the dwmac-sun8i driver. On SoCs
&
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20,
but with a reset control and two dedicated VDD pins for this controller
(one 1.2v and one 2.5v).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/ata/ahci_sunxi.c | 118
generic platform AHCI
controller binding document.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 -
.../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++
2 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arc
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
sions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
the two boards, and
the fifth and sixth patch finally adds USB host ports support.
Icenowy Zheng (6):
phy: sun4i-usb: add support for R40 USB PHY
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator for
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/allwinner/phy-sun4i-usb.c | 12
2 files changed, 13 insertions
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)"
写到:
>From: Icenowy Zheng
>
>[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ]
>
>As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA
>driver should be allowed to be built
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
>> 写到:
>>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Added 3.3V vqmmc regulator for mmc2 (eMMC).
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boo
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not use
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Dropped all max-frequency properties in MMC nodes.
Changes in v2
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
arch/arm/boot/dts/sun8i-r40.dtsi
As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.
Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
the syscon part, in the CCU of R40 SoC.
Export a regmap of the CCU.
Read access is not restricted to all registers, but only the GMAC
register is allowed to be written.
Signed-off-by: Icenowy Zheng
---
drivers/clk/
first patch does the conversion of the driver to a platform driver,
and the second patch adds the regmap.
Icenowy Zheng (2):
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: r40: export a regmap to access the GMAC register
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
写到:
>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>> >
>> >
>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo
>写到:
>> > >
于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>>
>> Add the device tree binding
-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
di
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values pro
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +0000, Icenowy Zheng wrote:
>> +&mmc2 {
>> +vmmc-supply = <®_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay"
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boo
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not use
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
arch/arm/boot/dts/sun8i-r40.dtsi
于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard
写到:
>On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:
>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Allwinner A64 SoC.
>>
>> As the thermal sensor driver is not yet implemented and some board
于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz
写到:
>Hi Icenowy,
>
>On 20/09/2017 17:18, Icenowy Zheng wrote:
>> AXP803 PMIC features AC/USB/Battery power supplies.
>>
>> As we have now the device tree bindings for them, add device tree
>> nodes for them.
&g
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-b
The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling
of the ARM cores on the A64 SoC.
Add this definition to enable it on Pine64.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch
driver of A64, and the remaining patches
set up the device tree bits of the DVFS on Pine64.
Icenowy Zheng (3):
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
arm64: allwinner: a64: add CPU opp table
arm64: allwinner: a64: set CPU regulator for Pine64
.../arm64/boot/dts/allwinner
Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.
OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64
于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron
写到:
>On Wed, 20 Sep 2017 23:18:07 +0800
>Icenowy Zheng wrote:
>
>> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power
>inputs:
>> AC, USB and Battery.
>>
>> This patchset adds support fo
AXP803 PMIC features AC/USB/Battery power supplies.
As we have now the device tree bindings for them, add device tree
nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot
d-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..955f392af6a2 100644
--- a/arch/
As we have now support for AXP803 ADC/Battery, and the AC Power part of
AXP803 is the same as AXP22x, add MFD cells for these drivers.
Signed-off-by: Icenowy Zheng
---
drivers/mfd/axp20x.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd
GPADC channels
are complex and will be support after more investigation.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 108 +++
1 file changed, 108 insertions(+)
diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
The AXP803 PMIC has battery support like other AXP PMICs, but with
different definition of max target charging voltage and constant
charging current.
Add support for AXP803 battery in axp20x-battery driver.
Signed-off-by: Icenowy Zheng
---
drivers/power/supply/axp20x_battery.c | 88
The ADC rate setup on AXP803 is more complex than AXP20x/22x.
As it's not a necessary setup, allow it to be skipped, to allow simpler
AXP803 support now.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --
AXP803 Battery/USB power supplies. For AC
power supply the one on AXP803 is compatible with the one on AXP22x.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 1 +
Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt | 1 +
2
patchset because it's not
present on Pine series boards.
In order to enable battery monitoring the ADC for battery is also enabled
for AXs.
In order to enable battery monitoring the ADC for battery is also enabled
for AXP803.
Icenowy Zheng (7):
dt-bindings: add compatibles for AXP803 Batter
于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote:
>> 在 2017-09-18 16:30，Maxime Ripard 写道：
>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
>> > > 于 2017年9月18日 GMT+08:00 下午3:3
于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote:
>> Allwinner A64/H5 SoCs come with a SID controller like the one in H3,
>but
>> without the silicon bug that makes the initial value at 0x200 wrong,
>so
>
Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but
without the silicon bug that makes the initial value at 0x200 wrong, so
the value at 0x200 can be directly read.
Add support for this kind of SID controller.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has
>its
>> register re-arranged, the clock divider moved to CCU (originally the
>>
readout register to be altered.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/sun4i-gpadc-iio.c | 123 +++---
1 file changed, 116 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 68926b986cd0
al sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Splitted out some code refactors.
- Code sequence changed back. (The gpadc_data went back to the start of
the source file)
drivers/iio/adc/sun4i-gpadc-
r has some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v4:
- Mention calibration data in commit message.
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.
arch/arm/boot/dts/sun8i-h3.dtsi
points are also not added yet.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3220da3ad790..687c6457d214 100644
--- a/arch/arm/boot/dts/sun8i-h3.
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen
SUN8I", not "SUN8I_A33".
Add "_A33" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v4:
- Change A23 to A33, as the driver never supports A23.
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux
ady merged.
Icenowy Zheng (6):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS
variants
iio: adc: sun4i-gpadc-iio: add supp
The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB
port, and the battery input is connected to a generic connector.
Enable these two power supplies in the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8
1 file changed
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4
1
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4
1 file changed, 4 insertions(+)
diff --g
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch
CCU device node for H3 SoC, and the skeleton
of the node enters the H3/H5 common DTSI; the H5 support is splited
into the third patch, as they will enter different tree.
The fourth patch finally adds simplefb nodes, using the
pipeline strings introduced in the first patch.
Icenowy Zheng (4):
dt
locks")
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 7a81c4885836..543c46d0e045 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-
The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.
Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Ice
for lock by adds CLK_SET_RATE_UNGATE
flag.
The second patch solves the problem that H3 GPU clock is not really tweaked
by add CLK_SET_RATE_PARENT flag to it.
Icenowy Zheng (2):
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
From: Icenowy Zheng
Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.
Add support for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
drivers/dma/sun6i
From: Icenowy Zheng
Originally we enable a special gate bit when the compatible indicates
A23/33.
But according to BSP sources and user manuals, more SoCs will need this
gate bit.
So make it a common quirk configured in the config struct.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu
This is a dedicated patchset of Allwinner V3s DMA support, which used
to be part of the audio codec support patchset.
It's a derivation of the DMA part of v3 of the codec patchset.
Icenowy Zheng (2):
dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk
dmaeng
于 2017年8月28日 GMT+08:00 下午8:16:44, Antony Antony 写到:
>On Fri, Aug 25, 2017 at 03:28:41PM +0200, Code Kipper wrote:
>> On 25 August 2017 at 12:32, Antony Antony wrote:
>
>> > +
>> > + brcmf: bcrmf@1 {
>> > + reg = <1>;
>> > + compatible = "brcm,bcm4329-fmac";
>>
于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard
写到:
>On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote:
>> +®_vcc5v0 {
>> +gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
>> +enable-active-high;
>> +};
>
>Same thing here, you'
于 2017年8月23日 GMT+08:00 上午4:10:43, Maxime Ripard
写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
>> form factor and position of variou
于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard
写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++
1
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181 ++
2 files
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Fix alphabetical orders.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch
The Allwinner V3s SoC is not quad-core, but single-core.
Fix this in the README file.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
di
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
di
From: Icenowy Zheng
Some RTL8211E chips have broken GbE function, which needs a hack to
fix. It's said that this fix will affect the performance on not-buggy
PHYs, so it should only be enabled on boards with the broken PHY.
Currently only some Pine64+ boards are known to have this issue.
From: Icenowy Zheng
The page select register also exists on RTL8211E PHY (although it
behaves slightly differently).
Change the register macro name to remove the F.
Signed-off-by: Icenowy Zheng
---
drivers/net/phy/realtek.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions
Some Pine64+ boards have a broken RTL8211E PHY, which cannot work
reliably in 1000Base-T mode with default configuration.
A solution is passed to Pine64, which is said to be disabling the
internal RX delay of the PHY.
Enable the hack by set the PHY mode to RGMII-TXID.
Signed-off-by: Icenowy
Some boards uses a PHY with internal delay with an Allwinner SoC.
Support these PHY modes in the driver.
As the driver has no configuration registers for these modes, just treat
them as ordinary RGMII.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3
RGMII variants' support to the dwmac-sun8i driver.
The second patch renames some macros in RTL PHY driver, and the third
patch introduces the hack as the "RGMII-TXID" mode of the PHY.
The fourth patch enables the hack in the device tree.
Icenowy Zheng (4):
net: stmmac: dwmac-sun8i:
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
di
于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai 写到:
>Hi,
>
>On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote:
>> When claiming SRAM, if the base is set to an error, it means that the
>> SRAM controller has been probed, but failed to remap the controller
>> memor
driver still has some problems to support the LCDs, the
real LCD device nodes are not added to the device tree files.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts | 49 ++
arch/arm
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" cl
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x
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