> On 06/20/2013 01:14 AM, Jay Agarwal wrote:
> > - decrease non-prefetch memory size to 128 MB
> > - increase prefetch memory size to 384 MB
> > - above change is done because most pcie devices
> > prefetch memory size requirement is quite higher
> > comp
- decrease non-prefetch memory size to 128 MB
- increase prefetch memory size to 384 MB
- above change is done because most pcie devices
prefetch memory size requirement is quite higher
compared to non-prefetch memory space.
Signed-off-by: Jay Agarwal
---
Patch is based on remotes
- decrease non-prefetch memory size to 128 MB
- increase prefetch memory size to 384 MB
- above change is done because most pcie devices
prefetch memory size requirement is quite higher
compared to non-prefetch memory space.
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based
On 06/20/2013 01:14 AM, Jay Agarwal wrote:
- decrease non-prefetch memory size to 128 MB
- increase prefetch memory size to 384 MB
- above change is done because most pcie devices
prefetch memory size requirement is quite higher
compared to non-prefetch memory space.
It's
+Stephen to suggest
> -Original Message-
> From: Jonghwan Choi [mailto:jhbird.c...@samsung.com]
> Sent: Wednesday, June 19, 2013 5:49 AM
> To: 'Jonghwan Choi'; linux-kernel@vger.kernel.org
> Cc: sta...@vger.kernel.org; Jay Agarwal
> Subject: [PATCH 3.9-stable] ARM: te
+Stephen to suggest
-Original Message-
From: Jonghwan Choi [mailto:jhbird.c...@samsung.com]
Sent: Wednesday, June 19, 2013 5:49 AM
To: 'Jonghwan Choi'; linux-kernel@vger.kernel.org
Cc: sta...@vger.kernel.org; Jay Agarwal
Subject: [PATCH 3.9-stable] ARM: tegra30: clocks: Fix pciex
> Quoting Stephen Warren (2013-06-04 12:08:08)
> > On 06/04/2013 12:57 PM, Jay Agarwal wrote:
> > > Registering pciex as peripheral clock instead of fixed clock as
> > > tegra_perih_reset_assert(deassert) api of this clock api gives
> > > warning and ultimately
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes/gitorious_thierryreding_linux
Quoting Stephen Warren (2013-06-04 12:08:08)
On 06/04/2013 12:57 PM, Jay Agarwal wrote:
Registering pciex as peripheral clock instead of fixed clock as
tegra_perih_reset_assert(deassert) api of this clock api gives
warning and ultimately does not succeed to assert(deassert
> > I have mentioned it in description as -> "Corrected logic in read/write
> config space to display right device number on bus 0"
> >
> > > Device 0:00.0 is usually the root complex, and device 0:01.0, 0:02.0
> > > etc are the root ports. The change proposed above makes 0:00.0 the
> > > first
I have mentioned it in description as - Corrected logic in read/write
config space to display right device number on bus 0
Device 0:00.0 is usually the root complex, and device 0:01.0, 0:02.0
etc are the root ports. The change proposed above makes 0:00.0 the
first root port,
> On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
> [...]
> > @@ -29,7 +29,7 @@
> > ranges = <0x8200 0 0x 0x 0 0x1000
> /* port 0 configuration space */
> > 0x8200 0 0x1000 0x000
> * PGP Signed by an unknown key
>
> On Wed, Jun 05, 2013 at 10:36:01AM -0600, Stephen Warren wrote:
> > On 06/05/2013 09:13 AM, Jay Agarwal wrote:
> > > - Make private data structure for each SoC
> > > - Add required Tegra30 clocks and regulators
> >
> * PGP Signed by an unknown key
>
> On Tue, Jun 04, 2013 at 01:17:15PM -0600, Stephen Warren wrote:
> > On 06/04/2013 12:57 PM, Jay Agarwal wrote:
> [...]
> > > struct tegra_pcie_port {
> > > @@ -384,7 +408,7 @@ static int tegra_pcie_read_conf(struc
* PGP Signed by an unknown key
On Tue, Jun 04, 2013 at 01:17:15PM -0600, Stephen Warren wrote:
On 06/04/2013 12:57 PM, Jay Agarwal wrote:
[...]
struct tegra_pcie_port {
@@ -384,7 +408,7 @@ static int tegra_pcie_read_conf(struct pci_bus
*bus, unsigned int devfn,
struct
* PGP Signed by an unknown key
On Wed, Jun 05, 2013 at 10:36:01AM -0600, Stephen Warren wrote:
On 06/05/2013 09:13 AM, Jay Agarwal wrote:
- Make private data structure for each SoC
- Add required Tegra30 clocks and regulators
- Add Tegra30 specific code in enable controller
On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
[...]
@@ -29,7 +29,7 @@
ranges = 0x8200 0 0x 0x 0 0x1000
/* port 0 configuration space */
0x8200 0 0x1000 0x1000 0 0x1000
/* port 1 configuration space
- Make private data structure for each SoC
- Add required Tegra30 clocks and regulators
- Add Tegra30 specific code in enable controller
- Added Tegra30 specific properties in pci binding document
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> > diff --git
> > a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> > b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
>
> > +- avdd-supply: Power supply for controller (1.05V)
>
> > + "cml": The Tegra clock of that name
>
> Both those changes need to mention
Moving PCIe controller node to correct place so
that it is sorted by register address in .dtsi file
Signed-off-by: Jay Agarwal
---
This patch is based on remotes/gitorious_thierryreding_linux/tegra/next and
should be applied on top of this.
changes in V2:
Corrected patch synopsis
arch/arm
Moving PCIe controller node to correct place so
that it is sorted by register address in .dtsi file
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
This patch is based on remotes/gitorious_thierryreding_linux/tegra/next and
should be applied on top of this.
changes in V2:
Corrected patch
diff --git
a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+- avdd-supply: Power supply for controller (1.05V)
+ cml: The Tegra clock of that name
Both those changes need to mention that those
- Make private data structure for each SoC
- Add required Tegra30 clocks and regulators
- Add Tegra30 specific code in enable controller
- Added Tegra30 specific properties in pci binding document
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Added num-lanes property
of tegra_pcie_bus structure in tegra_pcie_remove
- Added Tegra30 specific properties in pci binding document
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Added entry in required properties in pci
- Add interrupt-names property
- Correct downstream I/O size
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Avoided changes in cml clock as per review comment
arch/arm/boot/dts/tegra30
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert).
Signed-off-by: Jay Agarwal
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
Anybody aware of hang in r8169 driver over pcie interface mentioned at bottom
of this mail?
-Original Message-
From: Jay Agarwal
Sent: Tuesday, June 04, 2013 7:17 PM
To: 'Stephen Warren'
Cc: 'thierry.red...@avionic-design.de'
Subject: RE: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe
Forwarding to bigger aliases
Anybody aware of hang in r8169 driver over pcie interface mentioned at bottom
of this mail?
-Original Message-
From: Jay Agarwal
Sent: Tuesday, June 04, 2013 7:17 PM
To: 'Stephen Warren'
Cc: 'thierry.red...@avionic-design.de'
Subject: RE: [PATCH 4/4] ARM
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert).
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes/gitorious_thierryreding_linux
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Added
of tegra_pcie_bus structure in tegra_pcie_remove
- Added Tegra30 specific properties in pci binding document
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Added entry in required
- Add interrupt-names property
- Correct downstream I/O size
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should
be applied on top of this.
Changes in V3:
- Avoided changes in cml clock as per review comment
arch/arm
> On 05/29/2013 04:10 AM, Jay Agarwal wrote:
> >>>> So, if I apply this series, I do see the PCIe bridge and Ethernet
> >>>> device get enumerated, but I don't see the USB3 controller get
> >>>> enumerated. I believe that is a PCIe device behind the
> On 05/15/2013 07:55 AM, Jay Agarwal wrote:
> > Moving PCIe controller node to correct place so that it is sorted by
> > register address in .dtsi file
>
> Reviewed-by: Stephen Warren
Hi Thierry,
If reviews are done, Can you please include this into your repository?
-
On 05/15/2013 07:55 AM, Jay Agarwal wrote:
Moving PCIe controller node to correct place so that it is sorted by
register address in .dtsi file
Reviewed-by: Stephen Warren swar...@nvidia.com
Hi Thierry,
If reviews are done, Can you please include this into your repository
On 05/29/2013 04:10 AM, Jay Agarwal wrote:
So, if I apply this series, I do see the PCIe bridge and Ethernet
device get enumerated, but I don't see the USB3 controller get
enumerated. I believe that is a PCIe device behind the same bridge
on the
same Tegra PCIe port.
Shouldn't
> > > So, if I apply this series, I do see the PCIe bridge and Ethernet
> > > device get enumerated, but I don't see the USB3 controller get
> > > enumerated. I believe that is a PCIe device behind the same bridge
> > > on the
> > same Tegra PCIe port.
> > > Shouldn't this device show up?
> > I
So, if I apply this series, I do see the PCIe bridge and Ethernet
device get enumerated, but I don't see the USB3 controller get
enumerated. I believe that is a PCIe device behind the same bridge
on the
same Tegra PCIe port.
Shouldn't this device show up?
I have also reproduced
> > On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> > > - Enable PCIe controller on Cardhu
> > > - Only port 2 is connected on this board
> > > - Add regulators required for Tegra30
> > > - Patch is based on remotes/gitorious_thierryreding_linux/tegra
On 05/08/2013 04:57 AM, Jay Agarwal wrote:
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
diff --git
> On 05/08/2013 04:57 AM, Jay Agarwal wrote:
> > - Enable PCIe controller on Cardhu
> > - Only port 2 is connected on this board
> > - Add regulators required for Tegra30
> > - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
> &g
Moving PCIe controller node to correct place so
that it is sorted by register address in .dtsi file
Signed-off-by: Jay Agarwal
---
This patch is based on remotes/gitorious_thierryreding_linux/tegra/next
and should be applied on top of this.
arch/arm/boot/dts/tegra30.dtsi | 132
Moving PCIe controller node to correct place so
that it is sorted by register address in .dtsi file
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
This patch is based on remotes/gitorious_thierryreding_linux/tegra/next
and should be applied on top of this.
arch/arm/boot/dts/tegra30.dtsi
On 05/08/2013 04:57 AM, Jay Agarwal wrote:
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
diff --git
-by: Jay Agarwal
---
.../bindings/pci/nvidia,tegra20-pcie.txt |1 +
drivers/pci/host/pci-tegra.c | 145 +---
2 files changed, 127 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
b
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
Signed-off-by: Jay Agarwal
---
arch/arm/boot/dts/tegra30-cardhu.dtsi
- Add interrupt-names property
- Correct downstream I/O size
- Correct cml clock name for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
Signed-off-by: Jay Agarwal
---
arch/arm/boot/dts/tegra30.dtsi |6 +++---
1 files
of this.
Signed-off-by: Jay Agarwal
---
drivers/clk/tegra/clk-tegra30.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51b..6a80b40 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk
of this.
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
drivers/clk/tegra/clk-tegra30.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51b..6a80b40 100644
--- a/drivers/clk/tegra/clk-tegra30.c
- Add interrupt-names property
- Correct downstream I/O size
- Correct cml clock name for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
arch/arm/boot/dts/tegra30.dtsi |6
- Enable PCIe controller on Cardhu
- Only port 2 is connected on this board
- Add regulators required for Tegra30
- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next
- and should be applied on top of this.
Signed-off-by: Jay Agarwal jagar...@nvidia.com
---
arch/arm/boot/dts
-by: Jay Agarwal jagar...@nvidia.com
---
.../bindings/pci/nvidia,tegra20-pcie.txt |1 +
drivers/pci/host/pci-tegra.c | 145 +---
2 files changed, 127 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20
> On 04/12/2013 10:43 AM, Jay Agarwal wrote:
> >> On 04/08/2013 09:41 AM, Jay Agarwal wrote:
> >>> Signed-off-by: Jay Agarwal
> >>>
> >>> - Enable pcie root port 2 for cardhu
> >>> - Make private data structure for each SOC
> >
> On 04/08/2013 09:41 AM, Jay Agarwal wrote:
> > Signed-off-by: Jay Agarwal
> >
> > - Enable pcie root port 2 for cardhu
> > - Make private data structure for each SOC
> > - Add required tegra3 clocks and regulators
> > - Add tegra3 specific code in en
> On Mon, Apr 08, 2013 at 08:27:00PM +0200, Stephen Warren wrote:
> > On 04/08/2013 09:41 AM, Jay Agarwal wrote:
> > > Signed-off-by: Jay Agarwal
> >
> > Your s-o-b line should be below the patch description, not above it.
> > Please see Documentation/Submitt
> > err = regulator_disable(pcie->pex_clk_supply);
> > if (err < 0)
> > - dev_err(pcie->dev, "failed to disable pex-clk regulator:
> %d\n",
> > + dev_warn(pcie->dev, "failed to disable pex-clk regulator:
> %d\n",
> > err);
> >
> > err =
err = regulator_disable(pcie-pex_clk_supply);
if (err 0)
- dev_err(pcie-dev, failed to disable pex-clk regulator:
%d\n,
+ dev_warn(pcie-dev, failed to disable pex-clk regulator:
%d\n,
err);
err =
On Mon, Apr 08, 2013 at 08:27:00PM +0200, Stephen Warren wrote:
On 04/08/2013 09:41 AM, Jay Agarwal wrote:
Signed-off-by: Jay Agarwal jagar...@nvidia.com
Your s-o-b line should be below the patch description, not above it.
Please see Documentation/SubmittingPatches.
I also don't
On 04/08/2013 09:41 AM, Jay Agarwal wrote:
Signed-off-by: Jay Agarwal jagar...@nvidia.com
- Enable pcie root port 2 for cardhu
- Make private data structure for each SOC
- Add required tegra3 clocks and regulators
- Add tegra3 specific code in enable controller
- Modify clock tree
On 04/12/2013 10:43 AM, Jay Agarwal wrote:
On 04/08/2013 09:41 AM, Jay Agarwal wrote:
Signed-off-by: Jay Agarwal jagar...@nvidia.com
- Enable pcie root port 2 for cardhu
- Make private data structure for each SOC
- Add required tegra3 clocks and regulators
- Add tegra3 specific code
Signed-off-by: Jay Agarwal
- Add interrupt-names property
- Correct downstream I/O size
- Correct cml clock name for tegra30
- Based on git://gitorious.org/thierryreding/linux.git
arch/arm/boot/dts/tegra30.dtsi |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch
Signed-off-by: Jay Agarwal
- Add PCIe node entry for cardhu
- Enable only root port 2
- Initialize regulators required for tegra30
- Based on git://gitorious.org/thierryreding/linux.git
arch/arm/boot/dts/tegra30-cardhu.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions
Signed-off-by: Jay Agarwal
- Enable pcie root port 2 for cardhu
- Make private data structure for each SOC
- Add required tegra3 clocks and regulators
- Add tegra3 specific code in enable controller
- Modify clock tree to get clocks based on device
- Based on git://gitorious.org/thierryreding
Signed-off-by: Jay Agarwal jagar...@nvidia.com
- Enable pcie root port 2 for cardhu
- Make private data structure for each SOC
- Add required tegra3 clocks and regulators
- Add tegra3 specific code in enable controller
- Modify clock tree to get clocks based on device
- Based on git
Signed-off-by: Jay Agarwal jagar...@nvidia.com
- Add interrupt-names property
- Correct downstream I/O size
- Correct cml clock name for tegra30
- Based on git://gitorious.org/thierryreding/linux.git
arch/arm/boot/dts/tegra30.dtsi |6 +++---
1 files changed, 3 insertions(+), 3 deletions
Signed-off-by: Jay Agarwal jagar...@nvidia.com
- Add PCIe node entry for cardhu
- Enable only root port 2
- Initialize regulators required for tegra30
- Based on git://gitorious.org/thierryreding/linux.git
arch/arm/boot/dts/tegra30-cardhu.dtsi | 11 +++
1 files changed, 11 insertions
Hi All,
In my Graphics card, it has 4 memory requirement:
a. 32 bit non-prefetchable
b. 32 bit prefetchable
c. 64 bit non-prefetchable.
d. 64 bit prefetchable
And I see a is programmed in BAR0(offset 0x10), c in BAR3(offset 0x1C), d in
BAR1(offset 0x14) but b is not programmed anywhere.
So is
Hi All,
In my Graphics card, it has 4 memory requirement:
a. 32 bit non-prefetchable
b. 32 bit prefetchable
c. 64 bit non-prefetchable.
d. 64 bit prefetchable
And I see a is programmed in BAR0(offset 0x10), c in BAR3(offset 0x1C), d in
BAR1(offset 0x14) but b is not programmed anywhere.
So is
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