在2024年2月27日二月 上午3:14，maobibo写道：
> On 2024/2/27 上午4:02, Jiaxun Yang wrote:
>>
>>
>> 在2024年2月26日二月 上午8:04，maobibo写道：
>>> On 2024/2/26 下午2:12, Huacai Chen wrote:
>>>> On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>>>>>
>>>>
在2024年2月26日二月 上午8:04，maobibo写道：
> On 2024/2/26 下午2:12, Huacai Chen wrote:
>> On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>>>
>>>
>>>
>>> On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Instruction cpucfg can be
在 2021/4/19 18:56, Youling Tang 写道:
From: Huacai Chen
kexec-tools use mem=X@Y to pass usable memories to crash kernel, but in
commit a94e4f24ec836c8984f83959 ("MIPS: init: Drop boot_mem_map") all
BIOS passed memories are removed by early_parse_mem(). I think this is
reasonable for a normal
在 2021/4/19 18:50, Youling Tang 写道:
This problem may only occur on NUMA platforms. When machine start with the
"mem=" parameter on Loongson64, it cannot boot. When parsing the "mem="
parameter, first remove all RAM, and then add memory through memblock_add(),
which causes the newly added
On Wed, Apr 14, 2021, at 9:26 AM, Qing Zhang wrote:
> Add power management register operations to support reboot and poweroff.
>
> Signed-off-by: Qing Zhang
No that's not what we intended to do.
Please add a devicetree node for pm block.
Thanks
> ---
>
On Mon, Mar 29, 2021, at 3:15 PM, Qing Zhang wrote:
> When using the Loongson-3A4000 machine for serial port debugging,
> there is no /dev/ttyUSB* output, which makes the serial port unavailable,
> For convenience, we open this configuration.
>
> zhangqing@loongson-pc:~$ cat
hecking the range of CKSEG0 and XKPHYS.
> > loongson_fw_interface will be used in the future.
> >
> > Signed-off-by: Jiaxun Yang
> > Signed-off-by: Qing Zhang
> > Tested-by: Ming Wang
> > ---
> >
> > v3-v4: Standard submission of information
> >
On Wed, Mar 10, 2021, at 5:37 PM, zhangqing wrote:
>
>
> On 03/10/2021 04:50 PM, Sergei Shtylyov wrote:
> > Hello!
> >
> >You don't seem to need this initializer.
> Hi,Sergei
>
> Thanks for your suggestion,
> clk will not be affected by others when it is defined until the value is
>
On Wed, Mar 10, 2021, at 3:56 PM, Qing Zhang wrote:
> Add liointc-2.0 properties support, so update the maxItems and description.
>
> Signed-off-by: Jiaxun Yang
^ I have nothing todo with this patch so please drop me for this one :-)
> Signed-off-by: Qing Zhang
> Teste
在 2021/3/8 17:49, Thomas Bogendoerfer 写道:
On Sat, Mar 06, 2021 at 06:55:41PM +0800, Jiaxun Yang wrote:
On Sat, Mar 6, 2021, at 5:53 PM, Thomas Bogendoerfer wrote:
[...]
Just to understand you, you want
arch/mips/include/asm/loongson/2ef
arch/mips/include/asm/loongson/32
arch/mips/include
On Sat, Mar 6, 2021, at 5:53 PM, Thomas Bogendoerfer wrote:
> On Sat, Mar 06, 2021 at 05:00:15PM +0800, Jiaxun Yang wrote:
> >
> >
> > On Sat, Mar 6, 2021, at 4:03 PM, Thomas Bogendoerfer wrote:
> > > On Thu, Mar 04, 2021 at 07:00:57PM +0800, Qing Zh
On Sat, Mar 6, 2021, at 4:03 PM, Thomas Bogendoerfer wrote:
> On Thu, Mar 04, 2021 at 07:00:57PM +0800, Qing Zhang wrote:
> > The purpose of separating loongson_system_configuration from boot_param.h
> > is to keep the other structure consistent with the firmware.
> >
>
在 2021/3/5 11:12, HongJieDeng 写道:
From: Hongjie Deng
We need more stack space, xori/ori no longer apply when
_THREAD_MASK exceeds 16 bits
Signed-off-by: Hongjie Deng
---
arch/mips/include/asm/stackframe.h | 8
arch/mips/kernel/genex.S | 6 ++
2 files changed,
在 2021/3/4 下午7:00, Qing Zhang 写道:
The purpose of separating loongson_system_configuration from boot_param.h
is to keep the other structure consistent with the firmware.
Signed-off-by: Jiaxun Yang
Signed-off-by: Qing Zhang
Acked-by: Jiaxun Yang
- Jiaxun
---
.../include/asm/mach
在 2021/3/4 下午7:00, Qing Zhang 写道:
We don't need them anymore, They are uniform on all Loongson64 systems
and have been fixed in DeviceTree.loongson3_platform_init is replaced
with DTS + driver.
Signed-off-by: Jiaxun Yang
Signed-off-by: Qing Zhang
Acked-by: Jiaxun Yang
Hmm, why it comes
在 2021/3/5 上午7:08, Maciej W. Rozycki 写道:
On Thu, 4 Mar 2021, Tiezhu Yang wrote:
This is a known bug [2] with Clang, as Simon Atanasyan said,
"There is no plan on support O32 for MIPS64 due to lack of
resources".
Huh? Is that a joke? From the o32 psABI's point of view a MIPS64 CPU is
在 2021/3/1 下午11:29, Thomas Bogendoerfer 写道:
KVM_GUEST is broken and unmaintained, so let's remove it.
Signed-off-by: Thomas Bogendoerfer
Reviewed-by: Jiaxun Yang
I'll prepare a patch for KVM side removal.
Thanks.
- Jiaxun
在 2021/2/26 上午9:37, Jinyang He 写道:
On 02/24/2021 11:40 PM, Jiaxun Yang wrote:
On Wed, Feb 24, 2021, at 9:02 PM, Jinyang He wrote:
detect_memory_region() was committed by Commit 4d9f77d25268 ("MIPS: add
detect_memory_region()"). Then it was equipped by Commit dd63b00804a5
("MIP
On Wed, Feb 24, 2021, at 9:02 PM, Jinyang He wrote:
> detect_memory_region() was committed by Commit 4d9f77d25268 ("MIPS: add
> detect_memory_region()"). Then it was equipped by Commit dd63b00804a5
> ("MIPS: ralink: make use of the new memory detection code") and
> Commit 9b75733b7b5e ("MIPS:
On Tue, Feb 9, 2021, at 5:32 PM, Qing Zhang wrote:
> Distinguish between 3A series CPU and 2K1000 CPU UART0.
>
> Signed-off-by: Jiaxun Yang
> Signed-off-by: Qing Zhang
> Signed-off-by: Xingxing Su
Personally I don't like this kind of quirk.
Probably we should use earlyc
iointc1 node.
>
> Signed-off-by: Jiaxun Yang
> Signed-off-by: Qing Zhang
> Signed-off-by: Xingxing Su
You should document dt binding changes.
Thanks
- Jiaxun
> ---
> drivers/irqchip/irq-loongson-liointc.c | 55 +-
> 1 file changed, 46 insertions(+), 9 delet
On Tue, Feb 9, 2021, at 12:32 AM, Jiaxun Yang wrote:
>
>
> On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
> > According to MIPS EJTAG Specification [1], a Debug Breakpoint
> > exception occurs when an SDBBP instruction is executed, the
> > CP0_DEBUG bit
On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
> According to MIPS EJTAG Specification [1], a Debug Breakpoint
> exception occurs when an SDBBP instruction is executed, the
> CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception
> occurred, just check bit DBp for SDBBP is more
On Mon, Feb 1, 2021, at 9:12 AM, Jinyang He wrote:
> On 01/31/2021 06:38 PM, Jiaxun Yang wrote:
>
> >
> > On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote:
> >> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7.
> > Do we have NEW kernel bu
On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote:
> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7.
Do we have NEW kernel build?
CONFIG_64BIT assumed N64 as kernel ABI.
-Jiaxun
>
> Signed-off-by: Jinyang He
> ---
> arch/mips/kernel/mcount.S | 4 ++--
> 1 file changed, 2
在 2021/1/16 上午12:58, John Garry 写道:
This is a reboot of my original series to address the problem of drivers
for legacy ISA devices accessing unmapped IO port regions on arm64 systems
and causing the system to crash.
There was another recent report of such an issue [0], and some old ones
[1]
bot
Signed-off-by: Souptick Joarder
Reviewed-by: Jiaxun Yang
---
arch/mips/kernel/cacheinfo.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 5f9d0eb..c858ae3 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/ker
在 2021/1/12 下午8:29, Jinyang He 写道:
Not familiar with microMIPS. Not test on microMIPS.
Hi Jinyang,
I was messing around QEMU microMIPS and found kernel stuck
at loading init process after applied your patches :-(
Thanks.
- Jiaxun
Jinyang He (4):
MIPS: process: Reorder header files
-by: Alexander Lobakin
Reviewed-by: Jiaxun Yang
---
arch/mips/kernel/module.c | 109 ++
1 file changed, 52 insertions(+), 57 deletions(-)
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 3c0c3d1260c1..14f46d17500a 100644
--- a/arch
these machines.
Signed-off-by: Jiaxun Yang
Cc: sta...@vger.kernel.org # 5.4+
--
v2: Specify touchpad to ELAN0634
v3: Stupid missing ! in v2
v4: Correct acpi_dev_present usage (Hans)
---
drivers/platform/x86/ideapad-laptop.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git
l not increment by 4. Fix it and clear BSS from _edata
> to (_end - 1).
Oops, my fault.
My QEMU based local test setup somehow never really tested zboot.
Reviewed-by: Jiaxun Yang
Thanks!
- Jiaxun
>
> Signed-off-by: Jinyang He
> ---
> arch/mips/boot/compressed/head.S | 2 +-
>
profile switch itself, we'll leave it for userspace programs.
Tested on Lenovo Yoga-14S ARE Chinese Edition.
Signed-off-by: Jiaxun Yang
---
drivers/platform/x86/Kconfig | 1 +
drivers/platform/x86/ideapad-laptop.c | 289 ++
2 files changed, 290 insertions(+)
diff
Add a object pointer to handler callbacks to avoid having
global variables everywhere.
Signed-off-by: Jiaxun Yang
Suggested-by: Hans de Goede
---
drivers/acpi/platform_profile.c | 4 ++--
include/linux/platform_profile.h | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git
Tested on Lenovo Yoga-14S ARE Chinese Edition.
v2: Use another private data approach (Hans)
Jiaxun Yang (2):
ACPI: platform-profile: Introduce object pointers to callbacks
platform/x86: ideapad-laptop: DYTC Platform profile support
drivers/acpi/platform_profile.c | 4 +-
drivers
在 2021/1/5 下午3:39, Fāng-ruì Sòng 写道:
On Mon, Jan 4, 2021 at 4:21 AM Alexander Lobakin wrote:
GCC somehow manages to place some of the symbols from main.c into
.rel.dyn section:
mips-alpine-linux-musl-ld: warning: orphan section `.rel.dyn'
from `init/main.o' being placed in section `.rel.dyn'
在 2021/1/5 上午5:58, Mark Pearson 写道:
On 04/01/2021 15:58, Hans de Goede wrote:
Hi,
On 1/4/21 9:33 PM, Rafael J. Wysocki wrote:
On Mon, Jan 4, 2021 at 3:36 PM Hans de Goede
wrote:
Hi,
On 1/1/21 1:56 PM, Jiaxun Yang wrote:
Tested on Lenovo Yoga-14SARE Chinese Edition.
[...]
Just for my
在 2021/1/4 下午6:59, Peter Zijlstra 写道:
On Tue, Dec 29, 2020 at 08:55:59PM +0800, Tiezhu Yang wrote:
+u64 perf_reg_abi(struct task_struct *tsk)
+{
+ if (test_tsk_thread_flag(tsk, TIF_32BIT_REGS))
+ return PERF_SAMPLE_REGS_ABI_32;
+ else
+ return
these machines.
Signed-off-by: Jiaxun Yang
Cc: sta...@vger.kernel.org # 5.4+
--
v2: Specify touchpad to ELAN0634
v3: Stupid missing ! in v2
---
drivers/platform/x86/ideapad-laptop.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/ideapad-laptop.c
b
these machines.
Signed-off-by: Jiaxun Yang
Cc: sta...@vger.kernel.org # 5.4+
--
v2: Specify touchpad to ELAN0634
---
drivers/platform/x86/ideapad-laptop.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/ideapad-laptop.c
b/drivers/platform/x86/ideapad
在 2021/1/2 上午1:09, Barnabás Pőcze 写道:
Hi
2021. január 1., péntek 17:08 keltezéssel, Jiaxun Yang írta:
[...]
@@ -1006,6 +1018,10 @@ static int ideapad_acpi_add(struct platform_device *pdev)
if (!priv->has_hw_rfkill_switch)
write_ec_cmd(priv->adev->handle, VP
On Fri, Jan 1, 2021, at 10:20 PM, Barnabás Pőcze wrote:
> Hi
>
>
> 2021. január 1., péntek 7:11 keltezéssel, Jiaxun Yang írta:
>
> > Newer ideapads (e.g.: Yoga 14s, 720S 14) comes with I2C HID
> > Touchpad and do not use EC to switch touchpad. Reading VPCCMD_R_TO
Tested on Lenovo Yoga-14SARE Chinese Edition.
Jiaxun Yang (2):
ACPI: platform-profile: Introduce data parameter to handler
platform/x86: ideapad-laptop: DYTC Platform profile support
drivers/acpi/platform_profile.c | 4 +-
drivers/platform/x86/Kconfig | 1 +
drivers
Add a data parameter to handler callbacks to avoid having
global variables everywhere.
Signed-off-by: Jiaxun Yang
---
drivers/acpi/platform_profile.c | 4 ++--
include/linux/platform_profile.h | 5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/acpi
profile wwitch itself, we'll leave it for userspace programs.
Tested on Lenovo Yoga-14SARE Chinese Edition.
Signed-off-by: Jiaxun Yang
---
drivers/platform/x86/Kconfig | 1 +
drivers/platform/x86/ideapad-laptop.c | 281 ++
2 files changed, 282 insertions(+)
diff
.
Signed-off-by: Jiaxun Yang
Cc: sta...@vger.kernel.org # 5.4+
---
drivers/platform/x86/ideapad-laptop.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/ideapad-laptop.c
b/drivers/platform/x86/ideapad-laptop.c
index 7598cd46cf60..b6a4db37d0fc
在 2020/12/31 23:38, WANG Xuerui 写道:
Hi Jiaxun,
Overall a nice step towards a more conformant arch/mips! Some nits
below though.
On 12/30/20 11:23 AM, Jiaxun Yang wrote:
Add infrastructure to display CPU vulnerabilities.
As most MIPS CPU vendors are dead today and we can't confirm
在 2020/12/31 23:43, WANG Xuerui 写道:
Hi Jiaxun,
On 12/30/20 11:23 AM, Jiaxun Yang wrote:
Loongson64C is known to be vulnerable to meltdown according to
PoC from Rui Wang .
Loongson64G defended these side-channel attack by silicon.
"Loongson64G mitigated it in hardware"?
Cercueil
Signed-off-by: Jiaxun Yang
--
v2: Remove start label (paul)
---
arch/mips/boot/compressed/head.S | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb483a9ff..070b2fbabae4
在 2020/12/30 上午11:08, Jiaxun Yang 写道:
.cprestore is removed as we don't expect Position Independent
zboot ELF.
.noreorder is also removed and rest instructions are massaged
to improve readability.
t9 register is used for indirect jump as MIPS ABI requirement.
start label is removed
cluster is required for cacheinfo to set shared_cpu_map correctly.
Signed-off-by: Jiaxun Yang
Reviewed-by: Tiezhu Yang
Tested-by: Tiezhu Yang
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang
Reviewed-by: Tiezhu Yang
Tested-by: Tiezhu Yang
---
arch/mips/kernel/cacheinfo.c | 34
Add infrastructure to display CPU vulnerabilities.
As most MIPS CPU vendors are dead today and we can't confirm
vulnerabilities states with them, we'll display vulnerabilities
as "Unknown" by default and override them in cpu-probe.c
Signed-off-by: Jiaxun Yang
---
arch/mi
Loongson64C is known to be vulnerable to meltdown according to
PoC from Rui Wang .
Loongson64G defended these side-channel attack by silicon.
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cpu-probe.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch
-and-side-channel-vulnerabilities/
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cpu-probe.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 03adeed58efb..2460783dbdb1 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips
Cercueil
Signed-off-by: Jiaxun Yang
--
v2: Remove start label (paul)
---
arch/mips/boot/compressed/head.S | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb483a9ff..977218c90bc8
在 2020/12/25 下午6:35, Qing Zhang 写道:
Switch the DT binding to a YAML schema to enable the DT validation.
Signed-off-by: Qing Zhang
---
v4: fix warnings/errors about running 'make dt_binding_check'
---
.../devicetree/bindings/spi/loongson,spi-ls7a.yaml | 46 ++
1 file
On Mon, Dec 21, 2020, at 10:09 PM, Paul Cercueil wrote:
> Hi Jiaxun,
>
> Le lun. 21 déc. 2020 à 21:00, Jiaxun Yang a
> écrit :
> > .cprestore is removed as we don't except Position Independent
> > zboot ELF.
> >
> > .noreorder is also removed and rest ins
.cprestore is removed as we don't except Position Independent
zboot ELF.
.noreorder is also removed and rest instructions is massaged
to improve readability.
t9 register is used to indirect jump as MIPS ABI requirement.
Reported-by: Paul Cercueil
Signed-off-by: Jiaxun Yang
---
arch/mips/boot
在 2020/12/16 下午6:05, Tiezhu Yang 写道:
Hi,
In the current upstream mainline kernel, perf record --call-graph dwarf
is not supported for architecture mips64. I find the following related
patches about this feature by David Daney and
Archer Yan in Sep 2019.
AFAIK ddaney left Cavium at 2018
于 2020年12月9日 GMT+08:00 上午6:28:11, Roman Kiryanov 写到:
>On Sat, Nov 14, 2020 at 1:48 AM Jiaxun Yang wrote:
>> Thus I do think it shouldn't be retired as for now. If nobody comes in
>> I'd also willing to maintain
>
>Hi Jiaxun and Hancai,
>
>I sent a patch to add you
在 2020/12/8 15:44, Qing Zhang 写道:
add spi and amd node support.
Hi Qing,
Thanks for your patch.
What is AMD node?
Also given that different boards may have different flash, is it a wise
idea to hardcode here?
Thanks.
- Jiaxun
Signed-off-by: Qing Zhang
---
v2:
- Add spi about pci
在 2020/12/8 15:44, Qing Zhang 写道:
Add spi-ls7a binding documentation.
Signed-off-by: Qing Zhang
---
Documentation/devicetree/bindings/spi/spi-ls7a.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-ls7a.txt
Add vulnerabilities display for MIPS.
Jiaxun Yang (3):
MIPS: Add vulnerabilities infrastructure
MIPS: cpu-probe: Vulnerabilities for MIPS cores
MIPS: cpu-probe: Vulnerabilities for Loongson cores
arch/mips/Kconfig| 1 +
arch/mips/include/asm/cpu-info.h | 5
arch
ower memory after relocation?
Reviewed-by: Jiaxun Yang
Thanks.
- Jiaxun
>
>Signed-off-by: Jinyang He
>---
> arch/mips/loongson64/numa.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
>index
于 2020年12月3日 GMT+08:00 下午4:57:47, Jinyang He 写到:
>This problem may only occur on NUMA platforms. When machine start
>with the "mem=" parameter on Loongson64, it cannot boot. When parsing the
>"mem=" parameter, first all the RAM was removed, and then the memory was
>not added by
在 2020/11/25 下午6:07, Jinyang He 写道:
Provide a weak plat_get_fdt() in relocate.c in case some platform enable
USE_OF while plat_get_fdt() is useless.
1MB RELOCATION_TABLE_SIZE is small for Loongson64 because too many
instructions should be relocated. 2MB is enough in present.
Add KASLR
在 2020/12/2 下午6:39, Thomas Bogendoerfer 写道:
On Wed, Dec 02, 2020 at 11:00:05AM +0800, Jinyang He wrote:
Reading synci_step by using rdhwr instruction may return zero if no cache
need be synchronized. On the one hand, to make sure all load operation and
store operation finished we do __sync()
在 2020/12/3 上午11:19, Tiezhu Yang 写道:
In the current code, CONFIG_ARCH_KEEP_MEMBLOCK is not set for MIPS arch,
memblock_discard() will discard memory and reserved arrays if they were
allocated, select ARCH_KEEP_MEMBLOCK to give a chance to track "memory"
and "reserved" memblocks after early
在 2020/11/23 17:19, Qing Zhang 写道:
The LS3A SPI module is now supported, enable it.
Signed-off-by: Qing Zhang
---
arch/mips/boot/dts/loongson/loongson64c-package.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts/loongson/loongson64c-package.dtsi
Hi Lizhi,
You didn't send the patch to any mail list, is this intentional?
在 2020/11/23 18:03, lizhi01 写道:
Add gmac driver to support LS7A bridge chip.
Signed-off-by: lizhi01
---
arch/mips/configs/loongson3_defconfig | 4 +-
drivers/net/ethernet/stmicro/stmmac/Kconfig
Link: https://lore.kernel.org/lkml/x6+wgmuccpu2l...@kroah.com/
Cc: che...@lemote.com
Cc: gre...@linuxfoundation.org
Jiaxun Yang (2):
rtc: goldfish: Remove GOLDFISH dependency
MAINTAINERS: Set myself as Goldfish RTC maintainer
MAINTAINERS | 2 +-
drivers/rtc/Kconfig | 1 -
2 files
Goldfish platform is covered with dust.
However the goldfish-rtc had been used as virtualized RTC
in QEMU for RISC-V virt hw and MIPS loongson3-virt hw, thus
we can drop other parts of goldfish but leave goldfish-rtc here.
Signed-off-by: Jiaxun Yang
---
drivers/rtc/Kconfig | 1 -
1 file changed
While Gildfish platform is dusted, the RTC driver remains
valuable for us.
I'm volunteering to maintain goldfish RTC driver onward.
Signed-off-by: Jiaxun Yang
Cc: Miodrag Dinic
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
在 2020/11/14 下午4:15, Greg KH 写道:
+ qemu-riscv list and QEMU device maintainers of goldfish_rtc
On Sat, Nov 14, 2020 at 04:06:24PM +0800, 陈华才 wrote:
Hi, All,
Goldfish RTC works well on MIPS, and QEMU RISC-V emulator use Goldfish
as well, so I think we should keep it in kernel.
But does
于 2020年11月13日 GMT+08:00 上午11:41:01, Tiezhu Yang 写到:
>On 11/13/2020 10:21 AM, Jiaxun Yang wrote:
>>
>>
>> 在 2020/11/12 20:03, Tiezhu Yang 写道:
>>> On 11/12/2020 06:09 PM, Jiaxun Yang wrote:
>>>>
>>>>
>>>> 在 2020/11/12 18:04, Jiaxu
Hi all,
在 2020/11/11 22:52, Serge Semin 写道:
Hello Alexander
On Tue, Nov 10, 2020 at 11:29:50AM +0100, Alexander Sverdlin wrote:
2) The check_kernel_sections_mem() method can be removed. But it
should be done carefully. We at least need to try to find all the
platforms, which rely on its
在 2020/11/12 20:03, Tiezhu Yang 写道:
On 11/12/2020 06:09 PM, Jiaxun Yang wrote:
在 2020/11/12 18:04, Jiaxun Yang 写道:
Hi Tiezhu,
在 2020/11/12 16:29, Tiezhu Yang 写道:
Add read_persistent_clock64() to read the time from the battery backed
persistent clock. With this patch, we can fix
在 2020/11/12 18:04, Jiaxun Yang 写道:
Hi Tiezhu,
在 2020/11/12 16:29, Tiezhu Yang 写道:
Add read_persistent_clock64() to read the time from the battery backed
persistent clock. With this patch, we can fix the wrong time issue due
to the system clock is not consistent with hardware clock after
Hi Tiezhu,
在 2020/11/12 16:29, Tiezhu Yang 写道:
Add read_persistent_clock64() to read the time from the battery backed
persistent clock. With this patch, we can fix the wrong time issue due
to the system clock is not consistent with hardware clock after resume
from sleep state S3 (suspend to
在 2020/11/4 14:31, Jinyang He 写道:
Hi, all,
On 11/03/2020 03:12 PM, Tiezhu Yang wrote:
In play_dead function, the whole 64-bit PC mailbox was used as a
indicator
to determine if the master core had written boot jump information.
However, after we introduced CSR mailsend, the hardware will
在 2020/8/22 0:55, Thomas Bogendoerfer 写道:
On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote:
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang
在 2020/11/3 11:15, Tiezhu Yang 写道:
Since decode_cpucfg() is only used for Loongson64, just move
it to loongson_regs.h to avoid the pollution of common code
with #ifdef CONFIG_CPU_LOONGSON64.
Signed-off-by: Tiezhu Yang
Hi all,
Don't know if it's a good idea to move this piece of code
在 2020/11/3 11:15, Tiezhu Yang 写道:
In loongson3_type3_play_dead(), in order to make sure the PC address is
correct, use lw to read the low 32 bits first, if the result is not zero,
then use ld to read the whole 64 bits, otherwise there maybe exists atomic
problem due to write high 32 bits
在 2020/10/30 20:13, Jiaxun Yang 写道:
在 2020/10/30 14:22, Tiezhu Yang 写道:
On 10/30/2020 12:00 PM, Jiaxun Yang wrote:
在 2020/10/29 16:02, Tiezhu Yang 写道:
The field LPA of CP0_CONFIG3 register is read only for Loongson64,
so the
write operations are meaningless, remove them.
Signed-off
在 2020/10/30 14:22, Tiezhu Yang 写道:
On 10/30/2020 12:00 PM, Jiaxun Yang wrote:
在 2020/10/29 16:02, Tiezhu Yang 写道:
The field LPA of CP0_CONFIG3 register is read only for Loongson64,
so the
write operations are meaningless, remove them.
Signed-off-by: Tiezhu Yang
---
arch/mips/include
在 2020/10/29 16:02, Tiezhu Yang 写道:
Loongson 3A4000+ CPU has per-core Mail_Send register to send mail,
there is no need to maintain register address of each core and node,
just simply specify cpu number.
Signed-off-by: Lu Zeng
Signed-off-by: Jianmin Lv
Signed-off-by: Tiezhu Yang
---
在 2020/10/29 16:02, Tiezhu Yang 写道:
The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
write operations are meaningless, remove them.
Signed-off-by: Tiezhu Yang
---
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8
arch/mips/loongson64/numa.c
于 2020年10月12日 GMT+08:00 下午8:02:25, Tiezhu Yang 写到:
>On 10/12/2020 06:38 PM, Thomas Bogendoerfer wrote:
>> On Sun, Oct 11, 2020 at 07:47:53AM +0800, Tiezhu Yang wrote:
>>> Add /proc/boardinfo to get mainboard and BIOS info easily on the Loongson
>>> platform, this is useful to point out the
n.
(3) After commit 6fbde6b492df ("MIPS: Loongson64: Move files to the
top-level directory"), CONFIG_ZONE_DMA32 is always set for Loongson64
due to MACH_LOONGSON64 selects ZONE_DMA32, so no need to use ifdef any
more, just remove it.
Signed-off-by: Tiezhu Yang
Reviewed-by: Jiaxun Yang
--
在 2020/10/9 下午6:57, Tiezhu Yang 写道:
Add /proc/boardinfo to get mainboard and BIOS info easily on the Loongson
platform, this is useful to point out the current used mainboard type and
BIOS version when there exists problems related with hardware or firmware.
Hi Tiezhu,
You're touching
在 2020/10/8 23:20, Serge Semin 写道:
[...]
- add_memory_region(LOONGSON_HIGHMEM_START,
- highmemsize << 20, BOOT_MEM_RAM);
-
- add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
-
于 2020年10月2日 GMT+08:00 下午9:27:21, Thomas Bogendoerfer
写到:
>On Wed, Sep 23, 2020 at 07:02:54PM +0800, Jiaxun Yang wrote:
>>
>> +#ifdef CONFIG_CPU_LOONGSON64
>> +static int c0_compare_int_enable(struct clock_event_device *cd)
>> +{
>> +if (cpu_has_extime
s.txt,
Section "KERNEL I/O BARRIER EFFECTS"
Signed-off-by: Serge Semin
Cc: Maciej W. Rozycki
Reviewed-by: Jiaxun Yang
Based on #mipslinus discussions, I suspect this option can be selected by
most modern MIPS processors including all IMG/MTI cores,
Ingenic and Loongson.
Thanks.
在 2020/9/23 18:56, Peng Fan 写道:
From: Dengcheng Zhu
Support the MIPS architecture using the ins_ops association
method. With this patch, perf-annotate can work well on MIPS.
Testing it with a perf.data file collected on a mips machine:
$./perf annotate -i perf.data
:
options field of cpuinfo_mips was a single variable, it means
we can never have more than 64 options, while the diversity of MIPS
decided there will be more options.
Convert options to bitops based so we don't have to worry number
of options anymore.
Signed-off-by: Jiaxun Yang
---
arch/mips
Loongson64C and Loongson64G have extimer feature, which is a
timer sharing Cause.TI with cevt-r4k (named intimer).
To ensure the cevt-r4k's usability, we need to add a callback for
clock device to switch intimer.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/cpu-features.h | 4
It was missed when I was forking Loongson2ef from Loongson64 but
should be applied to Loongson2ef as march=loongson2f
will also enable Loongson MMI in GCC-9+.
Signed-off-by: Jiaxun Yang
Fixes: 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64")
Reported-by: Thomas Bogendoerfe
于 2020年9月19日 GMT+08:00 下午4:29:39, Youling Tang 写到:
>
>
>On 09/19/2020 03:02 PM, Jiaxun Yang wrote:
>>
>> 于 2020年9月19日 GMT+08:00 上午9:55:46, Youling Tang 写到:
>>> When the kernel crashkernel parameter is specified with just a size,
>>> we are supposed
于 2020年9月19日 GMT+08:00 上午9:55:46, Youling Tang 写到:
>When the kernel crashkernel parameter is specified with just a size,
>we are supposed to allocate a region from RAM to store the crashkernel.
>However, MIPS merely reserves physical address zero with no checking
>that there is even RAM there.
在 2020/9/17 20:41, Jinyang He 写道:
Hi, Huacai,
On 09/16/2020 01:39 PM, Huacai Chen wrote:
Hi, Jinyang,
On Tue, Sep 15, 2020 at 10:17 PM Jinyang He
wrote:
On 09/16/2020 09:33 AM, Jiaxun Yang wrote:
于 2020年9月15日 GMT+08:00 下午9:07:43, Jinyang He
写到:
Add loongson_kexec_prepare
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