On Thu, Apr 8, 2021 at 12:20 PM Rob Herring wrote:
>
> On Tue, Apr 06, 2021 at 02:25:49PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
> > >
> > > On Tue, Apr 06, 2021 at 01:26:51PM -0400, Jim Quinlan wrote:
> > > >
On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
>
> On Tue, Apr 06, 2021 at 01:26:51PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 12:47 PM Mark Brown wrote:
>
> > > No great problem with having these in the controller node (assming it
> > > accurately
On Tue, Apr 6, 2021 at 1:23 PM Mark Brown wrote:
>
> On Tue, Apr 06, 2021 at 12:59:16PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 12:34 PM Mark Brown wrote:
> > > On Thu, Apr 01, 2021 at 05:21:43PM -0400, Jim Quinlan wrote:
>
> > > This is broken
On Tue, Apr 6, 2021 at 12:47 PM Mark Brown wrote:
>
> On Thu, Apr 01, 2021 at 05:21:42PM -0400, Jim Quinlan wrote:
> > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> > allows optional regulators to be attached and controlled by the PCIe RC
On Tue, Apr 6, 2021 at 12:34 PM Mark Brown wrote:
>
> On Thu, Apr 01, 2021 at 05:21:43PM -0400, Jim Quinlan wrote:
>
> > + /* Look for specific pcie regulators in the RC DT node. */
> > + for_each_property_of_node(np, pp) {
> > +
and would be best handled by its driver, the device cannot be discovered
and probed unless its regulator is already turned on.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 83 +--
1 file changed, 78 insertions(+), 5 deletions(-)
diff --git a/d
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie
: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 122 ++
1 file changed, 122 insertions(+)
diff --git
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
power the EP device.
-- The brcmstb RC driver is modified to control these regulators
during probe, suspend, and resume.
-- 7216 type SOCs have additional error reporting HW and a
panic handler is added to dump its info.
-- A missing return value check is added.
Jim Quinlan (6):
r property in the pcie EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at
https://github.com/devicetree-org/dt-schema/pull/54
Signed-off-by: Jim Quinlan
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4
1 file changed, 4
Check for failure of clk_prepare_enable() on device resume.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops")
---
drivers/pci/controller/pcie-brcmstb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
On Tue, Mar 30, 2021 at 11:30 AM Mark Brown wrote:
>10.22.8.121
> On Tue, Mar 30, 2021 at 10:08:16AM -0500, Rob Herring wrote:
> > On Fri, Mar 26, 2021 at 03:18:59PM -0400, Jim Quinlan wrote:
>
> > > +pcie-ep@0,0 {
> > > +
/* Pmap_idx to avs pmap number */
const uint8_t pmap_idx_to_avs_id[20];
On Mon, Mar 29, 2021 at 1:16 PM Mark Brown wrote:
>
> On Mon, Mar 29, 2021 at 12:39:50PM -0400, Jim Quinlan wrote:
> > On Mon, Mar 29, 2021 at 12:25 PM Mark Brown
>
> > > Here you are fig
On Mon, Mar 29, 2021 at 12:25 PM Mark Brown
w./lib/python3.6/site-packages/dtschema/schemasrote:
>
> On Fri, Mar 26, 2021 at 03:19:00PM -0400, Jim Quinlan wrote:
>
> > + /* Now look for regulator supply properties */
> > + for_each_prope
On Fri, Mar 26, 2021 at 4:11 PM Bjorn Helgaas wrote:
>
> On Fri, Mar 26, 2021 at 03:19:00PM -0400, Jim Quinlan wrote:
> > Control of EP regulators by the RC is needed because of the chicken-and-egg
>
> Can you expand "EP"? Not sure if this refers to "endpoint&
: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 122 ++
1 file changed, 122 insertions(+)
diff --git
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie
The check was missing on PCIe resume.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops")
---
drivers/pci/controller/pcie-brcmstb.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/d
Control of EP regulators by the RC is needed because of the chicken-and-egg
situation: although the regulator is "owned" by the EP and would be best
handled on its driver, the EP cannot be discovered and probed unless its
regulator is already turned on.
Signed-off-by: Jim Quinlan
--
d resume.
-- 7216 type SOCs have additional error reporting HW and a
panic handler is added to dump its info.
-- A missing return value check is added.
Jim Quinlan (6):
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
PCI: brcmstb: Add control of EP voltage regulator
r property in the pcie EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at
https://github.com/devicetree-org/dt-schema/pull/54
Signed-off-by: Jim Quinlan
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 6 ++
1 file changed, 6
resume cycle; w/o using "rearm", the
"rescal" device will only ever fire once.
Of course for suspend/resume to work we also need to put the reset/rearm
calls in the suspend and resume routines.
Fixes: 740d6c3708a9 ("PCI: brcmstb: Add control of rescal reset")
Signed-off-b
ng.
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 reset is self de-asserting")
Fixes: c345ec6a50e9 ("ata: ahci_brcm: Support BCM7216 reset controller name")
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 46 ---
to reset after every resume from S2 or S3.
-- Split the use of "ahci" and "rescal" controllers in separate fields
to keep things simple.
v1 -- original
Jim Quinlan (2):
ata: ahci_brcm: Fix use of BCM7216 reset controller
PCI: brcmstb: Use reset/rearm instead of deassert/
PCI: brcmstb: Add control of rescal reset")
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/c
ng.
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 reset is self de-asserting")
Fixes: c345ec6a50e9 ("ata: ahci_brcm: Support BCM7216 reset controller name")
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 46 ---
s in separate fields
to keep things simple.
v1 -- original
Jim Quinlan (2):
ata: ahci_brcm: Fix use of BCM7216 reset controller
nPCI: brcmstb: Use reset/rearm instead of deassert/assert
drivers/ata/ahci_brcm.c | 46 +--
drivers/pci/controller
On Wed, Jan 6, 2021 at 2:42 PM Jim Quinlan wrote:
>
> -- Forwarded message -
> From: Bjorn Helgaas
> Date: Wed, Jan 6, 2021 at 2:19 PM
> Subject: Re: [PATCH v2 5/6] PCI: brcmstb: Add panic/die handler to RC driver
> To: Jim Quinlan
> Cc: , N
On Wed, Jan 6, 2021 at 4:30 AM Sudeep Holla wrote:
>
> On Tue, Jan 05, 2021 at 01:32:49PM -0500, Jim Quinlan wrote:
>
> [...]
>
> >
> > I don't think that is the case; the bottom routine,
> > do_wait_for_common(), decrements the x->done after a com
> From: Sudeep Holla
> Date: Tue, Jan 5, 2021 at 12:35 PM
> Subject: Re: [PATCH v4 2/2] firmware: arm_scmi: Augment SMC/HVC to allow
> optional interrupt
> To: Florian Fainelli
> Cc: Jim Quinlan , Sudeep Holla ,
> , , open
> list:SYSTEM CONTROL & POWER/MANAGEMEN
On Tue, Jan 5, 2021 at 9:01 AM Mark Brown wrote:
>
> On Mon, Jan 04, 2021 at 05:12:11PM -0500, Jim Quinlan wrote:
>
> > For us, the supplies are for the EP chip's power. We have the PCIe
> > controller turning them "on" for power-on/resume and "off" for
On Wed, Dec 9, 2020 at 10:07 AM Rob Herring wrote:
>
> On Mon, Nov 30, 2020 at 04:11:38PM -0500, Jim Quinlan wrote:
> > Quite similar to the regulator bindings found in "rockchip-pcie-host.txt",
> > this allows optional regulators to be attached and controll
. I agree with you -- thanks.
However, note that in function device_release() in
drivers/base/core.c there is this line:
kfree(dev->dma_range_map);
Won't this also be called if all of the appropriate drivers' probes
fail for this device, effecting a double kfree? Perhaps your patch
could also set "dev->dma_range_map" to NULL after calling kfree()?
Thanks much,
Jim Quinlan
Broadcom STB
Hi Sudeep,
Since RobH has reviewed patch 1/.2 and Florian has acked it, can you
please accept patches 1 & 2?
Thanks,
Jim Quinlan
Broadcom STB
On Tue, Dec 22, 2020 at 9:56 AM Jim Quinlan wrote:
>
> v4 -- s/message-serviced/a2p/ in the bindings commit message.
>-- Changed
Signed-off-by: Jim Quinlan
---
drivers/firmware/arm_scmi/smc.c | 38 -
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
index 82a82a5dc86a..fd41d436e34b 100644
--- a/drivers/firmware/arm_
In normal use of smc/hvc transport in SCMI the message completion is
indicated by the return of the SMC call. This commit provides for an
optional interrupt named "a2p" which is used instead to
indicate the completion of a message.
Signed-off-by: Jim Quinlan
---
Documentation/
ommit message, s/msg/message/, and remove extra WS on
"dt-bindings" commit (Sudeep)
-- Change interrupt name to "message-serviced", move irq assignent to end
of function. (Sudeep)
v1 -- original.
Jim Quinlan (2):
dt-bindings: arm: Add optional interrupt to smc
The Brcmstb PCIe RC uses a reset control "rescal" for certain chips. This
reset implements a "pulse reset" so it matches more the reset/rearm
calls instead of the deassert/assert calls.
Also, add reset_control calls in suspend/resume functions.
Signed-off-by: Jim Quinl
From: Jim Quinlan
This driver may use one of two resets controllers. Keep them in separate
variables to keep things simple. The reset controller "rescal" is shared
between the AHCI driver and the PCIe driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared()
v1 -- original
[1] Applied commit "reset: make shared pulsed reset controls re-triggerable"
found at git://git.pengutronix.de/git/pza/linux.git
branch reset/shared-retrigger
Jim Quinlan (2):
ata: ahci_brcm: Fix use of BCM7216 reset controller
PCI: brcmstb: use reset/re
In normal use of smc/hvc transport in SCMI the message completion is
indicated by the return of the SMC call. This commit provides for an
optional interrupt named "message-serviced" which is used instead to
indicate the completion of a message.
Signed-off-by: Jim Quinlan
---
Doc
of function. (Sudeep)
v1 -- original.
Jim Quinlan (2):
dt-bindings: arm: Add optional interrupt to smc/hvc SCMI transport
firmware: arm_scmi: Augment SMC/HVC to allow optional interrupt
.../devicetree/bindings/arm/arm,scmi.txt | 8
drivers/firmware/arm_scmi/smc.c |
Signed-off-by: Jim Quinlan
---
drivers/firmware/arm_scmi/smc.c | 38 -
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
index 82a82a5dc86a..fd41d436e34b 100644
--- a/drivers/firmware/arm_
On Mon, Dec 7, 2020 at 2:01 PM Rob Herring wrote:
>
> On Thu, Nov 12, 2020 at 12:56:26PM -0500, Jim Quinlan wrote:
> > In normal use of smc/hvc transport in SCMI the message completion is
> > indicated by the return of the SMC call. This commit provides for an
> >
On Tue, Dec 1, 2020 at 1:05 PM Bjorn Helgaas wrote:
>
> On Mon, Nov 30, 2020 at 04:11:42PM -0500, Jim Quinlan wrote:
> > Whereas most PCIe HW returns 0x on illegal accesses and the like,
> > by default Broadcom's STB PCIe controller effects an abort. This simple
>
The check was missing on PCIe resume.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index 3983d6c80769..64cf534e44d0
Control of EP regulators by the RC is needed because of the chicken-and-egg
situation: although the regulator is "owned" by the EP and would be best
handled on its driver, the EP cannot be discovered and probed unless its
regulator is already turned on.
Signed-off-by: Jim Quinlan
--
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index cbdb315d4b2f
: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 124 ++
1 file changed, 124 insertions(+)
diff --git a/drivers/pci/controller/pcie
reporting HW and a
panic handler is added to dump its info.
-- A missing return value check is added.
Jim Quinlan (6):
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
PCI: brcmstb: Add control of EP voltage regulator(s)
PCI: brcmstb: Do not turn off regulators if EP can
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
Quite similar to the regulator bindings found in "rockchip-pcie-host.txt",
this allows optional regulators to be attached and controlled by the
PCIe RC driver.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12
1 file changed, 12
On Thu, Nov 26, 2020 at 6:49 AM Mark Brown wrote:
>
> On Wed, Nov 25, 2020 at 02:24:19PM -0500, Jim Quinlan wrote:
>
> > + for (i = 0; i < PCIE_REGULATORS_MAX; i++) {
> > + ep_reg = devm_regulator_get_optional(dev,
> > ep_regulator_names[i]);
>
Control of EP regulators by the RC is needed because of the chicken-and-egg
situation: although the regulator is "owned" by the EP and would be best
handled on its driver, the EP cannot be discovered and probed unless its
regulator is already turned on.
Signed-off-by: Jim Quinlan
--
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 56 ---
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/pci
Quite similar to the regulator bindings found in "rockchip-pcie-host.txt",
this allows optional regulators to be attached and controlled by the
PCIe RC driver.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12
1 file changed, 12
.
-- A missing return value check is added.
Jim Quinlan (6):
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
PCI: brcmstb: Add control of EP voltage regulator(s)
PCI: brcmstb: Do not turn off regulators if EP can wake up
PCI: brcmstb: Give 7216 SOCs their own config type
PCI
: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 124 ++
1 file changed, 124 insertions(+)
diff --git a/drivers/pci/controller/pcie
The check was missing on PCIe resume.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index 469bbb0ebdd9..56c88d2b4f87
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index 9b46f0bc
On Mon, Nov 23, 2020 at 10:58 AM Jim Quinlan wrote:
>
> On Fri, Nov 20, 2020 at 2:45 PM Al Cooper wrote:
> >
> > From: Jim Quinlan
> >
> > This commit has of_platform_serial_probe() check specifically for the
> > "brcm,bcm7271-uart&quo
On Fri, Nov 20, 2020 at 2:45 PM Al Cooper wrote:
>
> From: Jim Quinlan
>
> This commit has of_platform_serial_probe() check specifically for the
> "brcm,bcm7271-uart" and whether its companion driver is enabled. If it
> is the case, and the clock provider is not
From: Jim Quinlan
This driver may use one of two resets controllers. Keep them in separate
variables to keep things simple. The reset controller "rescal" is shared
between the AHCI driver and the PCIe driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared()
v1 -- original
[1] Applied commit "reset: make shared pulsed reset controls re-triggerable"
found at git://git.pengutronix.de/git/pza/linux.git
branch reset/shared-retrigger
Jim Quinlan (2):
ata: ahci_brcm: Fix use of BCM7216 reset controller
PCI: brcmstb: use reset/re
The Brcmstb PCIe RC uses a reset control "rescal" for certain chips. This
reset implements a "pulse reset" so it matches more the reset/rearm
calls instead of the deassert/assert calls.
Also, add reset_control calls in suspend/resume functions.
Signed-off-by: Jim Quinl
On Thu, Nov 12, 2020 at 12:56 PM Jim Quinlan wrote:
>
> In normal use of smc/hvc transport in SCMI the message completion is
> indicated by the return of the SMC call. This commit provides for an
> optional interrupt named "message-serviced" which is used instead to
>
On Fri, Nov 20, 2020 at 6:14 AM Sudeep Holla wrote:
>
> On Thu, Nov 19, 2020 at 01:34:18PM -0500, Jim Quinlan wrote:
> > On Fri, Nov 13, 2020 at 10:12 AM Jim Quinlan
> > wrote:
> > >
> > > On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla wrote:
> > >
On Fri, Nov 13, 2020 at 10:12 AM Jim Quinlan wrote:
>
> On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla wrote:
> >
> > On Fri, Nov 13, 2020 at 09:26:43AM -0500, Jim Quinlan wrote:
> > > Hi, these are fast calls. Regards, Jim
> > >
> > >
> > &g
On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla wrote:
>
> On Fri, Nov 13, 2020 at 09:26:43AM -0500, Jim Quinlan wrote:
> > Hi, these are fast calls. Regards, Jim
> >
> >
> > On Fri, Nov 13, 2020 at 4:47 AM Sudeep Holla wrote:
> > >
> > > On Thu, Nov
Hi, these are fast calls. Regards, Jim
On Fri, Nov 13, 2020 at 4:47 AM Sudeep Holla wrote:
>
> On Thu, Nov 12, 2020 at 12:56:27PM -0500, Jim Quinlan wrote:
> > The SMC/HVC SCMI transport is modified to allow the completion of an SCMI
> > message to be indicated by an int
Signed-off-by: Jim Quinlan
---
drivers/firmware/arm_scmi/smc.c | 38 -
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
index 82a82a5dc86a..68ee6eb5fc27 100644
--- a/drivers/firmware/arm_
In normal use of smc/hvc transport in SCMI the message completion is
indicated by the return of the SMC call. This commit provides for an
optional interrupt named "message-serviced" which is used instead to
indicate the completion of a message.
Signed-off-by: Jim Quinlan
---
Doc
v2 -- Correct commit message, s/msg/message/, and remove extra WS on
"dt-bindings" commit (Sudeep)
-- Change interrupt name to "message-serviced", move irq assignent to end
of function. (Sudeep)
v1 -- original.
Jim Quinlan (2):
dt-bindings: arm: Add optional
On Wed, Nov 11, 2020 at 5:42 AM Sudeep Holla wrote:
>
> On Tue, Nov 10, 2020 at 01:38:19PM -0500, Jim Quinlan wrote:
> > The SMC/HVC SCMI transport is modified to allow the completion of an SCMI
> > message to be indicated by an interrupt rather than the return o
This change allows the SCMI "platform" to use the smc/hvc transport and to
optionally indicate the completion of an SCMI message with an interrupt.
This is in contrast to the nominal case where the return of the SMC call
indicates message completion.
Signed-off-by: Jim Quinlan
---
Doc
Signed-off-by: Jim Quinlan
---
drivers/firmware/arm_scmi/smc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
index 82a82a5dc86a..3bf935dbd00e 100644
--- a/drivers/firmware/arm_scmi/smc.c
+++
On Mon, Nov 9, 2020 at 5:05 AM Philipp Zabel wrote:
>
> Hi Jim,
>
> On Fri, 2020-11-06 at 14:17 -0500, Jim Quinlan wrote:
> > Before, only control_reset() was implemented. However, the reset core only
> > invokes control_reset() once in its lifetime. Beca
From: Jim Quinlan
This driver may use one of two resets controllers. Keep them in separate
variables to keep things simple. The reset controller "rescal" is shared
between the AHCI driver and the PCIe driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared()
and
having an empty control_assert() method.
Signed-off-by: Jim Quinlan
---
drivers/reset/reset-brcmstb-rescal.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-brcmstb-rescal.c
b/drivers/reset/reset-brcmstb-rescal.c
index b6f074d6a65f
to keep things simple.
v1 -- original
Jim Quinlan (2):
reset: brcmstb rescal: implement {de}assert() instead of reset()
ata: ahci_brcm: Fix use of BCM7216 reset controller
drivers/ata/ahci_brcm.c | 46 ++--
drivers/reset/reset-brcmstb-rescal.c |
On Thu, Nov 5, 2020 at 1:27 PM Sudeep Holla wrote:
>
> On Thu, Nov 05, 2020 at 10:28:25AM -0500, Jim Quinlan wrote:
> > On Thu, Nov 5, 2020 at 10:13 AM Rob Herring wrote:
> > >
> > > On Wed, Nov 4, 2020 at 4:04 PM Jim Quinlan
> > > wrote:
> > &
On Thu, Nov 5, 2020 at 10:13 AM Rob Herring wrote:
>
> On Wed, Nov 4, 2020 at 4:04 PM Jim Quinlan wrote:
> >
> > On Wed, Nov 4, 2020 at 4:50 PM Rob Herring wrote:
> > >
> > > On Thu, Oct 29, 2020 at 03:59:06PM -0400, Jim Quinlan wrote:
> > > > B
On Wed, Nov 4, 2020 at 4:50 PM Rob Herring wrote:
>
> On Thu, Oct 29, 2020 at 03:59:06PM -0400, Jim Quinlan wrote:
> > Bindings are added. Only one interrupt is needed because
> > we do not yet employ the SCMI p2a channel.
>
> I still don't understand what this is. To r
On Tue, Nov 3, 2020 at 2:38 PM Bjorn Helgaas wrote:
>
> On Mon, Nov 02, 2020 at 03:57:12PM -0500, Jim Quinlan wrote:
> > The variable 'tmp' is used multiple times in the brcm_pcie_setup()
> > function. One such usage did not initialize 'tmp' to the current value of
>
t;PCI: brcmstb: Add Broadcom STB PCIe host controller
driver")
Suggested-by: Rafał Miłecki
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcms
is
initiated with an ARM SMC call, but the return of this call does not
indicate the execution or completion of the message. Rather, the message's
completion is signaled by an interrupt.
Signed-off-by: Jim Quinlan
Signed-off-by: Florian Fainelli
---
drivers/mailbox/Kconfig | 12 +++
drivers
ailbox driver"
-- Drop label,unit address; changed title,description (RobH)
v1:
-- Original submission.
Jim Quinlan (2):
dt-bindings: Add bindings for BrcmSTB SCMI mailbox driver
mailbox: Add Broadcom STB mailbox driver
.../bindings/mailbox/brcm,brcmstb-mbox.ya
Bindings are added. Only one interrupt is needed because
we do not yet employ the SCMI p2a channel.
Signed-off-by: Jim Quinlan
---
.../bindings/mailbox/brcm,brcmstb-mbox.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings
On Fri, Oct 9, 2020 at 12:38 PM Sudeep Holla wrote:
>
> On Sat, Sep 19, 2020 at 03:22:30PM -0400, Jim Quinlan wrote:
> > only implements the agent-to-platform channel;
>
> In that case any reason why you can't reuse the existing smc transport
> for SCMI. It was added recentl
struct pci_host_bridge *bridge;
> > - struct device_node *fw_np;
> > +const struct pcie_cfg_data *data;
> > struct brcm_pcie *pcie;
> > int ret;
> >
>
> This is now a conflict between the pci tree and Linus' tree.
Hello,
Sorry, I did not foresee a conflict. Please keep both lines below.
struct device_node *fw_np;
const struct pcie_cfg_data *data;
Thank you,
Jim Quinlan
Broadcom STB
>
> --
> Cheers,
> Stephen Rothwell
smime.p7s
Description: S/MIME Cryptographic Signature
> [1.887183] lr : nand_scan_with_ids+0x1450/0x1470
Hi,
I'm having a hard time coming up with a theory regarding how a commit
concerning DMA offsets can affect the operation of a NAND driver that
appears not to use DMA or the dma-ranges property. Does anyone else
have some ideas, or
: b98f52bc6495 ("PCI: brcmstb: Add control of rescal reset")
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie
On Tue, Sep 29, 2020 at 5:31 PM Bjorn Helgaas wrote:
>
> On Mon, Sep 28, 2020 at 03:46:51PM -0400, Jim Quinlan wrote:
> > The Kconfig is modified so that the pcie_bus_config setting can be done at
> > build time in the same manner as the CONFIG_PCIEASPM_ choice. The
v2: Add more description text in the new Kconfig settings (Bjorn).
v1: Original
Jim Quinlan (1):
PCI: pcie_bus_config can be set at build time
drivers/pci/Kconfig | 56 +
drivers/pci/pci.c | 12 ++
2 files changed, 68 insertions
The Kconfig is modified so that the pcie_bus_config setting can be done at
build time in the same manner as the CONFIG_PCIEASPM_ choice. The
pci_bus_config setting may still be overridden by the bootline param.
Signed-off-by: Jim Quinlan
---
drivers/pci/Kconfig | 56
lock as noted by Florian Fainelli and suggested by
> > Jim Quinlan.
>
> Alex Dewar contributed another update suggestion.
>
> [PATCH v2] PCI: brcmstb: Add missing if statement and error path
> https://lore.kernel.org/linux-arm-kernel/20200921211623.33908-1-alex.dewa...@gmail.
_disable_unprepare(-cie->clk);" before the return. I am fine with
either what you have or implementing Florian's additional suggestion.
Thank you,
Jim Quinlan
Broadcom STB
> return ret;
>
> /* Take bridge out of reset so we can access the SERDES reg */
> --
> 2.28.0
>
smime.p7s
Description: S/MIME Cryptographic Signature
how this omission slipped by testing.
Thanks,
Jim Quinlan
Broadcom STB
On Mon, Sep 21, 2020 at 3:43 PM Florian Fainelli wrote:
>
> On 9/21/20 7:40 AM, Colin King wrote:
> > From: Colin Ian King
> >
> > The error return ret is not being check with an if statement and
&g
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