On Sat, Sep 19, 2020 at 3:32 PM Randy Dunlap wrote:
>
> Hi Jim,
>
> On 9/19/20 12:22 PM, Jim Quinlan wrote:
> > ---
> > drivers/mailbox/Kconfig | 12 +++
> > drivers/mailbox/Makefile | 2 +
> > drivers/mailbox/brcmstb-mailbox.c | 173 +
Bindings are added. Only one interrupt is needed because
we do not yet employ the SCMI p2a channel.
Signed-off-by: Jim Quinlan
---
.../bindings/mailbox/brcm,brcmstb-mbox.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings
is
initiated with an ARM SMC call, but the return of this call does not
indicate the execution or completion of the message. Rather, the message's
completion is signaled by an interrupt.
Signed-off-by: Jim Quinlan
Signed-off-by: Florian Fainelli
---
drivers/mailbox/Kconfig | 12 +++
drivers
ency on SMP (Florian)
Commit "mailbox: Add Broadcom STB mailbox driver"
-- Drop label,unit address; changed title,description (RobH)
v1:
-- Original submission.
Jim Quinlan (2):
dt-bindings: Add bindings for BrcmSTB SCMI mailbox driver
mailbox: Add Broadcom STB mailbox driv
is
initiated with an ARM SMC call, but the return of this call does not
indicate the execution or completion of the message. Rather, the message's
completion is signaled by an interrupt.
Signed-off-by: Jim Quinlan
Signed-off-by: Florian Fainelli
---
drivers/mailbox/Kconfig | 12 +++
drivers
Bindings are added. Only one interrupt is needed because
we do not yet employ the SCMI p2a channel.
Signed-off-by: Jim Quinlan
---
.../bindings/mailbox/brcm,brcmstb-mbox.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings
dress; changed title,description (RobH)
v1:
-- Original submission.
Jim Quinlan (2):
dt-bindings: Add bindings for BrcmSTB SCMI mailbox driver
mailbox: Add Broadcom STB mailbox driver
.../bindings/mailbox/brcm,brcmstb-mbox.yaml | 39
drivers/mailbox/Kconfig | 12
On Tue, Aug 25, 2020 at 4:16 AM Philipp Zabel wrote:
>
> On Mon, 2020-08-24 at 16:40 -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > A reset controller "rescal" is shared between the AHCI driver and the PCIe
> >
v2: Add more description text in the new Kconfig settings (Bjorn).
v1: Original
Jim Quinlan (1):
PCI: pcie_bus_config can be set at build time
drivers/pci/Kconfig | 56 +
drivers/pci/pci.c | 12 ++
2 files changed, 68 insertions
The Kconfig is modified so that the pcie_bus_config setting can be done at
build time in the same manner as the CONFIG_PCIEASPM_ choice. The
pci_bus_config setting may still be overridden by the bootline param.
Signed-off-by: Jim Quinlan
---
drivers/pci/Kconfig | 56
is
initiated with an ARM SMC call, but the return of this call does not
indicate the execution or completion of the message. Rather, the message's
completion is signaled by an interrupt.
Signed-off-by: Jim Quinlan
Signed-off-by: Florian Fainelli
---
drivers/mailbox/Kconfig | 13 +++
drivers
Bindings are added. Only one interrupt is needed because
we do not yet employ the SCMI p2a channel.
Signed-off-by: Jim Quinlan
---
.../bindings/mailbox/brcm,brcmstb-mbox.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings
On Thu, Sep 10, 2020 at 5:37 AM Thomas Bogendoerfer
wrote:
>
> On Tue, Sep 08, 2020 at 12:45:06PM -0400, Jim Quinlan wrote:
> > Currently, the example uasm code
> >
> > uasm_i_lui(p, tmp, 0xa000);
> >
> > issues a warning at Linux boot when the code
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/pcie-brcmstb.c
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Acked-by: Rob Herring
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert. Of course, PERST# is a PCIe asserted-low signal
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
hset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a function which depends upon the "dma-ranges" property of
the PCIe host controller. This is required for proper functionality
of
On Thu, Sep 10, 2020 at 12:17 PM Rob Herring wrote:
>
> On Mon, Aug 24, 2020 at 03:30:21PM -0400, Jim Quinlan wrote:
> > The Raspberry Pi (RPI) is currently the only chip using this driver
> > (pcie-brcmstb.c). There, only one memory controller is used, without an
&g
Hi Bjorn,
On Wed, Sep 9, 2020 at 10:25 PM Bjorn Helgaas wrote:
>
> On Tue, Sep 08, 2020 at 12:32:48PM -0400, Jim Quinlan wrote:
> > The Kconfig is modified so that the pcie_bus_config setting can be done at
> > build time in the same manner as the CONFIG_PC
On Thu, Sep 10, 2020 at 2:50 PM Rob Herring wrote:
>
> On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan
> wrote:
> >
> > On Thu, Sep 10, 2020 at 11:56 AM Rob Herring wrote:
> > >
> > > On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
> > &g
On Thu, Sep 10, 2020 at 3:08 PM Florian Fainelli wrote:
>
>
>
> On 9/10/2020 12:05 PM, Jim Quinlan wrote:
> > On Thu, Sep 10, 2020 at 2:50 PM Rob Herring wrote:
> >>
> >> On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan
> >> wrote:
> >>>
On Thu, Sep 10, 2020 at 11:56 AM Rob Herring wrote:
>
> On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
> > and resume. Now the PCIe driver may do
convert it to a
proper 16 bit unsigned integer.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/uasm.h | 2 +-
arch/mips/mm/uasm-micromips.c | 2 +-
arch/mips/mm/uasm-mips.c | 2 +-
arch/mips/mm/uasm.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/
The Kconfig is modified so that the pcie_bus_config setting can be done at
build time in the same manner as the CONFIG_PCIEASPM_ choice. The
pci_bus_config setting may still be overridden by the bootline param.
Signed-off-by: Jim Quinlan
---
drivers/pci/Kconfig | 40
On Mon, Sep 7, 2020 at 5:16 AM Lorenzo Pieralisi
wrote:
>
> On Thu, Aug 27, 2020 at 09:29:59AM -0400, Jim Quinlan wrote:
> > On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig wrote:
> > >
> > > On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote:
>
On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig wrote:
>
> On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote:
> > Hi,
> >
> > On 8/24/2020 12:30 PM, Jim Quinlan wrote:
> >>
> >> Patchset Summary:
> >>Enhance a PCIe hos
From: Jim Quinlan
A reset controller "rescal" is shared between the AHCI driver and the PCIe
driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared() to handle this sharing.
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 reset is self de-asserting")
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
g needed for the PCIe driver to work [1].
There have been many changes to the DMA and OF subsystems since that
time, making a cleaner and less intrusive patchset possible. This
patchset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar o
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
The Kconfig is modified so that the pcie_bus_config setting can be done at
build time in the same manner as the CONFIG_PCIEASPM_ choice. The
pci_bus_config setting may still be overridden by the bootline param.
Signed-off-by: Jim Quinlan
---
drivers/pci/Kconfig | 40
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
possible. This
patchset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a function which depends upon the "dma-ranges" property of
the PCIe host controller. This is required for pr
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
convert it to a
proper 16 bit unsigned integer.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/uasm.h | 2 +-
arch/mips/mm/uasm-micromips.c | 2 +-
arch/mips/mm/uasm-mips.c | 2 +-
arch/mips/mm/uasm.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
possible. This
patchset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a function which depends upon the "dma-ranges" property of
the PCIe host controller. This is required for pr
fls64
On Sat, Aug 1, 2020 at 1:39 PM Nicolas Saenz Julienne
wrote:
>
> Hi Jim,
>
> On Fri, 2020-07-24 at 16:33 -0400, Jim Quinlan wrote:
> > The Raspberry Pi (RPI) is currently the only chip using this driver
> > (pcie-brcmstb.c). There, only one memory con
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
1].
There have been many changes to the DMA and OF subsystems since that
time, making a cleaner and less intrusive patchset possible. This
patchset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a functi
From: Jim Quinlan
A reset controller "rescal" is shared between the AHCI driver and the PCIe
driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared() to handle this sharing.
Signed-off-by: Jim Quinlan
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 r
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
From: Jim Quinlan
A reset controller "rescal" is shared between the AHCI driver and the PCIe
driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared() to handle this sharing.
Signed-off-by: Jim Quinlan
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 r
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal
possible. This
patchset implements a generalization of "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a function which depends upon the "dma-ranges" property of
the PCIe host controller. This is required for proper functio
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
f "dev->dma_pfn_offset", except
that instead of a single scalar offset it provides for multiple
offsets via a function which depends upon the "dma-ranges" property of
the PCIe host controller. This is required for proper functionality
of the BrcmSTB PCIe controller and possibly s
in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely
used in the EP role and its system of mapping memory is an artifact that
requires multiple dma-ranges regions.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 68
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie
From: Jim Quinlan
A reset controller "rescal" is shared between the AHCI driver and the PCIe
driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared() to handle this sharing.
Signed-off-by: Jim Quinlan
Fixes: 272ecd60a636 ("ata: ahci_brcm: BCM7216 r
101 - 200 of 487 matches
Mail list logo
