eds to be aware of this. For
> example, after a suspend userspace needs to recalibrate it's offset
> between CPU and GPU time.
>
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
> drivers/gpu/drm/msm/msm_drv.c | 1 +
> driv
On Wed, Mar 24, 2021 at 06:23:52PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> They were reading a counter that was configured to ALWAYS_COUNT (ie.
> cycles that the GPU is doing something) rather than ALWAYS_ON. This
> isn't the thing that userspace is looking for.
Acked-by
jcrouse at codeaurora.org ha started bouncing. Redirect to a
more permanent address.
Signed-off-by: Jordan Crouse
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 85b93cdefc87..8c489cb1d1ce 100644
--- a/.mailmap
+++ b/.mailmap
@@ -165,6 +165,7 @@ Johan
pinning")
Link: https://lkml.kernel.org/r/20210323133254.33ed9...@omen.home.shazbot.org/
Reported-by: Alex Williamson
Suggested-by: Alex Williamson
Signed-off-by: Daniel Jordan
---
Alex, I couldn't immediately find a way to trigger this bug, but I can
run your test case if you like.
This i
Hi Alex,
Alex Williamson writes:
> I've found a bug in this patch that we need to fix. The diff is a
> little difficult to follow,
It was an awful diff, I remember...
> so I'll discuss it in the resulting function below...
>
> (1) Imagine the user has passed a vaddr range that alternates
> callback
> sched_cpu_activate() hence it may not be observable by sched_setaffinity() if
> it is called immediately after uevent.
>
> Out of line uevent can be avoided if we will ensure that cpuset_hotplug_work
> has run to completion using cpuset_wait_for_hotplug() after onlining th
Alexey Klimov writes:
> The first section of comment seems problematic to me with regards to such
> move:
>
> * As this needs to hold the cpu maps lock it's impossible
> * to call device_offline() because that ends up calling
> * cpu_down()
Andrey Ryabinin writes:
> static int cpuacct_stats_show(struct seq_file *sf, void *v)
> {
...
> for_each_possible_cpu(cpu) {
> u64 *cpustat = per_cpu_ptr(ca->cpustat, cpu)->cpustat;
>
> - val[CPUACCT_STAT_USER] += cpustat[CPUTIME_USER];
> -
Andrey Ryabinin writes:
> cpuacct has 2 different ways of accounting and showing user
> and system times.
>
> The first one uses cpuacct_account_field() to account times
> and cpuacct.stat file to expose them. And this one seems to work ok.
>
> The second one is uses cpuacct_charge() function
_usec looks ok now.
Reviewed-by: Daniel Jordan
Tested-by: Daniel Jordan
Andrey Ryabinin writes:
> cpuacct.stat in no-root cgroups shows user time without guest time
> included int it. This doesn't match with user time shown in root
> cpuacct.stat and /proc//stat.
Yeah, that's inconsistent.
> Make account_guest_time() to add user time to cgroup's cpustat to
> fix
().
Fix it up in vfio_pin_page_external(). Found by inspection.
Fixes: be16c1fd99f4 ("vfio/type1: Change success value of vaddr_get_pfn()")
Signed-off-by: Daniel Jordan
---
I couldn't test this due to lack of hardware.
drivers/vfio/vfio_iommu_type1.c | 8 +++-
1 file changed, 7 insert
On Tue, Mar 02, 2021 at 12:17:24PM +, Robin Murphy wrote:
> On 2021-02-25 17:51, Jordan Crouse wrote:
> > Call report_iommu_fault() to allow upper-level drivers to register their
> > own fault handlers.
> >
> > Signed-off-by: Jordan Crouse
> > ---
> >
On Fri, Feb 26, 2021 at 11:48:13AM -0700, Jordan Crouse wrote:
> On Fri, Feb 26, 2021 at 11:24:52AM -0600, Bjorn Andersson wrote:
> > On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
> >
> > > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
> >
extra
function hooks added on. I'm not sure if there is a clever way to figure out how
to meld the implementation hooks at runtime but the alternative is to just make
sure that the adreno-smmu static struct calls the same quirks as its generic
partner.
Jordan
> > Suggested-by: Akhil P Oommen
&g
th apps
> and adreno smmu implementing "arm,mmu-500", so the adreno smmu
> implementation is never reached because the current sequence checks
> for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
> specific impl and we never reach adreno smmu specific im
return qcom_smmu_create(smmu, _smmu_impl);
> -
> if (of_device_is_compatible(np, "qcom,adreno-smmu"))
> return qcom_smmu_create(smmu, _adreno_smmu_impl);
>
> + if (of_match_node(qcom_smmu_impl_of_match, np))
> + retu
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
Call report_iommu_fault() to allow upper-level drivers to register their
own fault handlers.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers
a solid base that we can expand on later for even more
extensive GPU side page fault debugging capabilities.
v3: Always clear FSR even if the target driver is going to handle resume
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support
Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19 +
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2
KED_VM exceeded
I didn't test vfio_pin_page_external() because there was no readily available
hardware, but the changes there are pretty minimal.
Daniel Jordan (3):
vfio/type1: Change success value of vaddr_get_pfn()
vfio/type1: Prepare for batched pinning with struct vfio_batch
vfio/type1:
allocate memory.
vaddr_get_pfn() becomes vaddr_get_pfns() to prepare for handling
multiple pages, though for now only one page is stored in the pages
array.
Signed-off-by: Daniel Jordan
---
drivers/vfio/vfio_iommu_type1.c | 71 +++--
1 file changed, 58 insertions(+), 13
.
Signed-off-by: Daniel Jordan
---
drivers/vfio/vfio_iommu_type1.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index ec9fd95a138b..7abaaad518a6 100644
--- a/drivers/vfio/vfio_iommu_type1.c
Jordan
---
drivers/vfio/vfio_iommu_type1.c | 135 +---
1 file changed, 89 insertions(+), 46 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index b7247a2fc87e..cec2083dd556 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b
Alex Williamson writes:
> This might not be the first batch we fill, I think this needs to unwind
> rather than direct return.
So it does, well spotted. And it's the same thing with the ENODEV case
farther up.
> Series looks good otherwise.
Thanks for going through it!
t; is a way to test this.
>
> If there is no other harm, we can put a hard dependency on CONFIG_NVMEM.
I'm not sure if we want to go this far given the squishiness about module
dependencies. As far as I know we are the only driver that uses this seriously
on QCOM SoCs and this is on
Alexey Klimov writes:
> int cpu_device_up(struct device *dev)
Yeah, definitely better to do the wait here.
> int cpuhp_smt_disable(enum cpuhp_smt_control ctrlval)
> {
> - int cpu, ret = 0;
> + struct device *dev;
> + cpumask_var_t mask;
> + int cpu, ret;
> +
> + if
On Thu, Feb 11, 2021 at 06:50:28PM +0530, Akhil P Oommen wrote:
> On 2/10/2021 6:22 AM, Jordan Crouse wrote:
> >Most a6xx targets have security issues that were fixed with new versions
> >of the microcode(s). Make sure that we are booting with a safe version of
> >the mic
nks. I feel silly that I missed that.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages and fix typos
Signed-off-by: Jordan Crouse
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 67
Alexey Klimov writes:
> When a CPU offlined and onlined via device_offline() and device_online()
> the userspace gets uevent notification. If, after receiving "online" uevent,
> userspace executes sched_setaffinity() on some task trying to move it
> to a recently onlined CPU, then it often fails
Peter Zijlstra writes:
> On Thu, Feb 04, 2021 at 12:50:34PM +, Alexey Klimov wrote:
>> On Thu, Feb 4, 2021 at 9:46 AM Peter Zijlstra wrote:
>> >
>> > On Thu, Feb 04, 2021 at 01:01:57AM +, Alexey Klimov wrote:
>> > > @@ -1281,6 +1282,11 @@ static int cpu_up(unsigned int cpu, enum
>> > >
Jordan
---
drivers/vfio/vfio_iommu_type1.c | 133 +---
1 file changed, 88 insertions(+), 45 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index c26c1a4697e5..ac59bfc4e332 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b
allocate memory.
vaddr_get_pfn() becomes vaddr_get_pfns() to prepare for handling
multiple pages, though for now only one page is stored in the pages
array.
Signed-off-by: Daniel Jordan
---
drivers/vfio/vfio_iommu_type1.c | 71 +++--
1 file changed, 58 insertions(+), 13
.
Signed-off-by: Daniel Jordan
---
drivers/vfio/vfio_iommu_type1.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 0b4dedaa9128..4d608bc552a4 100644
--- a/drivers/vfio/vfio_iommu_type1.c
Daniel Jordan (3):
vfio/type1: change success value of vaddr_get_pfn()
vfio/type1: prepare for batched pinning with struct vfio_batch
vfio/type1: batch page pinning
drivers/vfio/vfio_iommu_type1.c | 213 +++-
1 file changed, 154 insertions(+), 59 deletions(-)
base-
ally in for a nasty surprise due to the
> > > > mismatched outer-cacheability attributes.
> > > >
> > >
> > > Can't we add the syscached memory type similar to what is done on android?
> >
> > Maybe. How does the GPU driver map these things on the CPU si
On Thu, Jan 28, 2021 at 11:17:16AM -0800, Eric Anholt wrote:
> On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote:
> >
> > On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote:
> > > We were using the same force-poweron bit in the two codepaths, so they
>
On Fri, Jan 22, 2021 at 12:53:17PM +, Robin Murphy wrote:
> On 2021-01-22 12:41, Will Deacon wrote:
> >On Tue, Nov 24, 2020 at 12:15:58PM -0700, Jordan Crouse wrote:
> >>Call report_iommu_fault() to allow upper-level drivers to register their
> >>own fault ha
Alexey Klimov writes:
> Daniel, thank you for taking a look. I don't mind reviewing+testing
> another approach that you described.
Eh, I like yours better :)
>> Absent further discussion, Alexey, do you plan to post another version?
>
> I plan to update this patch and re-send in the next couple
Daniel Jordan writes:
> Peter Zijlstra writes:
>>> The nature of this bug is also described here (with different consequences):
>>> https://lore.kernel.org/lkml/20200211141554.24181-1-qais.you...@arm.com/
>>
>> Yeah, pesky deadlocks.. someone was going to try ag
een made when porting:
> 4 is the value that's supposed to be passed, but
> log2(4) = 2. Changing the value to 16 (= 2^4) fixes
> the issue.
I like keeping it in human readable values because its easier to visually
identify how many registers are saved without doing math.
Reviewed-by
On Wed, Jan 13, 2021 at 07:33:38PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
On Wed, Jan 13, 2021 at 07:33:39PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
> Content-Transfer-Encoding: 8bit
>
> The functions cgroup_threads_start and cgroup_procs_start are almost
You meant cgroup_threads_write and cgroup_procs_write.
> kernel/cgroup/cgroup.c | 55 +++---
> 1 file changed, 14 insertions(+), 41 deletions(-)
Ok, sure, that's a good thing.
Reviewed-by: Daniel Jordan
y
> along with the required fuse details for a618 gpu.
Reviewed-by: Jordan Crouse
> Signed-off-by: Akhil P Oommen
> ---
> Changes from v2:
> 1. Made the changes a6xx specific to save space.
> Changes from v1:
> 1. Added the changes to support a618 sku to the series.
>
has the support.
> >>
> >
> >From the PoV of bringing up new a6xx, we should probably consider that
> >some of them may not *yet* have LLCC enabled. I have an 8cx laptop
> >and once I find time to get the display working, the next step would
> >be bri
ioacchino Del Regno
>
Yep, I can see how this would be not ideal.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> 2 files changed, 17 insertions(+), 9 deletions(-)
&
nvmem_cell_put(cell);
> + DRM_DEV_ERROR(dev,
> + "failed to read speed-bin. Some OPPs may not be
> supported by hardware");
> + goto done;
> + }
> +
> + supp_hw = fuse_to_supp_hw(dev, r
Liang Li writes:
> The first version can be found at: https://lkml.org/lkml/2020/4/12/42
>
> Zero out the page content usually happens when allocating pages with
> the flag of __GFP_ZERO, this is a time consuming operation, it makes
> the population of a large vma area very slowly. This patch
Peter Zijlstra writes:
>> The nature of this bug is also described here (with different consequences):
>> https://lore.kernel.org/lkml/20200211141554.24181-1-qais.you...@arm.com/
>
> Yeah, pesky deadlocks.. someone was going to try again.
I dug up the synchronous patch
Alexey Klimov writes:
> I also in doubts if we need cpuset_wait_for_hotplug() in
> cpuhp_online_cpu_device()
> since an online uevent is sent there too.
We do need it there if we go with this fix. Your reproducer hits the
same issue when it's changed to exercise smt/control instead of
Jason Gunthorpe writes:
> On Fri, Dec 04, 2020 at 03:05:46PM -0500, Daniel Jordan wrote:
>> Well Alex can correct me, but I went digging and a comment from the
>> first type1 vfio commit says the iommu API didn't promise to unmap
>> subpages of previous mappings, so doin
Pavel Tatashin writes:
> On Fri, Dec 4, 2020 at 3:06 PM Daniel Jordan
> wrote:
>>
>> Jason Gunthorpe writes:
>>
>> > On Wed, Dec 02, 2020 at 08:34:32PM -0500, Pavel Tatashin wrote:
>> >> What I meant is the users of the interface do it increme
Jason Gunthorpe writes:
> On Wed, Dec 02, 2020 at 08:34:32PM -0500, Pavel Tatashin wrote:
>> What I meant is the users of the interface do it incrementally not in
>> large chunks. For example:
>>
>> vfio_pin_pages_remote
>>vaddr_get_pfn
>> ret = pin_user_pages_remote(mm, vaddr, 1,
On Wed, Dec 02, 2020 at 08:53:51PM +0530, Akhil P Oommen wrote:
> On 11/30/2020 10:32 PM, Jordan Crouse wrote:
> >On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a
no_gpu *adreno_gpu,
> const struct adreno_gpu_funcs *funcs, int nr_rings)
> @@ -899,6 +963,7 @@ int adreno_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
> struct adreno_platform_config *config = dev->platform_data;
> stru
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19 +
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2
Call report_iommu_fault() to allow upper-level drivers to register their
own fault handlers.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b
on later for even more
extensive GPU side page fault debugging capabilities.
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 406100f3da08066c00105165db8520bbc7694a36
Gitweb:
https://git.kernel.org/tip/406100f3da08066c00105165db8520bbc7694a36
Author:Daniel Jordan
AuthorDate:Thu, 12 Nov 2020 12:17:11 -05:00
ed later..
> > > drm_ioctl() dispatch is well prepared for extending ioctls.
> > >
> > > And I assume there should be some validation that the range is aligned
> > > to cache-line? Or can we flush a partial cache line?
> > >
> >
> > The range is inte
return 0;
> }
>
> +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
> + size_t range_start, size_t range_end)
> +{
> + struct msm_gem_object *msm_obj = to_msm_bo(obj);
> + struct device *dev = msm_obj->base.dev->dev;
> +
On
> +static void update_inactive(struct msm_gem_object *msm_obj)
> +{
> + struct msm_drm_private *priv = msm_obj->base.dev->dev_private;
> +
> + mutex_lock(>mm_lock);
> + WARN_ON(msm_obj->active_count != 0);
> +
> + list_del_init(_obj->mm_list);
&
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
> On 11/12/2020 10:05 PM, Jordan Crouse wrote:
> >On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a
; Cc: David Airlie
> Cc: Daniel Vetter
> Cc: linux-arm-...@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: freedr...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file change
cpuset's effective mask, not just the top one.
Fixes: 0ccea8feb980 ("cpuset: Make generate_sched_domains() work with
partition")
Signed-off-by: Daniel Jordan
Cc: Johannes Weiner
Cc: Li Zefan
Cc: Peter Zijlstra
Cc: Prateek Sood
Cc: Tejun Heo
Cc: Waiman Long
Cc: cgro...@vger.kernel.org
C
>info = adreno_info(config->rev);
> @@ -910,6 +975,10 @@ int adreno_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
>
> adreno_gpu_config.nr_rings = nr_rings;
>
> + ret = adreno_set_supported_hw(dev, adreno_gpu);
> + if (ret)
Peter Zijlstra writes:
> On Thu, Oct 29, 2020 at 02:18:45PM -0400, Daniel Jordan wrote:
>> rebuild_sched_domains_locked() prevented the race during the cgroup2
>> cpuset series up until the Fixes commit changed its check. Make the
>> check more robust so that it can detect
]] *ERROR* timeout waiting for space in
> ringbuffer 0
>
> in the resume path.
>
> Fixes: d3a569fccfa0 ("drm/msm: a6xx: Use WHERE_AM_I for eligible targets")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++
ged")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/
Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19 +
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2
on later for even more
extensive GPU side page fault debugging capabilities.
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm: Improve the a6xx page fault handler
drivers/gpu/drm/msm/adreno
Call report_iommu_fault() to allow upper-level drivers to register their
own fault handlers.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
/git/will/linux.git for-joerg/arm-smmu/updates to pick up
system cache patches and devm_realloc() updates. Use a function hook to
modify / write sctlr
v18: No deltas in this patchset since the last go-around for 5.10 [1].
[1] https://patchwork.freedesktop.org/series/81393/
Jordan Crouse
.
Signed-off-by: Jordan Crouse
Reviewed-by: Rob Herring
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm
if it wishes.
Co-developed-by: Jordan Crouse
Signed-off-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 +
drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 -
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
3 files changed, 19
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +
arch/arm64/boot/dts
hardware can implement
per-instance pagetables.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 151 -
drivers
;
> Fixes: 8907afb476ac ("drm/msm: Allow a5xx to mark the RPTR shadow as
> privileged")
> Signed-off-by: Marijn Suijten
> Tested-by: AngeloGioacchino Del Regno
>
Way better. Thanks for doing this.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno
On Mon, Nov 02, 2020 at 06:18:45PM +, Robin Murphy wrote:
> On 2020-11-02 17:14, Jordan Crouse wrote:
> >From: Rob Clark
> >
> >For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
> >pending translations are not terminated on iova fault. Otherwise
&g
On Mon, Nov 02, 2020 at 10:08:23AM -0700, Jordan Crouse wrote:
> On Thu, Oct 29, 2020 at 05:26:08PM +, Will Deacon wrote:
> > On Tue, Oct 27, 2020 at 04:34:04PM -0600, Jordan Crouse wrote:
> > > This short series adds support for the adreno-smmu implementation of the
>
per-instance pagetables in the drm/msm driver.
No deltas in this patchset since the last go-around for 5.10 [1].
[1] https://patchwork.freedesktop.org/series/81393/
Jordan Crouse (3):
iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU
dt-bindings: arm-smmu: Add compatible string
hardware can implement
per-instance pagetables.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 151 -
drivers
-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +
arch/arm64/boot/dts
.
Signed-off-by: Jordan Crouse
Reviewed-by: Rob Herring
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm
On Thu, Oct 29, 2020 at 05:26:08PM +, Will Deacon wrote:
> On Tue, Oct 27, 2020 at 04:34:04PM -0600, Jordan Crouse wrote:
> > This short series adds support for the adreno-smmu implementation of the
> > arm-smmu driver and the device-tree bindings to turn on the
cpuset's effective mask, not just the top one.
Fixes: 0ccea8feb980 ("cpuset: Make generate_sched_domains() work with
partition")
Signed-off-by: Daniel Jordan
Cc: Johannes Weiner
Cc: Li Zefan
Cc: Peter Zijlstra
Cc: Prateek Sood
Cc: Tejun Heo
Cc: Waiman Long
Cc: cgro...@vger.kernel.org
C
.
Signed-off-by: Jordan Crouse
Reviewed-by: Rob Herring
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm
-off-by: Jordan Crouse
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
hardware can implement
per-instance pagetables.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 151 -
drivers
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +
arch/arm64/boot/dts
in this patchset since the last go-around for 5.10 [1].
[1] https://patchwork.freedesktop.org/series/81393/
Jordan Crouse (3):
iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
arm: dts: qcom: sm845: Set the compatible string
On 10/27/20 12:46 AM, Nico Pache wrote:
> On Wed, Jul 08, 2020 at 03:51:40PM -0400, Daniel Jordan wrote:
> > (I was away for a while)
> >
> > On Thu, Jul 02, 2020 at 11:55:48AM -0400, Nico Pache wrote:
> > > Allow padata_do_multithreaded functio
On Tue, Oct 27, 2020 at 12:38:02PM +0530, Sai Prakash Ranjan wrote:
> On 2020-10-27 00:24, Jordan Crouse wrote:
> >This is an extension to the series [1] to enable the System Cache (LLC)
> >for
> >Adreno a6xx targets.
> >
> >GPU targets with an MMU-500 attached
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