Hi Zhang Qing,
On 12/31/2015 10:14 PM, zhangqing wrote:
make rtc-rk8xx.c compatible for all pmic chips.
for pmic chips(rk808\rk807\rk816\rk818) in the future.
The commit message will be better like this:
Rename the file to rtc-rk8xx.c to compatible other Rockchip PMIC chips
like
+
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", _smp_ops);
Reviewed-by: Kever Yang
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mdelay(1); /* ensure the cpus other than cpu0 to startup */
+
writel(virt_to_phys(rockchip_secondary_startup),
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
Reviewed-by: Kever Yang
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+* prior to having the power domain disabled.
+*/
+ mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
}
Reviewed-by: Kever Yang
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(virt_to_phys(rockchip_secondary_startup),
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
Reviewed-by: Kever Yang kever.y...@rock-chips.com
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/WFE state
+* prior to having the power domain disabled.
+*/
+ mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
}
Reviewed-by: Kever Yang kever.y...@rock-chips.com
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};
+
CPU_METHOD_OF_DECLARE(rk3066_smp, rockchip,rk3066-smp, rockchip_smp_ops);
Reviewed-by: Kever Yang kever.y...@rock-chips.com
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Hi Caesar,
Subject typo WIF/WFI.
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1
Hi Caesar,
Subject typo WIF/WFI.
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang w...@rock-chips.com
---
Hi Caesar,
On 04/08/2015 06:18 PM, Caesar Wang wrote:
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
Serien-cc: linux-kernel@vger.kernel.org
Hi Caesar,
On 04/08/2015 06:18 PM, Caesar Wang wrote:
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu x...@rock-chips.com
Signed-off-by: zhengxing zhengx...@rock-chips.com
Signed-off-by: Caesar Wang
Hi Daniel,
On 01/25/2015 05:42 PM, Daniel Lezcano wrote:
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This
Hi Daniel,
On 01/25/2015 05:42 PM, Daniel Lezcano wrote:
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This
Hi Paul,
I think you need this patch to fix the problem:
usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/
Thanks,
- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent
Hi Paul,
I think you need this patch to fix the problem:
usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/
Thanks,
- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent
Hi Roy,
Why you send two patches with different commit message but the same
change,
you should use V2 for a new patch.
On 12/03/2014 09:46 PM, LiYunzhi wrote:
From: lyz
You don't need the From for the patches from yourself.
Add a driver for the Rockchip SoC internal USB2.0 PHY.
This
Hi Roy,
Why you send two patches with different commit message but the same
change,
you should use V2 for a new patch.
On 12/03/2014 09:46 PM, LiYunzhi wrote:
From: lyz l...@rock-chips.com
You don't need the From for the patches from yourself.
Add a driver for the Rockchip SoC
Hi Roger,
Please use the --in-reply-to option for patches other than 0/4
with the git send-email.
On 11/25/2014 05:07 PM, Roger Chen wrote:
Roger Chen (4):
patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
patch2: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
Hi Chris,
On 11/25/2014 05:37 PM, Chris Zhong wrote:
The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.
I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In
Hi Roger,
The subject should prefix:
Arm: dts: rockchip: enable ...
On 11/25/2014 05:09 PM, Roger Chen wrote:
enable gmac in rk3288-evb-rk808.dts
Signed-off-by: Roger Chen
---
arch/arm/boot/dts/rk3288-evb-rk808.dts | 22 ++
1 file changed, 22 insertions(+)
diff
Hi Roger,
The Subject should use below prefix:
ARM: dts: rockchip: add gmac info for rk3288
On 11/25/2014 05:08 PM, Roger Chen wrote:
add gmac info in rk3288.dtsi for GMAC driver
Signed-off-by: Roger Chen
---
arch/arm/boot/dts/rk3288.dtsi | 59 +
Hi Roger,
This patch should be split into two patch, one for clock ID definition,
one for mac related clocks update.
The Subject for clk-rk3288.c should use below prefix:
clk: rockchip: modify clock for mac ...
On 11/25/2014 05:08 PM, Roger Chen wrote:
modify CRU config for GMAC driver
Hi Roger,
This patch should be split into two patch, one for clock ID definition,
one for mac related clocks update.
The Subject for clk-rk3288.c should use below prefix:
clk: rockchip: modify clock for mac ...
On 11/25/2014 05:08 PM, Roger Chen wrote:
modify CRU config for GMAC driver
Hi Roger,
The Subject should use below prefix:
ARM: dts: rockchip: add gmac info for rk3288
On 11/25/2014 05:08 PM, Roger Chen wrote:
add gmac info in rk3288.dtsi for GMAC driver
Signed-off-by: Roger Chen roger.c...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 59
Hi Roger,
The subject should prefix:
Arm: dts: rockchip: enable ...
On 11/25/2014 05:09 PM, Roger Chen wrote:
enable gmac in rk3288-evb-rk808.dts
Signed-off-by: Roger Chen roger.c...@rock-chips.com
---
arch/arm/boot/dts/rk3288-evb-rk808.dts | 22 ++
1 file changed, 22
Hi Chris,
On 11/25/2014 05:37 PM, Chris Zhong wrote:
The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.
I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In
Hi Roger,
Please use the --in-reply-to option for patches other than 0/4
with the git send-email.
On 11/25/2014 05:07 PM, Roger Chen wrote:
Roger Chen (4):
patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
patch2: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
Hi Jay,
On 11/19/2014 04:09 PM, Jianqun Xu wrote:
Patch is from Sonny Rao
Here should be,
From: Sonny Rao
- Kever
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Hi Jay,
On 11/19/2014 04:09 PM, Jianqun Xu wrote:
Patch is from Sonny Rao sonny...@chromium.org
Here should be,
From: Sonny Rao sonny...@chromium.org
- Kever
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More
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li
Signed-off-by: Kever Yang
---
Changes in v2
Hi Julius,
On 11/18/2014 05:21 AM, Julius Werner wrote:
On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device
This patch is no complete, Sorry for that, I will upload a new version
tomorrow.
- Kever
On 11/17/2014 09:14 PM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b
We will need a pll to support all kinds of clock rate requirement
for HDMI(from DCLK_VOP0) which may change the rate at run time.
In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP0 can select npll
as parent.
Signed-off-by: Kever Yang
Kever Yang (2):
clk: rockchip: leave npll for VOP0 only
arm: dts: rockchip: select npll as parent of DCLK_VOP0
arch/arm/boot/dts/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 24
2 files changed, 14 insertions(+), 12 deletions(-)
--
1.9.1
On 11/14/2014 11:55 PM, Alan Stern wrote:
On Thu, 13 Nov 2014, Julius Werner wrote:
Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li
Signed-off-by: Kever Yang
---
drivers/usb
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang
On 11/14/2014 11:55 PM, Alan Stern wrote:
On Thu, 13 Nov 2014, Julius Werner wrote:
Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all
Kever Yang (2):
clk: rockchip: leave npll for VOP0 only
arm: dts: rockchip: select npll as parent of DCLK_VOP0
arch/arm/boot/dts/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 24
2 files changed, 14 insertions(+), 12 deletions(-)
--
1.9.1
We will need a pll to support all kinds of clock rate requirement
for HDMI(from DCLK_VOP0) which may change the rate at run time.
In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP0 can select npll
as parent.
Signed-off-by: Kever Yang
The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
This patch is no complete, Sorry for that, I will upload a new version
tomorrow.
- Kever
On 11/17/2014 09:14 PM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
Hi Julius,
On 11/18/2014 05:21 AM, Julius Werner wrote:
On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang kever.y...@rock-chips.com wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang
Hi
On 11/14/2014 09:46 AM, Mike Turquette wrote:
Looking through the clock-tree there are a lot more components possibly
> >>using
> >>(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
> >>hevc,
> >>gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
>
Hi
On 11/14/2014 09:46 AM, Mike Turquette wrote:
Looking through the clock-tree there are a lot more components possibly
using
(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
hevc,
gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
reserving
the npll
This patch adds document for how to use the opetion property
assigned-clock-force-rates.
We may use this property to force update a clock setting.
Signed-off-by: Kever Yang
---
Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions
if the rate is not changed by now.
This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.
Signed-off-by: Kever Yang
---
drivers/clk/clk-conf.c | 33 -
1 file changed
When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.
Kever Yang (2):
clk: add property for force to update clock setting
dt-bindings: clk: add document
Hi Heiko,
On 11/07/2014 05:06 AM, Heiko Stübner wrote:
Hi Kever,
Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:
we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk
- clk_otgphy0 - USB PHY OTG
- clk_otgphy1 - USB PHY host0
- clk_otgphy2 - USB PHY host1
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk
Hi Heiko,
On 11/07/2014 05:06 AM, Heiko Stübner wrote:
Hi Kever,
Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:
we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3
When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.
Kever Yang (2):
clk: add property for force to update clock setting
dt-bindings: clk: add document
if the rate is not changed by now.
This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/clk-conf.c | 33
This patch adds document for how to use the opetion property
assigned-clock-force-rates.
We may use this property to force update a clock setting.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
1 file changed, 5
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index
for it so that we can use in dts.
Signed-off-by: Kever Yang
---
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock
According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk
p0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5,
GFLAGS),
The H/PCLK_VIO2_H2P is some kind of bus clock for a ahb2apb bridge
inside the VIO,
it should be on when some of VIO logic is working, but it is not easy to
assign these
two clocks to module driver. I think it is reasonable to mark
Doug,
On 11/13/2014 07:22 AM, Doug Anderson wrote:
Kever,
On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we
Doug,
On 11/13/2014 07:22 AM, Doug Anderson wrote:
Kever,
On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After
with
CLK_IGNORE_UNUSED
tag so far.
Reviewed-by: Kever Yang kever.y...@rock-chips.com
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Please read the FAQ
According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b
for it so that we can use in dts.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang
Acked-by: Paul Zimmerman
---
Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case
Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode
Hi Julius,
On 11/07/2014 06:11 AM, Julius Werner wrote:
On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can
Hi Julius,
On 11/07/2014 06:11 AM, Julius Werner wrote:
On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case
Changes in v2:
- update commit
On 11/06/2014 02:22 PM, Caesar Wang wrote:
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: Jack Dai
Hi Caesar,
On 11/06/2014 02:22 PM, Caesar Wang wrote:
Signed-off-by: Jack Dai
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
pls detail the reason why you need to add all the clocks into
power-controller node.
---
Changes in v8:
- DTS go back to v2
Changes in v7: None
Changes
Hi Caesar,
On 11/06/2014 02:22 PM, Caesar Wang wrote:
Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: jinkun.hong jinkun.h...@rock-chips.com
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
pls detail the reason why you need to add all the clocks into
power-controller node.
On 11/06/2014 02:22 PM, Caesar Wang wrote:
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: Jack
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang
---
Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work
drivers/usb/dwc2/hcd.c | 78 +++---
1 file changed, 67 insertions(+), 11 deletions
:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic
hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1
hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc
Signed-off-by: Kever Yang
---
Changes in v2:
- update the commit message
:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic
hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1
hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work
drivers/usb/dwc2/hcd.c | 78 +++---
1 file changed, 67 insertions
Hi Doug,
On 11/05/2014 05:32 AM, Doug Anderson wrote:
Kever
On Fri, Oct 31, 2014 at 2:29 AM, Kever Yang wrote:
This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v5:
- take CLK_IGNORE_UNUSED tag out of EMMC and UART2
- take CLK_IGNORE_UNUSED tag out of pclk_publ*, pclk_ddrupctl*
- add Doug's
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
---
Changes in v5:
- take CLK_IGNORE_UNUSED tag out of EMMC and UART2
- take
Hi Doug,
On 11/05/2014 05:32 AM, Doug Anderson wrote:
Kever
On Fri, Oct 31, 2014 at 2:29 AM, Kever Yang kever.y...@rock-chips.com wrote:
This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0
The HDMI clock is actually provide by DCLK_VOP0, so we need this
patch to handle the HDMI clock correctly
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk
clk-for-next
Kever Yang (5):
clk: rockchip: add some clock rate into rate table for rk3288
clk: divider: make clk_divider_recalc/set_rate available
clk: rockchip: introduce the div_ops handling for composite branches
clk: rockchip: add the vop_determine_rate for vop dclock
clk: rockchip
This patch makes these two function available for other file,
which may help to make costom usage of clock divider type.
Signed-off-by: Kever Yang
---
drivers/clk/clk-divider.c| 4 ++--
include/linux/clk-provider.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git
to change the NPLL's output
and always make CPLL not change.
This patch add vop_determinate_rate as a div_ops to handle
the HDMI clock things.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 69 +++
1 file changed, 69 insertions(+)
diff --git
106.5
1280x800 60 83.5
1024x768 60 65
800x600 60 40
800x600 56 36
640x480 60 25.175
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/rockchip
Rockchip Socs have a lot of clock node registered as composite
branch which include mux, divider and gate, most of them use
the same ops handling callback, we still need special ops
handling for some special clock node and this patch make it
possible.
Signed-off-by: Kever Yang
---
drivers/clk
106.5
1280x800 60 83.5
1024x768 60 65
800x600 60 40
800x600 56 36
640x480 60 25.175
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Rockchip Socs have a lot of clock node registered as composite
branch which include mux, divider and gate, most of them use
the same ops handling callback, we still need special ops
handling for some special clock node and this patch make it
possible.
Signed-off-by: Kever Yang kever.y...@rock
to change the NPLL's output
and always make CPLLGPLL not change.
This patch add vop_determinate_rate as a div_ops to handle
the HDMI clock things.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 69 +++
1 file changed, 69
clk-for-next
Kever Yang (5):
clk: rockchip: add some clock rate into rate table for rk3288
clk: divider: make clk_divider_recalc/set_rate available
clk: rockchip: introduce the div_ops handling for composite branches
clk: rockchip: add the vop_determine_rate for vop dclock
clk: rockchip
The HDMI clock is actually provide by DCLK_VOP0, so we need this
patch to handle the HDMI clock correctly
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk
This patch makes these two function available for other file,
which may help to make costom usage of clock divider type.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/clk-divider.c| 4 ++--
include/linux/clk-provider.h | 4
2 files changed, 6 insertions(+), 2
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang
---
Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock
Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock
Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag
This patch adds suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang
---
drivers/usb/dwc2/hcd.c | 74 ++
1 file changed, 63 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index fa49c72
|- hclk_sdio1
|- hclk_emmc
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 7a0741d..e1106ad 100644
--- a/drivers/clk
|- hclk_sdio1
|- hclk_emmc
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 7a0741d..e1106ad 100644
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