.org
[3] -> http://lore.kernel.org/r/20210222112314.10772-1-kis...@ti.com
[4] -> http://lore.kernel.org/r/20210310112745.3445-1-kis...@ti.com
Kishon Vijay Abraham I (6):
phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel
phy: ti: j721e-wiz: Delete "clk_div_sel&q
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Peter Rosin
Acked-by: Rob Herring
---
include/dt-bindings/mux/ti-serdes.h | 5 +
1
Add bindings for AM64 SERDES Wrapper.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/ti,phy-j721e-wiz.yaml| 4
include/dt-bindings/phy/phy-ti.h | 21 +++
2 files changed, 25 insertions(+)
create mode 100644 include/dt-bindings/phy/phy-ti.h
Add binding for refclk driver used to route the refclk out of torrent
SERDES.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/phy/phy-cadence-torrent.yaml | 20 ---
include/dt-bindings/phy/phy-cadence-torrent.h | 2 ++
2 files changed, 19
Menon so that he can merge
USB3 DT patches.
Changes from [1]:
*) Reverted back to adding compatible under enum.
[1] -> http://lore.kernel.org/r/20210222112314.10772-1-kis...@ti.com
Kishon Vijay Abraham I (3):
dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES
Wrapper
Hi Swapnil,
On 09/03/21 7:51 pm, Swapnil Kashinath Jakhade wrote:
> Hi Kishon,
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: Monday, February 22, 2021 4:53 PM
>> To: Kishon Vijay Abraham I ; Vinod Koul
>> ; Rob Herring ; Peter
+Vinod
Hi Aswath,
On 10/03/21 12:27 pm, Aswath Govindraju wrote:
> Hi Nishanth,
>
> On 01/03/21 8:52 pm, Nishanth Menon wrote:
>> On 11:21-20210301, Aswath Govindraju wrote:
>>> The following series of patches, add USB support for AM64.
>>>
>>> This series of patches depends on,
>>>
m.pdf
>
> Fixes: cd48ce86a4d0 ("arm64: dts: ti: k3-j721e-common-proc-board: Add support
> for SD card UHS modes")
> Signed-off-by: Aswath Govindraju
Reviewed-by: Kishon Vijay Abraham I
> ---
>
> Changes since v1:
> - Corrected the fixes tag to latest commit that ma
Hi Vinod,
On 16/11/20 1:00 pm, Vinod Koul wrote:
> On 03-11-20, 09:25, Kishon Vijay Abraham I wrote:
>> From: Faiz Abbas
>>
>> Serdes lanes might be shared between multiple cores in some usecases
>> and its not possible to lock PLLs for both the lanes indepe
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 9 +
1 file changed, 5
kis...@ti.com
[3] -> https://lore.kernel.org/r/20210222114030.26445-1-kis...@ti.com
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the
connector
dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64
SoC
dt-bindings: PCI: t
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml| 11 +++
1 file changed, 7 insertions
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 40 ++--
1 file changed, 37 insertions
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml| 17 -
include/dt-bindings/phy/phy-cadence.h | 4
2 files
commit 44d30d622821("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().
Fixes: 44d30d622821("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Ki
Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 271 ++-
2 files changed, 267 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 432832bdbd16..23d5382c34ed
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
---
d
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnod
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9.
25943.ga1790...@robh.at.kernel.org
[5] -> https://lore.kernel.org/r/20210304044122.15166-1-kis...@ti.com
Kishon Vijay Abraham I (13):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: ti: j721e-wiz: Invoke wiz_init() before
of_platform_device_create()
phy: cadence: cadence-sierra: Create PHY only for
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy
Hi Swapnil,
On 06/03/21 1:17 am, Swapnil Kashinath Jakhade wrote:
> Hi Kishon,
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: Thursday, March 4, 2021 10:11 AM
>> To: Kishon Vijay Abraham I ; Vinod Koul
>> ; Rob Herring ; Philipp
Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).
Signed-off-by: Kishon Vijay Abraham I
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 207 --
drivers/pci/controller/cadence/pcie-cadence.h
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 44 +++---
.../pci/controller/dwc/pcie
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
*) Fixed the error check in pci-epc-core.c
Changes from v1:
*) Re-based and Re-worked to latest kernel 5.10.0-rc2+ (now has generic
binding for EP)
[1] -> http://lore.kernel.org/r/20191231113534.30405-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/20201112175358.2653-1-kis...@ti.com
Kishon
Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint
Add binding to specify virtual function (associated with each physical
function) in endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-ep.yaml | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci
pcie_setup() was invoked. Fix the sequence here.
Fixes: 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-ep.c | 44 ++-
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/driver
Hi Rob,
On 22/02/21 4:53 pm, Kishon Vijay Abraham I wrote:
> Add bindings for AM64 SERDES Wrapper.
I've fixed all your comments provided in the previous version. Can you
review this and give your ACKs please?
Best Regards,
Kishon
>
> Signed-off-by: Kishon Vijay
Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 267 ++-
2 files changed, 265 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 432832bdbd16..23d5382c34ed
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml| 17 -
include/dt-bindings/phy/phy-cadence.h | 4
2 files
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
---
d
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/dri
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9.
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnod
590-1-kis...@ti.com
[4] -> http://lore.kernel.org/r/20210108025943.ga1790...@robh.at.kernel.org
Kishon Vijay Abraham I (13):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: ti: j721e-wiz: Invoke wiz_init() before
of_platform_device_create()
phy: cadence: cadence-sierra: Cre
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 40 ++--
1 file changed, 37 insertions
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().
Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by:
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c
t;
> Fixes: e6dc10f200da ("arm64: dts: ti: j721e-main: Add SDHCI nodes")
> Signed-off-by: Aswath Govindraju
Reviewed-by: Kishon Vijay Abraham I
Thanks
Kishon
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 17 -
> 1 file changed, 16 insertions(+),
Hi Leon,
On 22/02/21 1:30 pm, Steen Hegelund wrote:
> Hi Leon,
>
> On Sun, 2021-02-21 at 07:59 +0200, Leon Romanovsky wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>> know the content is safe
>>
>> On Thu, Feb 18, 2021 at 05:14:49PM +0100, Steen Hegelund wrote:
>>>
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml| 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller
115658.2795-1-kis...@ti.com
[2] -> https://lore.kernel.org/r/20210104124103.30930-1-kis...@ti.com
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the
connector
dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64
SoC
dt-b
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 9 +
1 file changed, 5 insertions(+), 4 deletions
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml| 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b
as a clock, so that platforms like AM642 EVM can
enable it.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index f9299dcdbdb7
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 39 +++---
1 file changed, 36 insertions(+), 3
nt
DT node and model the clocks within the driver.
Model the mux clocks without device tree input for AM64x SoC. Don't
remove the earlier design since DT nodes for J7200 and J721e are already
upstreamed.
[1] -> http://lore.kernel.org/r/20210108025943.ga1790...@robh.at.kernel.org
Signed-off-by:
efclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 202 +-
1 file changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-to
j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 956a93d96d9b..1a4e09a394a8
] -> https://lore.kernel.org/r/20201224114250.1083-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/20210108025943.ga1790...@robh.at.kernel.org
Kishon Vijay Abraham I (9):
dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES
Wrapper
dt-bindings: phy: cadence-torrent: Add binding for re
Add bindings for AM64 SERDES Wrapper.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/ti,phy-j721e-wiz.yaml| 10 ++---
include/dt-bindings/phy/phy-ti.h | 21 +++
2 files changed, 28 insertions(+), 3 deletions(-)
create mode 100644 include/dt
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Peter Rosin
---
include/dt-bindings/mux/ti-serdes.h | 5 +
1 file changed, 5
wiz_clk_div_sel" and
"struct wiz_clk_mux_sel" and make them point to constant data.
So far no issues are observed since both these structures are not
accessed outside the probe.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 75 +++---
Add binding for refclk driver used to route the refclk out of torrent
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-torrent.yaml | 20 ---
include/dt-bindings/phy/phy-cadence-torrent.h | 2 ++
2 files changed, 19 insertions(+), 3 deletions
Hi,
On 16/02/21 2:07 pm, Steen Hegelund wrote:
> Hi Andrew and Kishon,
>
> On Mon, 2021-02-15 at 15:07 +0100, Andrew Lunn wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>> know the content is safe
>>
>> On Mon, Feb 15, 2021 at 05:25:1
Hi Steen,
On 12/02/21 6:35 pm, Steen Hegelund wrote:
> Hi Kishon,
>
> On Fri, 2021-02-12 at 17:02 +0530, Kishon Vijay Abraham I wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>> know the content is safe
>>
>> Hi Steen,
>>
>&
On 12/02/21 1:02 am, Jan Kiszka wrote:
> From: Jan Kiszka
>
> This is demanded by the parent binding of ti,am654-pcie-rc, see
> Documentation/devicetree/bindings/pci/designware-pcie.txt.
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Kishon Vijay Abraham I
> ---
> a
> +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c
> @@ -723,7 +723,6 @@ static void ntb_epf_pci_remove(struct pci_dev *pdev)
> ntb_unregister_device(>ntb);
> ntb_epf_cleanup_isr(ndev);
> ntb_epf_deinit_pci(ndev);
> - kfree(ndev);
> }
Reviewed-by: Kishon Vijay Abraham I
>
> static const struct ntb_epf_data j721e_data = {
>
Hi Steen,
On 10/02/21 2:22 pm, Steen Hegelund wrote:
> Provide new phy configuration interfaces for media type and speed that
> allows allows e.g. PHYs used for ethernet to be configured with this
> information.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> Reviewed-by:
Hi Peter,
On 10/02/21 3:33 pm, Péter Ujfalusi wrote:
> Hi Kishon,
>
> On 2/9/21 2:02 PM, Kishon Vijay Abraham I wrote:
>> bcdma_get_*() and udma_get_*() checks if bchan/rchan/tchan/rflow is
>> already allocated by checking if it has a NON NULL value. For the
>> err
Hi Peter,
On 09/02/21 5:53 pm, Péter Ujfalusi wrote:
> Hi Kishon,
>
> On 2/9/21 11:00 AM, Kishon Vijay Abraham I wrote:
>> bcdma_get_*() and udma_get_*() checks if bchan/rchan/tchan/rflow is
>> already allocated by checking if it has a NON NULL value. For the
>> err
"dmaengine: ti: New driver for K3 UDMA")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/dma/ti/k3-udma.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 298460438bb4.
"dmaengine: ti: New driver for K3 UDMA")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/dma/ti/k3-udma.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 298460438bb4.
Hi Lorenzo, Rob,
On 12/01/21 12:45 pm, Kishon Vijay Abraham I wrote:
>
>
> On 30/12/20 5:35 pm, Nadeem Athani wrote:
>> Cadence controller will not initiate autonomous speed change if strapped
>> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
&
Hi Lorenzo,
On 04/02/21 10:39 pm, Lorenzo Pieralisi wrote:
> On Thu, Feb 04, 2021 at 07:15:39PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Lorenzo,
>>
>> On 04/02/21 3:28 pm, Lorenzo Pieralisi wrote:
>>> On Tue, Feb 02, 2021 at 12:12:55PM -0800, Randy Dunlap wrot
int/functions/pci-epf-ntb.o: in function
>> `epf_ntb_add_cfs':
>> pci-epf-ntb.c:(.text+0x1b): undefined reference to
>> `config_group_init_type_name'
>>
>> Fixes: 7dc64244f9e9 ("PCI: endpoint: Add EP function driver to provide NTB
>> functionality")
>>
64 bit BAR while
returning the first free unreserved BAR.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epc-core.c
b/drivers/pci/endpoint/pci-epc-co
Add specification for the *PCI NTB* function device. The endpoint function
driver and the host PCI driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/endpoint/index.rst | 1 +
.../PCI/endpoint/pci-ntb-function.rst
Add binding documentation for pci-ntb endpoint function that helps in
adding and configuring pci-ntb endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/function/binding/pci-ntb.rst | 38 +++
Documentation/PCI/endpoint/index.rst | 1 +
2 files
directly write to the physical address (in outbound
region) of the other interface to ring doorbell using MSI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 41 +
include/linux/pci-epc.h | 8 ++
2 files changed, 49
Modify pci_epc_get_next_free_bar() and pci_epc_get_first_free_bar() to
return error values if there are no free BARs available.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 2 ++
drivers/pci/endpoint/pci-epc-core.c | 12
Remove unused pci_epf_match_device() function added in pci-epf-core.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 16
include/linux/pci-epf.h | 2 --
2 files changed, 18 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epf
ops to be populated by the function driver if it has to
expose any function specific attributes and pci_epf_type_add_cfs() to
be invoked by pci-ep-cfs.c when sub-directory to main function directory
is created.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c |
Add documentation to help users use pci-epf-ntb function driver and
existing host side NTB infrastructure for NTB functionality.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Randy Dunlap
---
Documentation/PCI/endpoint/index.rst | 1 +
Documentation/PCI/endpoint/pci-ntb
Add TI J721E device to the pci id database. Since this device has
a configurable PCIe endpoint, it could be used with different
drivers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 -
include/linux/pci_ids.h | 1 +
2 files changed, 1 insertion(+), 1
to the user.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 23 +++
include/linux/pci-epf.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c
b/drivers/pci/endpoint/pci-ep-cfs.c
index
device has configurable number of memory windows
(Max 4), configurable number of doorbell (Max 32), and configurable
number of scratch-pad registers.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Dave Jiang
---
drivers/ntb/hw/Kconfig | 1 +
drivers/ntb/hw/Makefile | 1
Implement ->msi_map_irq() ops in order to map physical address to
MSI address and return MSI data.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Joseph
---
.../pci/controller/cadence/pcie-cadence-ep.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/driv
ace).
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Joseph
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
b/drivers/pci/controller/cadence/pcie-cadence-ep.c
in
Add a new endpoint function driver to provide NTB functionality
using multiple PCIe endpoint instances.
Signed-off-by: Kishon Vijay Abraham I
[a...@arndb.de: Select configfs dependency]
Signed-off-by: Arnd Bergmann
[yebi...@huawei.com: Fix unused but set variables]
Signed-off-by: Ye Bin
[geert
te a single EPC device with a EPF device will continue to work.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/pci-endpoint-cfs.rst | 10 ++
drivers/pci/endpoint/pci-ep-cfs.c | 147 ++
2 files changed, 157 insertions(+)
diff --git a/Documentat
http://lore.kernel.org/r/20210104152909.22038-1-kis...@ti.com
[13] -> http://lore.kernel.org/r/20210129124313.28549-1-kis...@ti.com
Kishon Vijay Abraham I (17):
Documentation: PCI: Add specification for the *PCI NTB* function
device
PCI: endpoint: Make *_get_first_free_bar() take into a
. This is in
preparation for adding NTB endpoint function driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 11 ++--
drivers/pci/endpoint/pci-ep-cfs.c | 6 +-
drivers/pci/endpoint/pci-epc-core.c | 47 +++
drivers/pci
Add an API to get the next unreserved BAR starting from a given BAR
number that can be used by the endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 26 ++
include/linux/pci-epc.h | 2 ++
2 files changed, 24
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