Hi Martin,
On 28/08/19 2:08 AM, Martin Blumenstingl wrote:
> Hello,
>
> On Tue, Aug 27, 2019 at 5:09 AM Chuan Hua, Lei
> wrote:
>>
>> Hi Martin,
>>
>> Thanks for your feedback. Please check the comments below.
>>
>> On 8/27/2019 5:15 AM, Martin Blumenstingl wrote:
>>> Hello,
>>>
>>> On Mon, Aug
ssing of_node_put() to a bunch of drivers using
for_each_available_child_of_node()
*) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
CP110 COMPHY
*) Other misc fixes and cleanup
Signed-off-by: Kishon Vijay Abraham I
Hi,
(Fixed Lorenzo's email address. All the patches in the series have wrong email
id)
On 23/08/19 8:09 AM, Xiaowei Bao wrote:
>
>
>> -Original Message-
>> From: Kishon Vijay Abraham I
>> Sent: 2019年8月22日 19:44
>> To: Xiaowei Bao ; bhelg..
On 22/07/19 12:53 PM, Neil Armstrong wrote:
> On 10/07/2019 07:04, Joe Perches wrote:
>> Arguments are supposed to be ordered high then low.
>>
>> Signed-off-by: Joe Perches
>> ---
>> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff
On 27/07/19 5:34 PM, Martin Blumenstingl wrote:
> Various Lantiq (now Intel) SoCs contain one or more PCIe controllers
> and PHYs.
> This adds a driver for the PCIe PHYs found on the Lantiq VRX200 and
> ARX300 SoCs. GRX390 should also be supported as far as I can tell,
> but I don't have any of
Hi,
On 22/08/19 4:52 PM, Xiaowei Bao wrote:
> The different PCIe controller in one board may be have different
> capability of MSI or MSIX, so change the way of getting the MSI
> capability, make it more flexible.
please use different pci_epc_features table for different boards.
Thanks
Kishon
>
Hi Sasha,
On 06/08/19 9:20 PM, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a "Fixes:" tag,
> fixing commit: 885bd765963b phy: qcom-qmp: Correct READY_STATUS poll break
> condition.
>
> The bot has tested the following trees:
Hi,
On 16/08/19 8:28 AM, Xiaowei Bao wrote:
>
>
>> -Original Message-
>> From: Andrew Murray
>> Sent: 2019年8月15日 19:54
>> To: Xiaowei Bao
>> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
>> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
>> shawn...@kernel.org
On 13/08/19 11:58 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR2 and BAR4 is 64bit, this is determined by hardware,
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiaowei Bao
Acked-by: Kishon Vijay Abraha
On 13/08/19 8:23 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
Do you mean BAR2 instead of BAR3 here?
Thanks
Kishon
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiao
ernel.org;
>> linux-kernel@vger.kernel.org; gustavo.pimen...@synopsys.com;
>> jingooh...@gmail.com; bhelg...@google.com; robh...@kernel.org;
>> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
>> ; lorenzo.pieral...@arm.com; M.h. Lian
>> ; Kishon Vijay Abraham I ;
>> Gabrie
> Cc: Roger Quadros
> Cc: Kishon Vijay Abraham I
> Signed-off-by: Stephen Boyd
> ---
>
> Please ack so I can take this through clk tree
Acked-by: Kishon Vijay Abraham I
>
> drivers/phy/ti/phy-am654-serdes.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletion
Hi Marek,
On 19/07/19 5:51 PM, Marek Szyprowski wrote:
> Hi Kishon,
>
> On 2019-07-19 12:04, Kishon Vijay Abraham I wrote:
>> Hi Marek,
>>
>> On 19/07/19 3:22 PM, Marek Szyprowski wrote:
>>> Commit 36914111e682 ("drivers: phy: add calibrate method"
Lorenzo,
On 11/06/19 10:08 AM, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 10/06/19 11:13 PM, Rob Herring wrote:
>> On Tue, Jun 4, 2019 at 7:19 AM Kishon Vijay Abraham I wrote:
>>>
>>> Export of_platform_device_create_pdata() to be used by drivers to
>&g
ticular the config options) that triggers
> this error would not hurt.
>
> Kishon please let me know if I can merge it (ACK it if so).
Acked-by: Kishon Vijay Abraham I
>
> Thanks,
> Lorenzo
>
>> Reported-by: Hulk Robot
>> Signed-off-by: YueHaibing
>> ---
&
Hi Greg,
On 01/07/19 3:44 PM, Greg Kroah-Hartman wrote:
> On Thu, Jun 27, 2019 at 06:46:50PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Greg,
>>
>> On 21/06/19 12:50 PM, Kishon Vijay Abraham I wrote:
>>>
>>>
>>> On 21/06/19 12:10 PM, Greg Kroah-H
-off-by: Kishon Vijay Abraham I
Bjorn Andersson (3):
dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
phy: qcom: Add Qualcomm PCIe2 PHY driver
phy: qcom-qmp: Correct READY_STATUS poll break condition
Guido
Hi Greg,
On 21/06/19 12:50 PM, Kishon Vijay Abraham I wrote:
>
>
> On 21/06/19 12:10 PM, Greg Kroah-Hartman wrote:
>> On Fri, Jun 21, 2019 at 11:41:26AM +0530, Kishon Vijay Abraham I wrote:
>>> Hi Greg,
>>>
>>> On 12/06/19 3:57 PM, Kishon Vijay Abrah
On 24/06/19 6:30 PM, Neil Armstrong wrote:
> Hi Kishon,
>
> On 05/06/2019 11:02, Neil Armstrong wrote:
>> Locking is not needed for the phy_g12a_usb3_pcie_cr_bus_read/write() and
>> currently it causes the following BUG because of the usage of the
>> regmap_read_poll_timeout() running in spinlo
Hi Vidya,
On 21/06/19 2:51 PM, Vidya Sagar wrote:
> Cleanup DBI read and write APIs by removing "__" (underscore) from their
> names as there are no no-underscore versions and the underscore versions
> are already doing what no-underscore versions typically do.
>
> Signed-off-by: Vidya Sagar
> -
On 21/06/19 12:10 PM, Greg Kroah-Hartman wrote:
> On Fri, Jun 21, 2019 at 11:41:26AM +0530, Kishon Vijay Abraham I wrote:
>> Hi Greg,
>>
>> On 12/06/19 3:57 PM, Kishon Vijay Abraham I wrote:
>>> Hi Greg,
>>>
>>> Please find the updated pull r
Hi Greg,
On 12/06/19 3:57 PM, Kishon Vijay Abraham I wrote:
> Hi Greg,
>
> Please find the updated pull request for 5.2 -rc cycle. Here I dropped
> the patch that added "static" for a function to fix sparse warning.
>
> I'm also sending the patches along wit
Hi,
On 24/05/19 9:31 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 24/05/19 5:53 PM, Fabio Estevam wrote:
>> Hi Kishon,
>>
>> On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote:
>>>
>>> This adds support for the Mixel DPHY as found on i.MX8 CPUs bu
This driver provides support for the programming required
> for each P2U that is going to be used for a PCIe controller.
One minor comment below. With that fixed
Acked-by: Kishon Vijay Abraham I
>
> Signed-off-by: Vidya Sagar
> ---
> Changes since [v9]:
> * Used _relaxed(
ed-by: Rob Herring
> Acked-by: Thierry Reding
Acked-by: Kishon Vijay Abraham I
> ---
> Changes since [v9]:
> * None
>
> Changes since [v8]:
> * None
>
> Changes since [v7]:
> * None
>
> Changes since [v6]:
> * None
>
> Changes since [v5]:
> * Ad
Hi,
On 14/06/19 6:08 PM, Marc Gonzalez wrote:
> + Doug (who is familiar with usleep_range quirks)
>
> On 14/06/2019 11:50, Vivek Gautam wrote:
>
>> On 6/13/2019 5:02 PM, Marc Gonzalez wrote:
>>
>>> readl_poll_timeout() calls usleep_range() to sleep between reads.
>>> usleep_range() doesn't work
Hi Lorenzo,
On 18/06/19 7:58 PM, Lorenzo Pieralisi wrote:
> On Tue, Jun 18, 2019 at 04:21:17PM +0530, Vidya Sagar wrote:
>
> [...]
>
>>> 2) It is not related to this patch but I fail to see the reasoning
>>> behind the __ in __dw_pci_read_dbi(), there is no no-underscore
>>> equivalent s
ng is problematic and does not follow the rules.
> It needs to be fixed, or you may face deadlocks. See below.
>
> On 2019-04-05 11:08, Kishon Vijay Abraham I wrote:
>> Add a new SERDES driver for TI's AM654x SoC which configures
>> the SERDES only for PCIe. Support fo U
Hi,
On 13/06/19 1:22 PM, Peter Rosin wrote:
> Hi,
>
> On 2019-06-13 06:57, Kishon Vijay Abraham I wrote:
>> Hi Peter,
>>
>> On 13/06/19 4:20 AM, Peter Rosin wrote:
>>> Hi!
>>>
>>> [I know this has already been merged upstream, but I only just
From: Thierry Reding
The Tegra210 SoC has four inputs that consume power in order to supply
the PLLs that drive the various USB, PCI and SATA pads.
Signed-off-by: Thierry Reding
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/tegra/xusb
"phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: Colin Ian King
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/ph
power supplies to be enabled by xusb-tegra124
*) Move Tegra210 PLL power supplies to be enabled by xusb-tegra210
*) Minor fixes: fix memory leaks at error path and addresses coverity.
Signed-off-by: Kishon Vijay Abraham I
Colin Ian
its
job already.
Fixes: 415060b21f31 ("phy: usb: phy-brcm-usb: Add ability to force DRD mode to
host or device")
Signed-off-by: Florian Fainelli
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/broadcom/phy-brcm-usb.c | 8
1 file changed, 8 insertions(+)
diff --git a/d
ned-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/renesas/phy-rcar-gen2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/renesas/phy-rcar-gen2.c
b/drivers/phy/renesas/phy-rcar-gen2.c
index 8dc5710d9c98..29
soon enough
and cause initialization to fail.
Reviewed-by: Rob Herring
Signed-off-by: Thierry Reding
Acked-by: Jon Hunter
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 12
1 file changed, 12 insertions(+)
diff --git
a
From: Thierry Reding
The Tegra124 SoC has four inputs that consume power in order to supply
the PLLs that drive the various USB, PCI and SATA pads.
Signed-off-by: Thierry Reding
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/tegra/xusb
Hi,
On 11/06/19 10:34 PM, Greg Kroah-Hartman wrote:
> On Tue, Jun 11, 2019 at 07:31:22PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Greg,
>>
>> Please find the pull request for 5.2 -rc cycle.
>>
>> The major fix being moving supplies powering PLLs used by USB, S
to be enabled by xusb-tegra124
*) Move Tegra210 PLL power supplies to be enabled by xusb-tegra210
*) Minor fixes: fix memory leaks at error path, fix sparse warnings
and addresses coverity.
Signed-off-by: Kishon Vijay Abraham I
Hi Rob,
On 10/06/19 11:13 PM, Rob Herring wrote:
> On Tue, Jun 4, 2019 at 7:19 AM Kishon Vijay Abraham I wrote:
>>
>> Export of_platform_device_create_pdata() to be used by drivers to
>> create child devices with the given platform data. This can be used
>> by platf
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SRIOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
PCI core does not enable legacy interrupt if it finds MSI or MSIX interrupt.
Explicitly enable legacy interrupt here in order to perform legacy
interrupt tests.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
the irq type of the PCI device. Fix it here by
adding 'irqtype' for each PCI device to shows the irq type of that
particular PCI device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions
Use atomic_notifier_call_chain to notify EPC events like linkup to EPF
instead of using linkup ops in EPF driver. This is in preparation for
adding proper locking mechanism to EPF ops. This will also enable to
add more events (in addition to linkup) in the future.
Signed-off-by: Kishon Vijay
Add MAINTAINER entry for PCIe on TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a6954776a37e..8a421949f335 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -121
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-ep.c | 35 +
drivers/pci/controller/pcie
Now that support for SRIOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 104 ---
drivers/pci/controller/pcie-cadence.h| 5
Add J721E in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in J721E.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc
-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pcie-cadence-ep.c
b/drivers/pci/controller/pcie-cadence-ep.c
index 3dc1a896c1e6..25638af7c668 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
.
Assign function number of each PF in EPC core and remove function
number allocation in endpoint configfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 27 +--
drivers/pci/endpoint/pci-epc-core.c | 12 +++-
include/linux/pci
Add device tree binding documentation for PCIe controller in J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci.txt | 63 +++
include/dt-bindings/pci/pci.h | 12
2 files changed, 75 insertions(+)
create mode
registered and configures
the VMAP block.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile| 1 +
drivers/pci/controller/pci-j721e.c | 431 +
3 files changed, 441 insertions(+)
create mode 100644
PCI_VENDOR_ID in root port configuration space is read-only register
and writing to it will have no effect. Use local management register to
configure Vendor ID and Subsystem Vendor ID.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-host.c | 9 +++--
1 file
Add support to add virtual function in endpoint core. Every virtual
function should be associated with a physical function. Provide APIs
to associate a virtual function with a physical function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 2 +-
drivers/pci
ops and ->is_link_up() ops to Cadence core PCIe driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/of/platform.c | 9 -
include/linux/of_platform.h | 3 +++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 0
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
Use cdns_pcie_start_link() to start link training and
cdns_pcie_wait_for_link() in order to wait to establish the link.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 11 ++-
drivers/pci/controller/pcie-cadence-host.c | 11 +++
2 files
wrapper and not in Cadence PCIe core.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 1 +
drivers/pci/controller/pcie-cadence-host.c | 1 +
drivers/pci/controller/pcie-cadence.c | 41 ++
drivers/pci/controller/pcie-cadence.h
SoC require the absolute address to be programmed in the and not
just the offset. Make "mem" an optional memory resource and use it
only for platforms that populate it.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 6 ++
drivers/pci/controlle
Protect concurrent access to pci_epf_ops with mutex.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 11 ++-
include/linux/pci-epf.h | 3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/endpoint/pci-epf-core.c
Use J721E specific compatible in pcie-cadence-* drivers. Since PCIe in
J721E SoC has a restriction that allows only 32-bit register access,
use the 32-bit accessors for read and write.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 12 +-
drivers/pci
The pci_epc_ops is not intended to be invoked from interrupt context.
Hence replace spin_lock_irqsave and spin_unlock_irqrestore with
mutex_lock and mutex_unlock respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 82
Update DT bindings for Cadence PCIe host controller with TI specific
compatible.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie
Certain platforms like TI's J721E allows only 32-bit register accesses.
Add read and write accessor to perform only 32-bit accesses in order to
support platfroms like TI's J721E.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cade
Update DT bindings for Cadence PCIe Endpoint controller with TI specific
compatible.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie
In platforms like TI's J721E EVM, the PERST# line is connected to a
GPIO line and PERST# should be driven high to indicate the clocks are
stable (As per Figure 2-10: Power Up of the PCIe CEM spec 3.0).
Add support to make GPIO drive PERST# line.
Signed-off-by: Kishon Vijay Abra
s and configuration space register access.
This is in preparation for adding PCIe support in TI's J721E SoC which
uses Cadence PCIe core.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/pcie-cadence-ep.c | 15 +++
drivers/pci/controller/pcie-cadence-host.c | 20 +++-
d
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/kernel.h | 1 +
1 file changed, 1 insertion(+)
diff --
Add binding to reset PERST# connected to a GPIO.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
b/Documentation/devicetree
Add DT binding to map a Requester ID to an IOMMU and associated IOMMU
specifier.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie
sepearate series if that is preferred.
Initial support for J721E SoC is sent here [1].
[1] -> https://lkml.org/lkml/2019/5/22/593
Kishon Vijay Abraham I (30):
dt-bindings: PCI: cadence: Add DT binding to use PCIe with IOMMU
dt-bindings: PCI: cadence: Add binding to reset PERST#
dt-
Hi,
On 20/05/19 1:34 PM, Caesar Wang wrote:
> Hi Doug,
>
> For now, nobody of rockchip is responsible for this driver.
> Cc: Nickey, Zain, Hjc
>
>
> On 5/8/19 7:48 AM, Douglas Anderson wrote:
>> While testing a newer kernel on rk3288-based Chromebooks I found that
>> the power draw in suspend
t BAR. Moreover, pci_epf_test_alloc_space()
> will call pci_epf_alloc_space() on bind for odd loop index when BAR is 64bit
> but leaks on subsequent unbind by not calling pci_epf_free_space().
>
> Signed-off-by: Alan Mikhak
> Reviewed-by: Paul Walmsley
Acked-by: Kishon Vijay Abraham I
> ---
>
Hi Alan,
On 31/05/19 11:46 PM, Alan Mikhak wrote:
> On Thu, May 30, 2019 at 10:08 PM Kishon Vijay Abraham I wrote:
>> Hi Alan,
>>>
>>> Hi Kishon,
>>>
>>> I have some improvements in mind for a v2 patch in response to
>>> feedback from
Hi,
On 31/05/19 1:19 PM, Arnd Bergmann wrote:
> On Fri, May 31, 2019 at 8:32 AM Vinod Koul wrote:
>> On 31-05-19, 10:50, Kishon Vijay Abraham I wrote:
>>> On 31/05/19 10:37 AM, Vinod Koul wrote:
>>>> On 30-05-19, 11:16, Kishon Vijay Abraham I wrote:
>>>>
Hi Vinod,
On 31/05/19 12:02 PM, Vinod Koul wrote:
> On 31-05-19, 10:50, Kishon Vijay Abraham I wrote:
>> Hi Vinod,
>>
>> On 31/05/19 10:37 AM, Vinod Koul wrote:
>>> Hi Kishon,
>>>
>>> On 30-05-19, 11:16, Kishon Vijay Abraham I wrote:
>>>
On 31/05/19 7:52 PM, Neil Armstrong wrote:
> On 31/05/2019 12:35, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On 31/05/19 4:01 PM, Neil Armstrong wrote:
>>> Fix the following BUG by disabling locking for the cr_regmap config.
>>
>> What caused the BU
Hi,
On 31/05/19 4:01 PM, Neil Armstrong wrote:
> Fix the following BUG by disabling locking for the cr_regmap config.
What caused the BUG in the first place? The commit log needs more details or
else this looks like a workaround to mask a BUG.
Thanks
Kishon
>
> BUG: sleeping function called fr
Hi Vinod,
On 31/05/19 10:37 AM, Vinod Koul wrote:
> Hi Kishon,
>
> On 30-05-19, 11:16, Kishon Vijay Abraham I wrote:
>> +Vinod Koul
>>
>> Hi,
>>
>> On 30/05/19 4:07 AM, Alan Mikhak wrote:
>>> On Mon, May 27, 2019 at 2:09 AM Gustavo Pimentel
>&g
Hi Alan,
On 30/05/19 11:26 PM, Alan Mikhak wrote:
> On Wed, May 29, 2019 at 10:48 PM Kishon Vijay Abraham I wrote:
>>
>> +Vinod Koul
>>
>> Hi,
>>
>>>>> On Fri, May 24, 2019 at 1:59 AM Gustavo Pimentel
>>>>> wrote:
>>&g
out 'pci_epc_set_bar()'
> preceding the moved code is the original comment and was also moved
> along with the code.
>
> Regards,
> Alan Mikhak
>
> On Fri, May 24, 2019 at 1:51 AM Kishon Vijay Abraham I wrote:
>>
>> Hi,
>>
>> On 24/05/19 5:25 AM,
+Vinod Koul
Hi,
On 30/05/19 4:07 AM, Alan Mikhak wrote:
> On Mon, May 27, 2019 at 2:09 AM Gustavo Pimentel
> wrote:
>>
>> On Fri, May 24, 2019 at 20:42:43, Alan Mikhak
>> wrote:
>>
>> Hi Alan,
>>
>>> On Fri, May 24, 2019 at 1:59 AM Gustavo Pimentel
>>> wrote:
Hi Alan,
This
Add PCIe Endpoint DT node.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 26
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 09f18b1e70f2
AM654 base board does not have any PCIe slots. Disable all the
SERDES and PCIe instances.
Signed-off-by: Kishon Vijay Abraham I
---
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 24 +++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base
Add DT node for SERDES0 and SERDES1.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 41
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index
Add mux-controller DT node as a child node of scm_conf. This is
required for muxing SERDES between USB, PCIe and ICSS2 SGMII.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
GIC_ITS used in AM654 platform has the same configuration as that of
GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its"
property to get PCI MSI working.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 +
1 file changed, 1 insertio
Add PCIe Root Complex DT node.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 53
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch
l the driver patches and binding documentation patches for PCIe and
SERDES are already merged.
Kishon Vijay Abraham I (6):
arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to
gic_its
arm64: dts: k3-am6: Add mux-controller DT node required for muxing
SERDES
arm64: d
ci_epf_free_space(), if called first, and BAR
>> would not get cleared.
>>
>> Signed-off-by: Alan Mikhak
Acked-by: Kishon Vijay Abraham I
>> ---
>> drivers/pci/endpoint/functions/pci-epf-test.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>
Hi,
On 24/05/19 5:25 AM, Alan Mikhak wrote:
> +Bjorn Helgaas, +Gustavo Pimentel, +Wen Yang, +Kangjie Lu
>
> On Thu, May 23, 2019 at 2:55 PM Alan Mikhak wrote:
>>
>> Always skip odd bar when skipping 64bit BARs in pci_epf_test_set_bar()
>> and pci_epf_test_alloc_space().
>>
>> Otherwise, pci_epf_
Hi,
On 24/05/19 3:25 AM, Alan Mikhak wrote:
> Always skip odd bar when skipping 64bit BARs in pci_epf_test_set_bar()
> and pci_epf_test_alloc_space().
>
> Otherwise, pci_epf_test_set_bar() will call pci_epc_set_bar() on odd loop
> index when skipping reserved 64bit BAR. Moreover, pci_epf_test_all
ntroller drivers or results may be unexpected.
>>
>> In pci_epf_test_alloc_space(), check if BAR being used for test register
>> space is a fixed size BAR. If so, allocate the required fixed size.
>>
>> Signed-off-by: Alan Mikhak
Acked-by: Kishon Vijay Abraham I
>
res checking for null endpoint function pointer.
>>
>> Signed-off-by: Alan Mikhak
Acked-by: Kishon Vijay Abraham I
>> ---
>> drivers/pci/endpoint/pci-epc-core.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drive
Hi Alan,
On 21/05/19 1:40 PM, Alan Cooper wrote:
I'm seeing an issue on a system where I have a generic PHY that is
used by a USB XHCI driver. The XHCI driver does the phy_init() in
probe and the phy_exit() in remove. The problem happens when I use
sysfs to "unload" the PHY driver before doing a
Add devicetree binding documentation for PCIe in EP mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/pci-keystone.txt | 44 +++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt
Hi Lorenzo,
On 26/04/19 3:10 PM, Lorenzo Pieralisi wrote:
> On Mon, Mar 25, 2019 at 03:09:43PM +0530, Kishon Vijay Abraham I wrote:
>> Add PCIe EP support for AM654x Platforms in pci-keystone.c
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> drivers/pci/co
iri (1):
phy: ocelot-serdes: Add support for SERDES6G muxing
Kishon Vijay Abraham I (4):
phy: core: Add *release* phy_ops invoked when the consumer relinquishes
PHY
phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset
callback
dt-bindings: phy:
On 19/04/19 10:28 AM, Andy Gross wrote:
> On Thu, Apr 18, 2019 at 09:35:44AM +0200, Marc Gonzalez wrote:
>>
>> It is not clear to me what I could/should have done differently to avoid
>> the conflict?
>
> I dropped the patch for now. We can deal with this later as it is trivial.
> The best way
CI_KEYSTONE_HOST or PCI_KEYSTONE_EP. I'm not sure what that
> would mean, but we would still try to build pci-keystone.o
>
> I'm hoping we can amend that commit before the merge window.
Sometime back Niklas had fixed this for DRA7xx in
commit b052835c63857e13d9ada3ebc57a8f9e1d
Hi Lorenzo,
On 16/04/19 7:45 PM, Lorenzo Pieralisi wrote:
> On Sat, Apr 13, 2019 at 10:26:33AM -0500, Bjorn Helgaas wrote:
>> On Mon, Mar 25, 2019 at 03:09:35PM +0530, Kishon Vijay Abraham I wrote:
>>> Add PCIe RC support for AM654x Platforms in pci-keystone.c
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