driver to get USB gadget working on H3/R40/V3/V3s
*) Fix cable state handling in phy-twl4030-usb driver to get rid of
regulator_put() warning
*) Fix linker errors and compilation warnings got with randconfig
*) Fix sparse warnings and .cocci warnings
Signed-off-by: Kishon Vijay Abraham I
Hi Greg,
On 16/04/19 4:00 PM, Greg Kroah-Hartman wrote:
> On Wed, Apr 03, 2019 at 10:13:53AM +0530, Kishon Vijay Abraham I wrote:
>> Hi Greg,
>>
>> Please find the pull request for 5.1 -rc cycle below.
>>
>> It fixes PHY programming sequence in phy-ti-pipe3 driv
Hi Bjorn,
On 13/04/19 8:00 PM, Bjorn Helgaas wrote:
> On Mon, Mar 25, 2019 at 02:04:41PM +0530, Kishon Vijay Abraham I wrote:
>> No functional change. Move host specific platform_get_resource to
>> ks_add_pcie_port and the common platform_get_resource (applicable
>> to b
Hi Bjorn,
On 13/04/19 7:33 PM, Bjorn Helgaas wrote:
> Hi Kishon,
>
> On Mon, Mar 25, 2019 at 03:09:23PM +0530, Kishon Vijay Abraham I wrote:
>> pci-keystone driver uses irq_of_parse_and_map to get irq number of
>> error_irq. Use platform_get_irq instead and
Hi Lorenzo,
On 12/04/19 4:41 PM, Lorenzo Pieralisi wrote:
> On Fri, Apr 12, 2019 at 02:20:06PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Lorenzo,
>>
>> On 11/04/19 8:33 PM, Lorenzo Pieralisi wrote:
>>> On Mon, Mar 25, 2019 at 03:09:33PM +0530, Kishon Vijay Abraham
Hi Russell,
On 12/04/19 3:01 PM, Russell King - ARM Linux admin wrote:
> On Fri, Apr 12, 2019 at 02:20:06PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Lorenzo,
>>
>> On 11/04/19 8:33 PM, Lorenzo Pieralisi wrote:
>>> On Mon, Mar 25, 2019 at 03:09:33PM +0530
Hi Lorenzo,
On 11/04/19 9:02 PM, Lorenzo Pieralisi wrote:
> On Mon, Mar 25, 2019 at 03:09:39PM +0530, Kishon Vijay Abraham I wrote:
>> Modify pci_epf_alloc_space API to take alignment size as argument in
>> order to argument in order to allocate aligned buffers to be mapped to
>
Hi Lorenzo,
On 11/04/19 8:33 PM, Lorenzo Pieralisi wrote:
> On Mon, Mar 25, 2019 at 03:09:33PM +0530, Kishon Vijay Abraham I wrote:
>> hook_fault_code is an ARM32 specific API for hooking into data abort.
>> Since pci-keystone.c will be used for AM65X platforms which is an
&g
PHY drivers may try to access PHY registers in the ->reset() callback.
Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback
so that the PHY drivers don't have to enable clocks by themselves before
accessing PHY registers.
Signed-off-by: Kishon Vijay Abraham I
---
drive
*release* phy ops
*) Populate release phy_ops in phy-am654-serdes to cleanup
initializations done in of_xlate
Kishon Vijay Abraham I (4):
phy: core: Add *release* phy_ops invoked when the consumer
relinquishes PHY
phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking
Add a new phy_ops *release* invoked when the consumer relinquishes the
PHY using phy_put/devm_phy_put. The initializations done by the PHY
driver in of_xlate call back can be can be cleaned up here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-core.c | 5 +
include/linux/phy
umentation in order to represent all these different
configurations in device tree.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/ti,phy-am654-serdes.txt | 82 +++
include/dt-bindings/phy/phy-am654-serdes.h| 13 +++
2 files changed, 95 insertions(+)
create m
uot; warnings]
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/Kconfig| 12 +
drivers/phy/ti/Makefile | 1 +
drivers/phy/ti/phy-am654-serdes.c | 624 ++
3 files changed, 637 insertions(+)
create mode 100644 drive
From: Roger Quadros
Add support to select all 16 CLKSEL combinations that are shown in
"SerDes Reference Clock Distribution" in AM65 TRM.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-am654-serdes.c | 132 +++-
Hi Andrew,
On 25/03/19 7:35 PM, Andrew F. Davis wrote:
> On 3/25/19 3:08 AM, Kishon Vijay Abraham I wrote:
>> Add a new SERDES driver for TI's AM654x SoC which configures
>> the SERDES only for PCIe. Support fo USB3 will be added later.
>>
>> SERDES in am654x has thr
ng
process")
Cc: Gustavo Pimentel
Reported-by: Adrian Hunter
Signed-off-by: Kishon Vijay Abraham I
---
tools/pci/Makefile | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tools/pci/Makefile b/tools/pci/Makefile
index 46e4c2f318c9..9b7534457060 100644
--- a/tools/pci/
Hi Lorenzo,
This series includes a couple of patches, one which fixes
inadvertent removal of pcitest.sh from kernel repo when
doing a "clean" and other lets the user use 'h' option to
display the list of options supported by pcitest.
Thanks
Kishon
Kishon Vijay Abraham I (2):
tools
'h' is a valid option character for pcitest utility used to print
the pcitest usage. Add 'h' in optstring of getopt() in order to get
rid of "pcitest: invalid option -- 'h'" warning. While at that remove
unncessary case '?'.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: S
Hi Lorenzo,
On 03/04/19 10:49 PM, Lorenzo Pieralisi wrote:
> On Thu, Mar 21, 2019 at 03:29:27PM +0530, Kishon Vijay Abraham I wrote:
>> Platforms which populate msi_host_init, has it's own MSI controller
>> logic. Writing to MSI control registers on platforms which doesn't use
>
Hi,
On 26/03/19 8:43 PM, Vidya Sagar wrote:
> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
> For each PCIe lane of a controller, there is a P2U unit instantiated at
> hardware level. This driver
got with randconfig
*) Fix sparse warnings and .cocci warnings
Signed-off-by: Kishon Vijay Abraham I
Arnd Bergmann (3):
phy: allwinner: allow compile testing
phy: ti: usb2: fix OMAP_CONTROL_PHY dependency
phy: mapp
Hi Rob,
On 28/03/19 11:37 PM, Rob Herring wrote:
> On Mon, Mar 25, 2019 at 01:38:13PM +0530, Kishon Vijay Abraham I wrote:
>> AM654x has two SERDES instances. Each instance has three input clocks
>> (left input, externel reference clock and right input) and two output
>>
Hi,
On 22/03/19 9:42 PM, Marc Gonzalez wrote:
> Copy init sequence from downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372
Can't we instead have reference to HW manual or datasheet?
>
> Signed-off-by: Marc
On 22/03/19 10:12 PM, Florian Fainelli wrote:
> On 3/19/19 11:38 AM, Scott Branden wrote:
>> Thanks Srinath and Rob - patch series looks good now.
>>
>> patch series,
>>
>> Acked-by: Scott Branden
>>
>
> Kishon, can you let me know when you apply patches 1 and 2 so I can
> queue up patch 3
ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
arch/arm/boot/dts/dra7.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch
Certain platforms like TI's AM654 doesn't have separate address space for
dbi2 instead they are accessed using the same address space as dbi
with some configuration bit set. In order to support such platforms,
add callbacks for accessing dbi2 address space.
Signed-off-by: Kishon Vijay Abraham I
Add devicetree binding documentation for PCIe in RC mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation
more flexibility using
RESBAR, this can be revisited.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-ep.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/dwc/pcie
st_reg_bar having invalid value when used outside probe. Fix it here.
Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support
for PCI_ENDPOINT_TEST regs to be mapped to any BAR")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file
Add PCIe EP support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 23 +-
drivers/pci/controller/dwc/pci-keystone.c | 242 +++---
2 files changed, 236 insertions(+), 29 deletions(-)
diff --git
start of the window unlike before where
writes were always to the beginning of the ATU window.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-desi
ince "PCIe Subsystem Address Translation"
section in TRM indicates minimum ATU window size is 64K.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/pci_endpoint_t
of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled.
Make of_pci_get_max_link_speed() to be also used by PCI Endpoint
controllers with just CONFIG_PCI_ENDPOINT enabled.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/pci/Makefile | 2 +-
drivers/pci
iatu_unroll_enabled flag is set only for Designware in host mode.
However iATU unroll can be applicable for endpoint mode too. Set
iatu_unroll_enabled flag in dw_pcie_setup which is common for
both host mode and endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc
"PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/
Add const qualifier to struct dw_pcie_ep_ops member of
struct dw_pcie_ep.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-layerscape-ep.c| 2 +-
drivers/pci/controller/dwc/pcie-artpec6.c | 2
"max-link-speed" is absent.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
index e4a816
invoking pci_epf_alloc_space.
This is mainly required for Synopsys Designware PCIe core which masks
the lower bits based on the BAR size (See "I/O and MEM Match Modes"
section in DesignWare Cores PCI Express Controller Databook version
4.90a).
Signed-off-by: Kishon Vijay Abraham I
---
d
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-
ll still be used.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware.c | 14 --
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pc
hook_fault_code is an ARM32 specific API for hooking into data abort.
Since pci-keystone.c will be used for AM65X platforms which is an
ARM64 platform, allow hook_fault_code to be compiled only for ARM32.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4
Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link
directly from host_init. start_link/stop_link ops is required for
adding EP mode support.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 44 +++
1 file changed, 22
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++
1 file
No functional change. Instead of having two functions
ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host,
have a single function to perform all the host initialization.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 63
Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always
relying on the default values. This is required when EP mode has to
be explicitly written to BOOTCFG_DEVCFG register.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 37
has never worked out of the box in mainline kernel, dt backward
compatibility is ignored.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci
.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
index a6a482bd648f..e4a816f53b8e 100644
--- a/drivers/pci/controller
Add PCIe RC support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 2 +-
drivers/pci/controller/dwc/pci-keystone.c | 161 --
2 files changed, 148 insertions(+), 15 deletions(-)
diff --git
No functional change. Move host specific platform_get_resource to
ks_add_pcie_port and the common platform_get_resource (applicable
to both host and endpoint) to probe. This is in preparation for
adding endpoint support to pci-keystone driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers
e Keystone PCI dt-bindngs. This new
binding will also be used by PCI in AM654 platform.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/
pci-keystone driver uses irq_of_parse_and_map to get irq number of
error_irq. Use platform_get_irq instead and move platform_get_irq()
and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
since error_irq is common to both RC mode and EP mode.
Signed-off-by: Kishon Vijay
*) Update "Reviewed-by: Rob Herring " tags.
[1] -> https://lore.kernel.org/patchwork/cover/989487/
[2] -> https://lkml.org/lkml/2019/3/21/193
[3] -> https://lkml.org/lkml/2019/3/19/235
Kishon Vijay Abraham I (26):
PCI: keystone: Add start_link/stop_link dw_pcie_ops
PCI
Hi,
On 25/03/19 2:04 PM, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
> uses Synopsys core revision 4.90a and uses the same TI wrapper as used
> in keystone2 with certain modification. Hence AM654 will use the same
> pci wrappe
Add PCIe RC support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 2 +-
drivers/pci/controller/dwc/pci-keystone.c | 161 --
2 files changed, 148 insertions(+), 15 deletions(-)
diff --git
ince "PCIe Subsystem Address Translation"
section in TRM indicates minimum ATU window size is 64K.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/pci_endpoint_t
iatu_unroll_enabled flag is set only for Designware in host mode.
However iATU unroll can be applicable for endpoint mode too. Set
iatu_unroll_enabled flag in dw_pcie_setup which is common for
both host mode and endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc
start of the window unlike before where
writes were always to the beginning of the ATU window.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-desi
Add PCIe EP support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 23 +-
drivers/pci/controller/dwc/pci-keystone.c | 242 +++---
2 files changed, 236 insertions(+), 29 deletions(-)
diff --git
of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled.
Make of_pci_get_max_link_speed() to be also used by PCI Endpoint
controllers with just CONFIG_PCI_ENDPOINT enabled.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/pci/Makefile | 2 +-
drivers/pci
Certain platforms like TI's AM654 doesn't have separate address space for
dbi2 instead they are accessed using the same address space as dbi
with some configuration bit set. In order to support such platforms,
add callbacks for accessing dbi2 address space.
Signed-off-by: Kishon Vijay Abraham I
more flexibility using
RESBAR, this can be revisited.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-ep.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/dwc/pcie
st_reg_bar having invalid value when used outside probe. Fix it here.
Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support
for PCI_ENDPOINT_TEST regs to be mapped to any BAR")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file
"PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/
Add const qualifier to struct dw_pcie_ep_ops member of
struct dw_pcie_ep.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-plat.c | 2
invoking pci_epf_alloc_space.
This is mainly required for Synopsys Designware PCIe core which masks
the lower bits based on the BAR size (See "I/O and MEM Match Modes"
section in DesignWare Cores PCI Express Controller Databook version
4.90a).
Signed-off-by: Kishon Vijay Abraham I
---
d
Add devicetree binding documentation for PCIe in RC mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/pci
"max-link-speed" is absent.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
index e4a816
ll still be used.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pcie-designware.c | 14 --
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pc
.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
index a6a482bd648f..e4a816f53b8e 100644
--- a/drivers/pci/controller
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-
hook_fault_code is an ARM32 specific API for hooking into data abort.
Since pci-keystone.c will be used for AM65X platforms which is an
ARM64 platform, allow hook_fault_code to be compiled only for ARM32.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4
Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always
relying on the default values. This is required when EP mode has to
be explicitly written to BOOTCFG_DEVCFG register.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 37
Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link
directly from host_init. start_link/stop_link ops is required for
adding EP mode support.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 44 +++
1 file changed, 22
No functional change. Move host specific platform_get_resource to
ks_add_pcie_port and the common platform_get_resource (applicable
to both host and endpoint) to probe. This is in preparation for
adding endpoint support to pci-keystone driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers
has never worked out of the box in mainline kernel, dt backward
compatibility is ignored.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci
to be used by Endpoint controller
driver
*) Add support to set max-link-speed from DT in pci-keystone driver
*) Update "Reviewed-by: Rob Herring " tags.
[1] -> https://lore.kernel.org/patchwork/cover/989487/
[2] -> https://lkml.org/lkml/2019/3/21/193
[3] -> https://lkml.org/lkml/2019/3/1
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++
1 file changed, 2 insertions(+)
No functional change. Instead of having two functions
ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host,
have a single function to perform all the host initialization.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 63
e Keystone PCI dt-bindngs. This new
binding will also be used by PCI in AM654 platform.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindin
pci-keystone driver uses irq_of_parse_and_map to get irq number of
error_irq. Use platform_get_irq instead and move platform_get_irq()
and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
since error_irq is common to both RC mode and EP mode.
Signed-off-by: Kishon Vijay
From: Roger Quadros
Add support to select all 16 CLKSEL combinations that are shown in
"SerDes Reference Clock Distribution" in AM65 TRM.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-am654-serdes.c | 134 +++-
uot; warnings]
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/Kconfig| 12 +
drivers/phy/ti/Makefile | 1 +
drivers/phy/ti/phy-am654-serdes.c | 539 ++
3 files changed, 552 insertions(+)
create mode 100644 drive
umentation in order to represent all these different
configurations in device tree.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/ti,phy-am654-serdes.txt | 81 +++
include/dt-bindings/phy/phy-am654-serdes.h| 13 +++
2 files changed, 94 insertions(+)
create m
PHY drivers may try to access PHY registers in the ->reset() callback.
Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback
so that the PHY drivers don't have to enable clocks by themselves before
accessing PHY registers.
Signed-off-by: Kishon Vijay Abraham I
---
drive
Add a new phy_ops *release* invoked when the consumer relinquishes the
PHY using phy_put/devm_phy_put. The initializations done by the PHY
driver in of_xlate call back can be can be cleaned up here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-core.c | 5 +
include/linux/phy
by rOGER
*) Add dt-binding Documentation in a new file ti,phy-am654-serdes.txt
*) Add Roger's patch to support all CLKSEL values.
Changes from v1:
*) Add *release* phy ops
*) Populate release phy_ops in phy-am654-serdes to cleanup
initializations done in of_xlate
Kishon Vijay Abraham I (4
-0357-4294-7e92d95d8...@arm.com
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 24 ---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
(), msi_set_irq(), msi_clear_irq()
callback functions.
Add support to use different msi_irq_chip with default as
dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of
msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone
specific dw_pcie_host_ops.
Signed-off-by: Kishon Vijay
instead of Designware's MSI controller
logic.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-host.c | 24 ++-
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci
ks_pcie_get_irq_controller_info() is used to configure both MSI and
legacy interrupt. This will prevent MSI or legacy interrupt specific
intializations. Add separate functions to configure MSI and legacy
interrupts.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci
Now that Keystone started using its own msi_irq_chip, remove
Keystone specific callback functions defined in dw_pcie_host_ops.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie-designware-host.c | 50 ++-
drivers/pci/controller/dwc/pcie-designware.h | 5
callback functions
added in dw_pcie_host_ops.
Move the default msi_irq_chip assignment to dw_pcie_host_init since
platforms that doesn't use the default msi_irq_chip will assign
msi_irq_chip in msi_host_init() callback.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci
No functional change. Change both MSI interrupt and legacy interrupt
related macros to take an additional argument in order to return the
correct register offset.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 26 +++
1 file changed, 13
egacy interrupt handling" from the patch series. It should be
handled differently.
*) Added Gustavo's ACKed by and fixed a commit message.
[1] -> https://patchwork.kernel.org/patch/10681587/
Kishon Vijay Abraham I (8):
PCI: keystone: Cleanup interrupt related macros
PCI: keystone:
d pci-keystone.c"), which merged the keystone PCIe
driver to use a single file, two functions for handling the
interrupt handler is not required.
Handle MSI interrupt in a single interrupt handler here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keyst
;>return -EINVAL;
>>>>}
>>>>
>>>> - run_test(test);
>>>> - return 0;
>>>> + return run_test(test);
>>>> }
>>>> --
>>>> 2.7.4
>>>>
>>>
>>> Hi Kishon,
>>>
>>> are you OK with this patch ? Please let me know.
>>
>> Please let me know, I need your ACK on this to queue it.
>
> Hi Kishon,
>
> I will merge this patch unless you have something against it,
> please let me know.
Sorry for missing this earlier.
Acked-by: Kishon Vijay Abraham I
>
> Thanks,
> Lorenzo
>
Hi Marc,
On 18/03/19 4:46 PM, Marc Zyngier wrote:
> On Mon, 18 Mar 2019 11:03:07 +0530
> Kishon Vijay Abraham I wrote:
>
>> Hi Marc,
>>
>> On 07/03/19 5:32 PM, Marc Zyngier wrote:
>>> On Thu, 07 Mar 2019 09:12:30 +,
>>> Kishon Vijay Abraham I w
Hi Faiz,
On 19/03/19 12:05 PM, Faiz Abbas wrote:
> commit 5b0d62108b46 ("mmc: sdhci-omap: Add platform specific reset
> callback") skips data resets during tuning operation. Because of this,
> a data error or data finish interrupt might still arrive after a command
> error has been handled and
Hi Faiz,
On 19/03/19 12:05 PM, Faiz Abbas wrote:
> Make sdhci_send_command() public so that it can be called from platform
> drivers.
This should be sdhci_finish_command here and also in subject
How about using "mmc: sdhci: Export sdhci_finish_command()"?
Thanks
Kishon
>
> Signed-off-by: Faiz
Hi Thierry,
On 21/02/19 9:16 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> This series adds support for Tegra186 to the XUSB pad controller driver.
> Patch 1 extends the device tree bindings with support for Tegra186 while
> patches 2-4 are preparatory work for the final patch 5 that
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