Hi Tom,
On 04/01/2021 07:43 AM, Tom Rix wrote:
small alloc's should use kzalloc.
On 3/23/21 10:29 PM, Lizhi Hou wrote:
fpga-mgr and region implementation for xclbin download which will be
called from main platform driver
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off
Hi Tom,
On 04/01/2021 07:07 AM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
platform driver that handles IOCTLs, such as hot reset and xclbin download.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xmgmt-main.h | 34
Hi Tom,
On 04/06/2021 02:00 PM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
MAINTAINERS| 11
Hi Tom,
On 04/06/2021 06:50 AM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
ICAP stands for Hardware Internal Configuration Access Port. ICAP is
discovered by walking firmware metadata. A platform device node will be
by walking the firmware
Sure.
created for it. FPGA bitstream
to something else.
Will change local regmap to 'compat'.
On 3/23/21 10:29 PM, Lizhi Hou wrote:
Add VSEC driver. VSEC is a hardware function discovered by walking
PCI Express configure space. A platform device node will be created
for it. VSEC provides board logic UUID and few offset of other
Hi Tom,
On 03/29/2021 10:12 AM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code enumerates and extracts sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS.
ok
/23/21 10:29 PM, Lizhi Hou wrote:
XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for the driver to parse
device tree blob.
to parse the device
Will fix
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off
Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
MAINTAINERS| 11 +++
drivers/Makefile | 1 +
drivers/fpga/Kconfig | 2
Add DDR calibration driver. DDR calibration is a hardware function
discovered by walking firmware metadata. A platform device node will
be created for it. Hardware provides DDR calibration status through
this function.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xleaf/clkfreq.h | 21 ++
drivers/fpga/xrt/lib/xleaf/clkfreq.c | 240 +++
2 files changed, 261 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h
create mode 100644 drivers
-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xleaf/axigate.h | 23 ++
drivers/fpga/xrt/lib/xleaf/axigate.c | 342 +++
2 files changed, 365 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h
create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c
Add devctl driver. devctl is a type of hardware function which only has
few registers to read or write. They are discovered by walking firmware
metadata. A platform device node will be created for them.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers
Add clock driver. Clock is a hardware function discovered by walking
xclbin metadata. A platform device node will be created for it. Other
part of driver configures clock through clock driver.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt
Add User Clock Subsystem (UCS) driver. UCS is a hardware function
discovered by walking xclbin metadata. A platform device node will be
created for it. UCS enables/disables the dynamic region clocks.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers
ICAP stands for Hardware Internal Configuration Access Port. ICAP is
discovered by walking firmware metadata. A platform device node will be
created for it. FPGA bitstream is written to hardware through ICAP.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
Add VSEC driver. VSEC is a hardware function discovered by walking
PCI Express configure space. A platform device node will be created
for it. VSEC provides board logic UUID and few offset of other hardware
functions.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
fpga-mgr and region implementation for xclbin download which will be
called from main platform driver
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/mgmt/fmgr-drv.c| 191 +++
drivers/fpga/xrt/mgmt/fmgr.h| 19 ++
drivers
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/mgmt/root.c | 333 +++
1 file changed, 333 insertions(+)
create mode 100644 drivers/fpga/xrt/mgmt/root.c
diff --git a/drivers/fpga/xrt/mgmt/root.c b/drivers/fpga/xrt/mgmt/root.c
new file mode 100644
index
platform driver that handles IOCTLs, such as hot reset and xclbin download.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xmgmt-main.h | 34 ++
drivers/fpga/xrt/mgmt/main.c | 670 ++
drivers/fpga/xrt
Helper functions for char device node creation / removal for platform
drivers. This is part of platform driver infrastructure.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/lib/cdev.c | 232
1 file
Contains common code for all root drivers and handles root calls from
platform drivers. This is part of root driver infrastructure.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/events.h | 45 +++
drivers/fpga/xrt/include/xroot.h
Infrastructure code providing APIs for managing leaf driver instance
groups, facilitating inter-leaf driver calls and root calls.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/lib/subdev.c | 865 ++
1 file
xrt-lib kernel module infrastructure code to register and manage all
leaf driver modules.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/subdev_id.h | 38
drivers/fpga/xrt/include/xleaf.h | 264
group driver that manages life cycle of a bunch of leaf driver instances
and bridges them with root.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/group.h | 25 +++
drivers/fpga/xrt/lib/group.c | 286
XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for the driver to parse
device tree blob.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/metadata.h | 233
Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code enumerates and extracts sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga
Describe XRT driver architecture and provide basic overview of
Xilinx Alveo platform.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
Documentation/fpga/index.rst | 1 +
Documentation/fpga/xrt.rst | 844 +++
2 files changed
29189-15-liz...@xilinx.com
https://lore.kernel.org/lkml/20210218064019.29189-16-liz...@xilinx.com
https://lore.kernel.org/lkml/20210218064019.29189-17-liz...@xilinx.com
https://lore.kernel.org/lkml/20210218064019.29189-18-liz...@xilinx.com
https://lore.kernel.org/lkml/20210218064019.29189-19-liz...@xilinx.co
Hi Tom,
On 03/03/2021 07:12 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add ICAP driver. ICAP is a hardware function discovered by walking
What does ICAP stand for ?
ICAP stands for Hardware Internal Configuration Access Port. I will add
this.
firmware metadata. A platform
On 03/04/2021 05:39 AM, Tom Rix wrote:
CAUTION: This message has originated from an External Source. Please use proper
judgment and caution when opening attachments, clicking links, or responding to
this email.
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add devctl driver. devctl is a type
Hi Tom,
On 02/26/2021 09:22 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
platform driver that handles IOCTLs, such as hot reset and xclbin download.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xmgmt-main.h | 37
Hi Moritz,
On 02/21/2021 12:36 PM, Moritz Fischer wrote:
On Wed, Feb 17, 2021 at 10:40:18PM -0800, Lizhi Hou wrote:
Add partition isolation platform driver. partition isolation is
a hardware function discovered by walking firmware metadata.
A platform device node will be created
Hi Tom,
On 03/06/2021 07:54 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add partition isolation platform driver. partition isolation is
a hardware function discovered by walking firmware metadata.
A platform device node will be created for it. Partition isolation
function isolate
Hi Tom,
On 03/06/2021 07:34 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add DDR calibration driver. DDR calibration is a hardware function
discovered by walking firmware metadata. A platform device node will
be created for it. Hardware provides DDR calibration status through
Hi Tom,
On 03/06/2021 07:25 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add clock frequence counter driver. Clock frequence counter is
a hardware function discovered by walking xclbin metadata. A platform
device node will be created for it. Other part of driver can read
Hi Tom,
On 03/05/2021 07:23 AM, Tom Rix wrote:
why are clock and clkfeq separated ?
clock and clkfreq are two different IPs. clkfreq is a simple counter to
confirm the clock output is expected.
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add clock driver. Clock is a hardware function discovered
Hi Tom,
On 03/02/2021 08:09 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add UCS driver. UCS is a hardware function discovered by walking xclbin
What does UCS stand for ? add to commit log
UCS stands for User Clock Subsystem. I will add it to log.
metadata. A platform device
Hi Moritz,
On 02/21/2021 10:33 AM, Moritz Fischer wrote:
On Sun, Feb 21, 2021 at 09:12:37AM -0800, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Alveo FPGA firmware and partial reconfigure file are in xclbin format.
This code enumerates and extracts
Add
code to enumerate
Hi Tom,
On 03/01/2021 11:01 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Add VSEC driver. VSEC is a hardware function discovered by walking
PCI Express configure space. A platform device node will be created
for it. VSEC provides board logic UUID and few offset of other hardware
Hi Moritz,
On 03/02/2021 07:14 AM, Moritz Fischer wrote:
On Mon, Mar 01, 2021 at 04:25:37PM -0800, Lizhi Hou wrote:
Hi Tom，
On 02/28/2021 08:54 AM, Tom Rix wrote:
CAUTION: This message has originated from an External Source. Please use proper
judgment and caution when opening attachments
Hi Tom,
On 02/28/2021 08:36 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
fpga-mgr and region implementation for xclbin download which will be
called from main platform driver
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt
Hi Moritz,
On 02/21/2021 12:24 PM, Moritz Fischer wrote:
On Wed, Feb 17, 2021 at 10:40:13PM -0800, Lizhi Hou wrote:
Add ICAP driver. ICAP is a hardware function discovered by walking
firmware metadata. A platform device node will be created for it.
FPGA bitstream is written to hardware
Hi Tom，
On 02/28/2021 08:54 AM, Tom Rix wrote:
CAUTION: This message has originated from an External Source. Please use proper
judgment and caution when opening attachments, clicking links, or responding to
this email.
On 2/26/21 1:23 PM, Lizhi Hou wrote:
Hi Tom,
snip
I also do
Hi Moritz,
On 02/21/2021 12:43 PM, Moritz Fischer wrote:
Lizhi,
On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote:
Hello,
This is V3 of patch series which adds management physical function driver for
Xilinx
Alveo PCIe accelerator cards,
https://www.xilinx.com/products/boards
Hi Tom,
On 02/21/2021 09:12 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Alveo FPGA firmware and partial reconfigure file are in xclbin format.
This code enumerates and extracts
Will change this to
Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code
Hi Fernando,
On 02/22/2021 05:23 PM, Fernando Pacheco wrote:
On Wed, Feb 17, 2021 at 10:40:03PM -0800, Lizhi Hou wrote:
XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for driver to parse
device tree blob.
Signed-off
Hi Tom,
On 02/20/2021 09:07 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for driver to parse
for the driver to parse the
will fix.
device tree blob
On 02/18/2021 05:52 AM, Tom Rix wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
Hello,
This is V3 of patch series which adds management physical function driver for
Xilinx
Alveo PCIe accelerator cards,
https://www.xilinx.com/products/boards-and-kits/alveo.html
This driver is part of Xilinx
Add VSEC driver. VSEC is a hardware function discovered by walking
PCI Express configure space. A platform device node will be created
for it. VSEC provides board logic UUID and few offset of other hardware
functions.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
Add devctl driver. devctl is a type of hardware function which only has
few registers to read or write. They are discovered by walking firmware
metadata. A platform device node will be created for them.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers
Add UCS driver. UCS is a hardware function discovered by walking xclbin
metadata. A platform device node will be created for it.
UCS enables/disables the dynamic region clocks.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xleaf
Add DDR calibration driver. DDR calibration is a hardware function
discovered by walking firmware metadata. A platform device node will
be created for it. Hardware provides DDR calibration status through
this function.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xleaf/axigate.h | 25 ++
drivers/fpga/xrt/lib/xleaf/axigate.c | 298 +++
2 files changed, 323 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h
create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 +++
drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 +++
2 files changed, 244 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h
create mode 100644
Add ICAP driver. ICAP is a hardware function discovered by walking
firmware metadata. A platform device node will be created for it.
FPGA bitstream is written to hardware through ICAP.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include
Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
MAINTAINERS| 11 +++
drivers/Makefile | 1 +
drivers/fpga/Kconfig | 2
Add clock driver. Clock is a hardware function discovered by walking
xclbin metadata. A platform device node will be created for it. Other
part of driver configures clock through clock driver.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt
fpga-mgr and region implementation for xclbin download which will be
called from main platform driver
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/mgmt/fmgr-drv.c| 187 +++
drivers/fpga/xrt/mgmt/fmgr.h| 28 ++
drivers
Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xroot.h | 114 +++
drivers/fpga/xrt/mgmt/root.c | 342 +++
2 files changed, 456 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xroot.h
create mode 100644 drivers/fpga/xrt/mgmt/root.c
infrastructure code providing APIs for managing leaf driver instance
groups, facilitating inter-leaf driver calls and root calls, managing leaf
driver device nodes.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/events.h| 48
platform driver that handles IOCTLs, such as hot reset and xclbin download.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xmgmt-main.h | 37 ++
drivers/fpga/xrt/mgmt/main-impl.h | 37 ++
drivers/fpga/xrt/mgmt/main.c
group driver that manages life cycle of a bunch of leaf driver instances
and bridges them with root.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/group.h | 27
drivers/fpga/xrt/lib/group.c | 265
xrt-lib kernel module infrastructure code to register and manage all
leaf driver modules.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/lib/main.c | 274
drivers/fpga/xrt/lib/main.h | 17 +++
2 files
Alveo FPGA firmware and partial reconfigure file are in xclbin format. Add
code to enumerate and extract sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga
XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for driver to parse
device tree blob.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/metadata.h | 229
Describe XRT driver architecture and provide basic overview of
Xilinx Alveo platform.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
Documentation/fpga/index.rst | 1 +
Documentation/fpga/xrt.rst | 842 +++
2 files changed
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