[PATCH 1/1] iommu/vt-d: Remove unnecessary rcu_read_locks

. dmar_remove_one_dev_info() doesn't touch any of those lists, so it doesn't require a lock. In fact it is called 6 times without it anyway. Fixes: d160aca5276d ("iommu/vt-d: Unify domain->iommu attach/detachment") Signed-off-by: Lukasz Odzioba --- drivers/iommu/intel-iommu.c | 4 1 fi

RE: [2/4] crypto: af_alg - Allow arbitrarily long algorithm names" email-alg_bind.txt

Hi, I found this patch by accident and it got my attention. I think we can't make this name arbitrarily long because bind syscall checks addrlen before feeding protocol with it. Current limit on my machine is 128 bytes and I can't even reach alg_bind() function if I specify more than that. We

RE: [2/4] crypto: af_alg - Allow arbitrarily long algorithm names" email-alg_bind.txt

Hi, I found this patch by accident and it got my attention. I think we can't make this name arbitrarily long because bind syscall checks addrlen before feeding protocol with it. Current limit on my machine is 128 bytes and I can't even reach alg_bind() function if I specify more than that. We

[tip:x86/urgent] x86/cpu: Fix bootup crashes by sanitizing the argument of the 'clearcpuid=' command-line option

Commit-ID: dd853fd216d1485ed3045ff772079cc8689a9a4a Gitweb: http://git.kernel.org/tip/dd853fd216d1485ed3045ff772079cc8689a9a4a Author: Lukasz Odzioba <lukasz.odzi...@intel.com> AuthorDate: Wed, 28 Dec 2016 14:55:40 +0100 Committer: Ingo Molnar <mi...@kernel.org> CommitDate

[tip:x86/urgent] x86/cpu: Fix bootup crashes by sanitizing the argument of the 'clearcpuid=' command-line option

Commit-ID: dd853fd216d1485ed3045ff772079cc8689a9a4a Gitweb: http://git.kernel.org/tip/dd853fd216d1485ed3045ff772079cc8689a9a4a Author: Lukasz Odzioba AuthorDate: Wed, 28 Dec 2016 14:55:40 +0100 Committer: Ingo Molnar CommitDate: Thu, 5 Jan 2017 08:54:34 +0100 x86/cpu: Fix bootup

[PATCH 1/1] x86: sanitize argument of clearcpuid command-line option

: ac72e7888a61 ("x86: add generic clearcpuid=... option") Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- As an example let's change definition of one_hundred variable: 81c4eeec d one_hundred 81d69720 D boot_cpu_data (0x14 is x86_capability offset) 8*(0x

[PATCH 1/1] x86: sanitize argument of clearcpuid command-line option

: ac72e7888a61 ("x86: add generic clearcpuid=... option") Signed-off-by: Lukasz Odzioba --- As an example let's change definition of one_hundred variable: 81c4eeec d one_hundred 81d69720 D boot_cpu_data (0x14 is x86_capability offset) 8*(0x81d69734-0xff

[tip:perf/urgent] perf/x86/intel/cstate: Add C-state residency events for Knights Landing

Commit-ID: 889882bce2a5f69242c1f3acd840983f467499b9 Gitweb: http://git.kernel.org/tip/889882bce2a5f69242c1f3acd840983f467499b9 Author: Lukasz Odzioba <lukasz.odzi...@intel.com> AuthorDate: Tue, 4 Oct 2016 18:26:26 +0200 Committer: Ingo Molnar <mi...@kernel.org> CommitDate:

[tip:perf/urgent] perf/x86/intel/cstate: Add C-state residency events for Knights Landing

Commit-ID: 889882bce2a5f69242c1f3acd840983f467499b9 Gitweb: http://git.kernel.org/tip/889882bce2a5f69242c1f3acd840983f467499b9 Author: Lukasz Odzioba AuthorDate: Tue, 4 Oct 2016 18:26:26 +0200 Committer: Ingo Molnar CommitDate: Wed, 19 Oct 2016 15:52:16 +0200 perf/x86/intel/cstate

[PATCH 1/1] x86/perf/intel/cstate: add C-state residency events for Knights Landing

Although KNL does support C1,C6,PC2,PC3,PC6 states, the patch only supports C6,PC2,PC3,PC6, because there is no counter for C1. C6 residency counter MSR on KNL has a different address than other platforms which is handled as a new quirk flag. Signed-off-by: Lukasz Odzioba <lukasz.o

[PATCH 1/1] x86/perf/intel/cstate: add C-state residency events for Knights Landing

Although KNL does support C1,C6,PC2,PC3,PC6 states, the patch only supports C6,PC2,PC3,PC6, because there is no counter for C1. C6 residency counter MSR on KNL has a different address than other platforms which is handled as a new quirk flag. Signed-off-by: Lukasz Odzioba --- arch/x86/events

[PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing

n Phi gen 2) support") Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com> --- drivers/edac/sb_edac.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/edac/sb_edac.c b/

[PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing

n Phi gen 2) support") Signed-off-by: Lukasz Odzioba Signed-off-by: Hubert Chrzaniuk --- drivers/edac/sb_edac.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 6744d88..61e2c52 100644 --- a/dr

[PATCH v2 1/1] mm/swap.c: flush lru pvecs on compound page arrival

severe - after applying it kill rate of above example drops to 0%, due to reducing maximum amount of memory held on pvec from 28MB (with THP) to 56kB per CPU. Suggested-by: Michal Hocko <mho...@suse.com> Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- v2: Flush all pvecs ins

[PATCH v2 1/1] mm/swap.c: flush lru pvecs on compound page arrival

severe - after applying it kill rate of above example drops to 0%, due to reducing maximum amount of memory held on pvec from 28MB (with THP) to 56kB per CPU. Suggested-by: Michal Hocko Signed-off-by: Lukasz Odzioba --- v2: Flush all pvecs instead of just lru_add_pvec --- mm/swap.c | 11

[PATCH 1/1] mm/swap.c: flush lru_add pvecs on compound page arrival

%. Suggested-by: Michal Hocko <mho...@suse.com> Tested-by: Lukasz Odzioba <lukasz.odzi...@intel.com> Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- mm/swap.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/mm/swap.c b/mm/swap.c index 95916

[PATCH 1/1] mm/swap.c: flush lru_add pvecs on compound page arrival

%. Suggested-by: Michal Hocko Tested-by: Lukasz Odzioba Signed-off-by: Lukasz Odzioba --- mm/swap.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/mm/swap.c b/mm/swap.c index 9591614..3fe4f18 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -391,9 +391,8 @@ static void

[PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing

x.intel.com> Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- arch/x86/events/core.c | 3 ++- arch/x86/events/intel/core.c | 17 ++--- arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/perf_event.h | 41 - 4

[PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing

on PMC0 This patch introduces INTEL_EEVENT_CONSTRAINT where third parameter specifies extended config bits allowed only on given PMCs. Patch depends on "Change offcore response masks for Knights Landing" Reported-by: Andi Kleen Acked-by: Andi Kleen Signed-off-by: Lukasz Odzioba --- arch/

[tip:perf/core] perf/x86/intel: Add 'static' keyword to locally used arrays

Commit-ID: 20f362785869196fb61a76661a48321169a9046e Gitweb: http://git.kernel.org/tip/20f362785869196fb61a76661a48321169a9046e Author: Lukasz Odzioba <lukasz.odzi...@intel.com> AuthorDate: Mon, 16 May 2016 23:16:18 +0200 Committer: Ingo Molnar <mi...@kernel.org> CommitDate

[tip:perf/core] perf/x86/intel: Change offcore response masks for Knights Landing

Commit-ID: 9c489fce7a4a46c8a408e16e126bf3225401c7b5 Gitweb: http://git.kernel.org/tip/9c489fce7a4a46c8a408e16e126bf3225401c7b5 Author: Lukasz Odzioba <lukasz.odzi...@intel.com> AuthorDate: Mon, 16 May 2016 23:16:59 +0200 Committer: Ingo Molnar <mi...@kernel.org> CommitDate

[tip:perf/core] perf/x86/intel: Change offcore response masks for Knights Landing

Commit-ID: 9c489fce7a4a46c8a408e16e126bf3225401c7b5 Gitweb: http://git.kernel.org/tip/9c489fce7a4a46c8a408e16e126bf3225401c7b5 Author: Lukasz Odzioba AuthorDate: Mon, 16 May 2016 23:16:59 +0200 Committer: Ingo Molnar CommitDate: Fri, 3 Jun 2016 09:40:17 +0200 perf/x86/intel: Change

[tip:perf/core] perf/x86/intel: Add 'static' keyword to locally used arrays

Commit-ID: 20f362785869196fb61a76661a48321169a9046e Gitweb: http://git.kernel.org/tip/20f362785869196fb61a76661a48321169a9046e Author: Lukasz Odzioba AuthorDate: Mon, 16 May 2016 23:16:18 +0200 Committer: Ingo Molnar CommitDate: Fri, 3 Jun 2016 09:40:17 +0200 perf/x86/intel: Add

[PATCH 1/1] arch/x86/perf/intel: Add static keyword to some arrays

Add static keyword to intel_bdw_event_constraints, snb_events_attrs, nhm_events_attrs, intel_skl_event_constraints arrays. Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- arch/x86/events/intel/core.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH 1/1] arch/x86/perf/intel: Add static keyword to some arrays

Add static keyword to intel_bdw_event_constraints, snb_events_attrs, nhm_events_attrs, intel_skl_event_constraints arrays. Signed-off-by: Lukasz Odzioba --- arch/x86/events/intel/core.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b

[PATCH 1/1] perf/x86/intel: Change offcore response masks for Knights Landing

Due to change in register definition we need to update OCR mask. MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14 MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38 Reported-by: Andi Kleen <a...@linux.intel.com> Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com&g

[PATCH 1/1] perf/x86/intel: Change offcore response masks for Knights Landing

Due to change in register definition we need to update OCR mask. MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14 MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38 Reported-by: Andi Kleen Signed-off-by: Lukasz Odzioba --- arch/x86/events/intel/core.c | 6 ++ 1 file

[PATCH 1/1] Bumps limit of maximum core ID from 32 to 128.

-by: Lukasz Odzioba --- drivers/hwmon/coretemp.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 3e03379..6a27eb2 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -52,7 +52,7 @@ module_param_named

[PATCH 1/1] Bumps limit of maximum core ID from 32 to 128.

-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- drivers/hwmon/coretemp.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 3e03379..6a27eb2 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@

[PATCH 1/1] hwmon: coretemp: use dynamically allocated array to store per core data

coretemp.0: Adding Core XXX failed Signed-off-by: Lukasz Odzioba --- drivers/hwmon/coretemp.c | 94 +- 1 files changed, 76 insertions(+), 18 deletions(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 3e03379..1e60039 100644

hwmon: coretemp: use dynamically allocated array to store per core data

This patch is continuation of my previous work. After Guenter Roeck's and Jean Delware's comments I changed list to an array. Initial array size is 4 and it is extended when core id exeeds size of the array, which in practice can mean every time a new core is initialized. I am not sure whether

[PATCH 1/1] hwmon: coretemp: use dynamically allocated array to store per core data

coretemp.0: Adding Core XXX failed Signed-off-by: Lukasz Odzioba <lukasz.odzi...@intel.com> --- drivers/hwmon/coretemp.c | 94 +- 1 files changed, 76 insertions(+), 18 deletions(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c

hwmon: coretemp: use dynamically allocated array to store per core data

This patch is continuation of my previous work. After Guenter Roeck's and Jean Delware's comments I changed list to an array. Initial array size is 4 and it is extended when core id exeeds size of the array, which in practice can mean every time a new core is initialized. I am not sure whether

[PATCH] hwmon: coretemp: use list instead of fixed size array for temp data

Removes the limits of supported CPU cores and max core ID. Patch is based on Kirill A. Shutemov's work from 2012. Signed-off-by: Lukasz Odzioba --- drivers/hwmon/coretemp.c | 120 - 1 files changed, 75 insertions(+), 45 deletions(-) diff --git

[PATCH] hwmon: coretemp: use list instead of fixed size array for temp data

Removes the limits of supported CPU cores and max core ID. Patch is based on Kirill A. Shutemov's work from 2012. Signed-off-by: Lukasz Odzioba lukasz.odzi...@intel.com --- drivers/hwmon/coretemp.c | 120 - 1 files changed, 75 insertions(+), 45