On 21.02.2018 16:46, Guenter Roeck wrote:
On 02/20/2018 11:15 PM, Mikko Perttunen wrote:
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver
for this.
I am kind of lost. Please explain.
Are you saying that we
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver for
this.
In any case, we cannot add something like this to device tree since it's
not a hardware device.
Mikko
On 21.02.2018 08:58, Rajkumar Rampelli wrote:
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
Notes:
v4:
- fixed copyright headers ac
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
On 16.02.2018 14:33, Philippe Ombredanne wrote:
Mikko,
On Thu, Feb 15, 2018 at 3:52 PM, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
Notes:
v3:
- added hypervisor-related apertu
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
On 10.02.2018 00:54, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:36AM +0200, Mikko Perttunen wrote:
...
index ..dcc6eea52684
--- /dev/null
+++ b/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,664 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018
On 07.02.2018 12:21, Marc Zyngier wrote:
Hi Mikko,
On 06/02/18 07:22, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UA
On 02/10/2018 12:49 AM, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:34AM +0200, Mikko Perttunen wrote:
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- add
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file changed, 16 insertions
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
Reviewed-by: Mikko Perttunen
On 01/27/2018 04:28 PM, Julia Lawall wrote:
Check the variable that was most recently initialized.
The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
//
@@
expression x, y, f, g, e, m;
statement S1,S2,S3,S4;
@@
x = f(...);
if
This nas been NAK'd before as harder to read than the current way.
Thanks,
Mikko
On 01/23/2018 10:29 PM, Christopher Díaz Riveros wrote:
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
This issue was detected by using the Coccinelle software.
Signed-off-by: Christopher Díaz Riveros
On 01/16/2018 12:06 AM, Lyude Paul wrote:
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a fa
On 11.01.2018 23:56, Rob Herring wrote:
On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to bo
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (6):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 246
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dt
FWIW, we had this problem some years ago with the Tegra CPU clock - then
it was determined that a simpler solution was to have the determine_rate
callback support unsigned long rates - so clock drivers that need to
return rates higher than 2^31 can instead implement the determine_rate
callback.
On 07.11.2017 23:23, Dmitry Osipenko wrote:
On 07.11.2017 15:28, Mikko Perttunen wrote:
On 05.11.2017 18:46, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
...
+static int mlock_id_for_class(unsigned int class)
+{
+#if HOST1X_HW >= 6
+switch (class)
+{
+c
On 11/29/2017 06:00 PM, Joshua Abraham wrote:
Signed-off-by: Joshua Abraham
This patch fixes the issue:
CHECK: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
---
drivers/staging/nvec/nvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 29.11.2017 14:18, Dmitry Osipenko wrote:
On 29.11.2017 12:10, Mikko Perttunen wrote:
On 12.11.2017 13:23, Dmitry Osipenko wrote:
On 11.11.2017 00:15, Dmitry Osipenko wrote:
On 07.11.2017 18:29, Dmitry Osipenko wrote:
On 07.11.2017 16:11, Mikko Perttunen wrote:
On 05.11.2017 19:14, Dmitry
On 29.11.2017 00:18, Vasyl Gomonovych wrote:
Fix ptr_ret.cocci warnings:
drivers/gpu/drm/tegra/gem.c:420:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Signed-off-by: Vasyl Gomonovych
---
On 12.11.2017 13:23, Dmitry Osipenko wrote:
On 11.11.2017 00:15, Dmitry Osipenko wrote:
On 07.11.2017 18:29, Dmitry Osipenko wrote:
On 07.11.2017 16:11, Mikko Perttunen wrote:
On 05.11.2017 19:14, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
Add an option to
On 16.11.2017 18:40, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
To allow client drivers to free resources when jobs have completed,
deliver job completion callbacks to them. This requires adding
reference counting to context objects, as job completion can happen
after
The upstream kernel currently has no core rail suspend support (LP0/SC7)
on Tegras - in general the downstream kernel (used e.g. in L4T) is the
reference that has the most functionality on Tegra.
IIRC the MMC subsystem and Tegra MMC driver between upstream and
downstream are currently quite di
Enable Tegra186 CPU frequency scaling support by default.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6356c6da34ea..42711031a72d 100644
--- a/arch/arm64
Enable Tegra BPMP thermal sensor support by default, built as a module.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 42711031a72d..d0f05da8baf9 100644
--- a
of_find_node_by_name() drops a reference to its first argument.
Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC")
Cc: stable # 4.0
Cc: Mikko Perttunen
Signed-off-by: Johan Hovold
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On 05.11.2017 19:14, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
Add an option to host1x_channel_request to interruptibly wait for a
free channel. This allows IOCTLs that acquire a channel to block
the userspace.
Wouldn't it be more optimal to request channel and
On 05.11.2017 19:43, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
In the traditional channel allocation model, a single hardware channel
was allocated for each client. This is simple from an implementation
perspective but prevents use of hardware scheduling.
This patch
On 05.11.2017 18:46, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
>> ...
+static int mlock_id_for_class(unsigned int class)
+{
+#if HOST1X_HW >= 6
+ switch (class)
+ {
+ case HOST1X_CLASS_HOST1X:
+ return 0;
+ case HOST1X_
for contexts.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 27 ---
drivers/gpu/drm/tegra/drm.h | 4
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 2cdd054520bf
The size of a single channel's aperture is different on Tegra186 vs.
previous chips. Parameterize the value using a new define in the
register definition headers.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 3 +--
drivers/gpu/host1x/hw/hw_host1x01_chan
Allow job submitters to set a callback to be called when the job has
completed. The jobs are stored and the callbacks called outside the
CDMA lock area to allow the callbacks to do CDMA-requiring operations
like freeing channels.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/cdma.c | 44
patch implements locking on all platforms from Tegra20 to
Tegra186.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/cdma.c | 1 +
drivers/gpu/host1x/cdma.h | 1 +
drivers/gpu/host1x/hw/cdma_hw.c| 122
As a preparation for each context potentially being able to have a
separate hardware channel, and thus requiring a separate syncpoint,
move syncpoints to be stored inside each context instead of global
client data.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 8
This ensures that there are no concurrency issues when multiple users
are trying to use VIC concurrently, and also simplifies the code
slightly.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/vic.c | 47 +++--
1 file changed, 20 insertions
patch only adapts VIC to the new model.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 46 ++
drivers/gpu/drm/tegra/drm.h | 7 +++-
drivers/gpu/drm/tegra/vic.c | 79 +++--
3 files changed, 92 insertions(+), 40
Add an option to host1x_channel_request to interruptibly wait for a
free channel. This allows IOCTLs that acquire a channel to block
the userspace.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 9 +
drivers/gpu/drm/tegra/gr2d.c | 6 +++---
drivers/gpu/drm/tegra
Add support for dumping current MLOCK state in debug dumps also
on T186, now that MLOCKs are used by the driver.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/debug_hw_1x06.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/host1x/hw
With the new channel allocation model, multiple threads can be
allocating channels simultaneously. Therefore we need to add a lock
around the code.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/channel.c | 7 +++
drivers/gpu/host1x/channel.h | 2 ++
2 files changed, 9 insertions
ested using the host1x_test test suite, and also by running
the performance test of host1x_test in parallel.
Thanks,
Mikko
Mikko Perttunen (10):
gpu: host1x: Parameterize channel aperture size
gpu: host1x: Print MLOCK state in debug dumps on T186
gpu: host1x: Add lock around channel allocatio
On 09/30/2017 05:41 AM, Dmitry Osipenko wrote:
On 28.09.2017 15:50, Mikko Perttunen wrote:
..
diff --git a/drivers/gpu/host1x/hw/channel_hw.c
b/drivers/gpu/host1x/hw/channel_hw.c
index 8447a56c41ca..b929d7f1e291 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw
This function actually doesn't sleep in the version that was merged.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
---
drivers/gpu/host1x/channel.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/chan
-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
---
drivers/gpu/host1x/hw/channel_hw.c | 22 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12
3 files changed, 46 insertions(+)
diff
y newlines
and by fixing other small issues.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
---
drivers/gpu/host1x/debug.c| 14 ++-
drivers/gpu/host1x/debug.h| 14 ---
drivers/gpu/host1x/hw/debug_hw.c
since that would require extra work and is unnecessary with
the current channel allocation model.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.h | 15 +
drivers/gpu/host1x/hw/channel_hw.c | 3 +++
drivers/gpu/host1x/hw/syncpt_hw.c | 46
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually. Also do
some other cleanup with user pointers to make them stand out more
and look cleaner.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 29
in case of job timeouts. They are now actually readable by humans
without use of additional scripts.
Patch 4 is a simple aesthetical fix to the TegraDRM submit path.
Everything was tested on TX1 and TX2 and should be applied on the
previously posted Tegra186 support series.
Cheers,
Mikko
Mikko
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/debug_hw.c | 59 ---
drivers/gpu/host1x/hw/debug_hw_1x01.c | 2 +-
drivers/gpu/host1x/hw
On 09/05/2017 04:33 PM, Dmitry Osipenko wrote:
On 05.09.2017 11:10, Mikko Perttunen wrote:
... >> diff --git a/drivers/gpu/host1x/hw/channel_hw.c
b/drivers/gpu/host1x/hw/channel_hw.c
index 8447a56c41ca..0161da331702 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/hos
Reviewed-by: Mikko Perttunen
Tested-by: Mikko Perttunen
Tested to work with Host1x :)
I noticed a slight difference with downstream where downstream has
global interrupts 170 and 171 - but looks like the latter is for secure
faults which we should never get so this way seems more correct
On 05.09.2017 14:10, Daniel Vetter wrote:
Since this is new hw support, is there also open source userspace using
all this?
The VIC HW in Tegra186 is backwards compatible with the one in Tegra210,
which has open userspace (https://github.com/cyndis/vaapi-tegra-driver),
so that userspace shou
Add a node for the Video Image Compositor on the Tegra186.
Signed-off-by: Mikko Perttunen
---
v2:
- Fixed reg property in accordance with changed parent cells.
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia
.
The series has been tested on the Jetson TX1 (T210) and TX2 (T186)
using the host1x_test test suite available at
http://github.com/cyndis/host1x_test
The series itself is available at
http://github.com/cyndis/linux, branch host1x-t186-1
Cheers,
Mikko
Mikko Perttunen (6):
arm64: tegra: Add
Add #power-domain-cells for the BPMP node on Tegra186 so that the power
domain provider may be used.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts
Add Tegra186 support for VIC - no changes are required except for new
firmware and compatibility string.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/tegra
Add the node for Host1x on the Tegra186, without any subdevices
for now.
Signed-off-by: Mikko Perttunen
---
v2:
- Changed address-cells and size-cells to 1 and fixed the ranges
property correspondingly.
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++
1 file changed, 18
this commit.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
---
drivers/gpu/host1x/Makefile| 3 +-
drivers/gpu/host1x/dev.c | 60 +++-
drivers/gpu/host1x/dev.h | 4 +
drivers/gpu/host1x
Add the Tegra186-specific hypervisor-related register range
properties.
Signed-off-by: Mikko Perttunen
---
v2:
- Dropped incorrect note about cells properties.
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 4
1 file changed, 4 insertions(+)
diff --git
a
y newlines
and by fixing other small issues.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
---
This uses pr_cont, which there are currently talks of being replaced
with something better. I kept using it here for now until there is
some conclusion of what&
since that would require extra work and is unnecessary with
the current channel allocation model.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Changed from set_protection(bool) to enable_protection
- Added some comments
- Added missing check for hv_regs being NULL in
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/debug_hw.c | 57 ---
drivers/gpu/host1x/hw/debug_hw_1x01.c | 3 +-
drivers/gpu/host1x/hw
-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
---
drivers/gpu/host1x/hw/channel_hw.c | 22 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12
3 files changed, 46 insertions(+)
diff
This function actually doesn't sleep in the version that was merged.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/channel.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c
index db9b91d1384c..2fb93c2
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu
tested on TX1 and TX2 and should be applied on the
previously posted Tegra186 support series.
Cheers,
Mikko
Mikko Perttunen (6):
gpu: host1x: Enable Tegra186 syncpoint protection
gpu: host1x: Enable gather filter
gpu: host1x: Improve debug disassembly formatting
gpu: host1x: Disassemble more
On 08/21/2017 08:27 PM, Mikko Perttunen wrote:
On 08/20/2017 07:59 PM, Dmitry Osipenko wrote:
On 20.08.2017 19:44, Dmitry Osipenko wrote:
On 20.08.2017 19:24, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
The gather filter is a feature present on Tegra124 and newer
On 08/20/2017 07:59 PM, Dmitry Osipenko wrote:
On 20.08.2017 19:44, Dmitry Osipenko wrote:
On 20.08.2017 19:24, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
The gather filter is a feature present on Tegra124 and newer where the
hardware prevents GATHERed command
On 08/19/2017 02:11 PM, Dmitry Osipenko wrote:
On 19.08.2017 13:35, Mikko Perttunen wrote:
On 08/19/2017 01:09 PM, Dmitry Osipenko wrote:
On 19.08.2017 11:10, Mikko Perttunen wrote:
[snip]
+host1x_hw_syncpt_set_protection(host, true);
Is it really okay to force the protection? Maybe
On 08/19/2017 01:42 PM, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
The gather filter is a feature present on Tegra124 and newer where the
hardware prevents GATHERed command buffers from executing commands
normally reserved for the CDMA pushbuffer which is maintained by
On 08/19/2017 01:09 PM, Dmitry Osipenko wrote:
On 19.08.2017 11:10, Mikko Perttunen wrote:
[snip]
+host1x_hw_syncpt_set_protection(host, true);
Is it really okay to force the protection? Maybe protection should be enabled
with a respect to CONFIG_TEGRA_HOST1X_FIREWALL? In that case we
On 08/19/2017 01:36 AM, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.
Enable this feature where available and assign syncpoints
On 08/19/2017 01:05 AM, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 9
y newlines
and by fixing other small issues.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/debug.c| 14 ++-
drivers/gpu/host1x/debug.h| 14 ---
drivers/gpu/host1x/hw/debug_hw.c | 46 ++-
drivers/gpu/host1x/hw/debug
-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 22 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/host1x/hw
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