From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
From: Tuomas Tynkkynen
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
Sorry, I was not aware of those options.
drivers/cpufreq/Kconfig.arm
On 11/07/2014 05:54 PM, Eduardo Valentin wrote:
Terve Mikko,
On Wed, Oct 15, 2014 at 01:05:19PM +0300, Mikko Perttunen wrote:
Eduardo: ping
I had no objections with the driver at this point. Neither with the DT
part. I decided to include it in my -linus queue, which means, it will
To better facilitate discussion, here's an outline of how the driver works:
emc_set_rate (CAR) gets called
The current timing (= rate,parent pair) is checked along with the
target timing.
If the target timing has the same clock source (~parent, see
emc_parent_clk_sources in the clk dr
On 11/06/2014 10:04 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree
On 11/06/2014 09:56 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen
Implements functionality needed to change the rate of the memory bus
clock.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
---
v2:* Use subsys_initcall(), so
Signed-off-by: Mikko Perttunen
---
v6:
- return unrounded rates from clk_round_rate and clk_recalc_rate. The rounded
rate doesn't make much sense for a voltage controlled oscillator and cpufreq
freaks out if any rounding happens to the CPU clock rate.
drivers/clk/tegra/clk-dfll.c
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v6:
- disable clks if resume fails
- cosmetic fix in error handling
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1090 ++
drivers/clk/tegra
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-dfll.c | 657 ++-
1 file changed, 654 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 358c5d4..e71f4fb 100644
--- a/drivers/clk/tegra/clk
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 +
2 files changed, 167 insertions(+)
create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
diff
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
- Style fixes
- Removed incorrect and unused DFLL_I2C_CFG_SLAVE_ADDR_MASK define
- Documented that dfll_register_clk can return -ENOMEM
- Harmonized clock operation order
- Check !soc before allocating
per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/mach-tegra/Kconfig | 1 +
drivers/clk/tegra/cvb.c
block will complete.
Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 47
From: Tuomas Tynkkynen
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 22 ++
1 file changed
From: Tuomas Tynkkynen
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1
From: Tuomas Tynkkynen
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file changed, 3 insertions(+), 1
From: Tuomas Tynkkynen
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v5:
- Don't name cpu@0 'cpu0'. Instead, we will reference by path.
arch/arm/boot/dts/te
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 69 ++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
diff --git a/Documentation/devicetree
driver
for all the cpufreq operations.
This driver also relies on the DFLL driver to fill the OPP table for the
CPU0 device, so that the cpufreq-dt driver knows what frequencies to
use.
Signed-off-by: Tuomas Tynkkynen
Acked-by: Viresh Kumar
Signed-off-by: Mikko Perttunen
---
v5:
- Use
ce2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (1):
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (14):
clk: tegra: Add binding f
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v5:
- Duplicate the cpus/cpu@0 structure here instead of referring to a named
'cpu0' node. This fits in better with the style used by Tegra device trees.
From: Tuomas Tynkkynen
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq/Kconfig.arm | 6 +-
drivers/cpufreq/Makefile
On 10/21/2014 05:45 PM, Tomeu Vizoso wrote:
Needed to properly decode the ram code register.
Signed-off-by: Tomeu Vizoso
---
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/nvidia,
At least this and 11/12 have lost my Signed-off-by.
Mikko
On 10/21/2014 05:45 PM, Tomeu Vizoso wrote:
From: Mikko Perttunen
The EMC driver needs to know the number of external memory devices and also
needs to update the EMEM configuration based on the new rate of the memory bus.
To know how
Eduardo: ping
Cheers,
Mikko
On 09/29/2014 05:17 PM, Mikko Perttunen wrote:
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones
On 10/10/2014 04:14 PM, Mark Rutland wrote:
On Fri, Oct 10, 2014 at 01:46:55PM +0100, Tomeu Vizoso wrote:
From: Mikko Perttunen
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
---
.../bindings/memory
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v7: bunch of style fixes
drivers/thermal
On 09/27/2014 03:06 PM, Juha-Matti Tilli wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
struct
On 09/29/2014 11:29 AM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:45 PM, Thierry Reding wrote:
[...]
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor
On 09/26/2014 02:45 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:13PM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature
On 09/26/2014 03:05 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 03:00:11PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features of
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis
From: Mikko Perttunen
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 47
From: Mikko Perttunen
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
Acked-by: Eduardo Valentin
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++
include/dt
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v6: fixed sparse warning for wrong order of
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis/linux.git soctherm-v6
Thanks,
Mikko
Mikko Perttunen (4):
of: Add bindings for nvidia,tegra124-soctherm
ARM
From: Mikko Perttunen
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen
---
v6: added comments to cooling map nodes
arch/arm/boot/dts
On 09/25/2014 08:59 AM, Thierry Reding wrote:
On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+ const struct tegra_tsensor *sensor,
+ struct
On 09/24/2014 09:48 PM, Eduardo Valentin wrote:
Hello Mikko,
On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees
On 09/17/2014 01:40 AM, Stephen Warren wrote:
That's a huge time-sink, unless I work out NFS root,
which probably isn't properly or easily supported by any distro.
FWIW, this is how I've been working, and it hasn't been /that/ difficult
to get working. The Tegra side is trivial, just append so
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
---
v4
From: Mikko Perttunen
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko
From: Mikko Perttunen
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
by the hardware. Add a property
From: Mikko Perttunen
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei
e the sensors.
Git repo at
git://github.com/cyndis/linux.git pmc-thermtrip-v3
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C bindings
ARM: tegra124: Add I2C controller ids to device tree
ARM: tegra
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
---
v3
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required.
The
:22 PM, Tomeu Vizoso wrote:
On 26 August 2014 09:42, Mikko Perttunen wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The serie
8/21/2014 08:54 PM, Stephen Warren wrote:
On 08/21/2014 10:53 AM, Thierry Reding wrote:
On Thu, Aug 21, 2014 at 09:38:29AM -0600, Stephen Warren wrote:
On 08/21/2014 12:58 AM, Thierry Reding wrote:
On Wed, Aug 20, 2014 at 02:16:49PM -0600, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko
From: Mikko Perttunen
Currently the i2c-tegra bus driver prepares, enables
and set_rates its clocks separately for each transfer.
This causes locking problems when doing I2C transfers
from clock notifiers; see
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268653.html
This
Moi Eduardo,
can you ack this series or is there still something to do?
Thanks,
Mikko
On 21/08/14 19:01, Eduardo Valentin wrote:
Hello Juha-Matti,
On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
this series
This enables AHCI_TEGRA by default. This driver is required
for Serial ATA support on Tegra124-based boards.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs
: Mikko Perttunen
---
v2: reordered and separated includes
drivers/ata/ahci_tegra.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index f1fef74..0329044 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata
On 26/08/14 10:47, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 26, 2014 at 10:42:21AM +0300, Mikko Perttunen wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The series has been tested on Jetson TK1.
The first two patches remove the old "em
On 25/08/14 22:22, Stephen Warren wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Th
On 25/08/14 20:23, Stephen Warren wrote:
On 07/16/2014 02:54 AM, Mikko Perttunen wrote:
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
I have applied patches 2 and 3 to Tegra's for-3.18/dt branch. I fixed
t
FWIW, please fix the authorship information for next version.
Cheers,
Mikko
On 25/08/14 09:29, Wei Ni wrote:
From: lightning314
Split set&show temp codes as common functions, so we can use it
directly when implement linux thermal framework.
And handle error return value for the lm90_select_re
On 21/08/14 18:40, Stephen Warren wrote:
On 08/21/2014 07:11 AM, Mikko Perttunen wrote:
On 20/08/14 23:25, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Perttunen wrote:
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is
On 20/08/14 23:25, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Perttunen wrote:
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis/linux.git soctherm-v5
Thanks,
Mikko
Mikko Perttunen (4):
of: Add bindings for nvidia,tegra124-soctherm
ARM
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen
---
v5: reordered nodes
arch/arm/boot/dts/tegra124.dtsi | 47
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v5:
- changed tsample_ate to 480
- constified structs
- added missing
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++
include/dt-bindings/thermal/tegra124-soctherm.h| 13 ++
2
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen
---
v5: added cooling-maps nodes
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 41
On 20/08/14 22:50, Stephen Warren wrote:
On 08/06/2014 04:25 AM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Since both
On 20/08/14 22:44, Stephen Warren wrote:
On 08/06/2014 04:25 AM, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
diff --git a/arch/arm/boot
On 08/19/2014 05:33 PM, edubez...@gmail.com wrote:
Juha-Matti, moro,
On Tue, Aug 19, 2014 at 10:09 AM, Juha-Matti Tilli
wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling f
On 19/08/14 17:09, Juha-Matti Tilli wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
I have several comments about this patch. Overall, the code lo
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v4:
- constified struct
- added bunch of defines for masks and shifts
/unprepare and clk_set_rate calls to
the probe function, leaving only clk_enable/disable to be
done on each transfer. This solves the locking issue.
Signed-off-by: Mikko Perttunen
---
drivers/i2c/busses/i2c-tegra.c | 57 +-
1 file changed, 45 insertions(+), 12
e the sensors.
Git repo at
git://github.com/cyndis/linux.git pmc-thermtrip-v2
Testing script at https://gist.github.com/cyndis/66126c9c176b5f94a76f.
If your fan stops it is working.
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controll
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required.
Signed-off-by: Mikko
device tree
bindings, so that drivers can know what ID to write to a hardware
register when configuring a block that sends I2C messages autonomously.
Signed-off-by: Mikko Perttunen
---
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 5 +
1 file changed, 5 insertions(+)
diff
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 6
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
---
.../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 21
On 13/08/14 13:53, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 13, 2014 at 01:41:52PM +0300, Mikko Perttunen wrote:
On 13/08/14 13:36, Thierry Reding wrote:
Old Signed by an unknown key
On Wed, Aug 13, 2014 at 12:52:22PM +0300, Mikko Perttunen wrote:
On 13/08/14 11
On 13/08/14 13:36, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 13, 2014 at 12:52:22PM +0300, Mikko Perttunen wrote:
On 13/08/14 11:57, Thierry Reding wrote:
Old Signed by an unknown key
On Wed, Aug 13, 2014 at 11:42:53AM +0300, Mikko Perttunen wrote:
On 13/08/14 11
On 13/08/14 11:57, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 13, 2014 at 11:42:53AM +0300, Mikko Perttunen wrote:
On 13/08/14 11:12, Mikko Perttunen wrote:
On 13/08/14 11:07, Thierry Reding wrote:
Old Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:57AM
On 13/08/14 11:12, Mikko Perttunen wrote:
On 13/08/14 11:07, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:57AM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for hardware-triggered thermal reset to the PMC
driver. Namely, it adds device
On 13/08/14 11:07, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:57AM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for hardware-triggered thermal reset to the PMC
driver. Namely, it adds device tree properties for specifying the I2C
command
On 13/08/14 11:03, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 13, 2014 at 10:52:18AM +0300, Mikko Perttunen wrote:
On 13/08/14 10:37, Thierry Reding wrote:
Old Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:59AM +0300, Mikko Perttunen wrote:
This adds the
On 13/08/14 10:53, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 05, 2014 at 11:13:00AM +0300, Mikko Perttunen wrote:
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra114 and Tegra124. The
On 13/08/14 10:37, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:59AM +0300, Mikko Perttunen wrote:
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC
On 13/08/14 10:35, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 05, 2014 at 11:12:58AM +0300, Mikko Perttunen wrote:
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant
On 11/08/14 16:32, Eduardo Valentin wrote:
Hello Mikko,
It follows more small comments.
On Wed, Aug 6, 2014 at 6:25 AM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
: Mikko Perttunen
---
drivers/ata/ahci_tegra.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index f1fef74..ad99e0f5 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -26,6 +26,7 @@
#include
Before this patch, the driver included ,
which was effectively renamed to at about the same
time the ahci_tegra series landed. Fix the include path so that the
driver compiles.
Signed-off-by: Mikko Perttunen
---
This would be for 3.17.
drivers/ata/ahci_tegra.c | 2 +-
1 file changed, 1
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 47
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
---
v3: updated text slightly, added example using define
.../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++
include/dt-bindings/thermal/tegra124
branch is also available in my github repo,
git://github.com/cyndis/linux.git soctherm-v3
Thanks,
Mikko
Mikko Perttunen (4):
of: Add bindings for nvidia,tegra124-soctherm
ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
ARM: tegra: Add thermal trip points for Jetson TK1
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