Re: [v4] PCI: Avoid unsync of LTR mechanism configuration

Hi Bjorn, On Thu, 2021-02-18 at 10:50 -0600, Bjorn Helgaas wrote: > On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is >

Re: [v3] PCI: Avoid unsync of LTR mechanism configuration

Hi, On Mon, 2021-02-01 at 13:32 +0200, Mika Westerberg wrote: > Hi, > > On Fri, Jan 29, 2021 at 03:11:37PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register i

Re: [v2] PCI: Avoid unsync of LTR mechanism configuration

On Thu, 2021-01-28 at 16:27 +0200, Mika Westerberg wrote: > Hi, > > On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register i

Re: [PATCH v2] PCI: Re-enable downstream port LTR if it was previously enabled

On Fri, 2021-01-22 at 07:20 -0600, Bjorn Helgaas wrote: > On Fri, Jan 22, 2021 at 03:03:11PM +0800, Mingchuang Qiao wrote: > > On Thu, 2021-01-21 at 16:31 -0600, Bjorn Helgaas wrote: > > > [+cc Alex and Mingchuang et al from > > > https://lore.kernel.org/r/20210112

Re: [PATCH v2] PCI: Re-enable downstream port LTR if it was previously enabled

On Thu, 2021-01-21 at 16:31 -0600, Bjorn Helgaas wrote: > [+cc Alex and Mingchuang et al from > https://lore.kernel.org/r/20210112072739.31624-1-mingchuang.q...@mediatek.com] > > On Tue, Jan 19, 2021 at 04:14:10PM +0300, Mika Westerberg wrote: > > PCIe r5.0, sec 7.5.3.16 says that the downstream

Re: [PATCH] pci: avoid unsync of LTR mechanism configuration

On Tue, 2021-01-12 at 15:36 -0600, Bjorn Helgaas wrote: > Note subject line tips at > https://lore.kernel.org/r/20171026223701.ga25...@bhelgaas-glaptop.roam.corp.google.com > > On Tue, Jan 12, 2021 at 03:27:39PM +0800, mingchuang.q...@mediatek.com wrote: > > Fro