card. In contrast, without affinity,
all MSIRs can be used for core 0, the MSI interrupts can up to 32.
So the parameter is added to control affinity mode.
"lsmsi=no-affinity" will disable affinity and increase MSI
interrupt number.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
card. In contrast, without affinity,
all MSIRs can be used for core 0, the MSI interrupts can up to 32.
So the parameter is added to control affinity mode.
"lsmsi=no-affinity" will disable affinity and increase MSI
interrupt number.
Signed-off-by: Minghuan Lian
---
v3-v2:
- 1. update the d
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v3-v2:
- keep the old misspelled compatible strings
v2-v1:
- MSI dts node change has been merged into the patch 6/9
drivers/irqchip/irq-ls-scfg-msi.c
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian
---
v3-v2:
- keep the old misspelled compatible strings
v2-v1:
- MSI dts node change has been merged into the patch 6/9
drivers/irqchip/irq-ls-scfg-msi.c | 165
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v3-v1:
- None
.../interrup
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v3-v1:
- None
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
drivers
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v3-v2:
- None
v2-v1:
- change whitespace number
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v3-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arc
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v3-v2:
- None
v2-v1:
- change whitespace number
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
v3-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v3-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v3-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file chan
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v3-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dt
This patch set is to update Layerscape MSI driver.
1. fix the compatible strings typo
2. Add MSI support to LS1046a
3. Add MSI support to LS1043a v1.1
4. Add MSI affinity support
Minghuan Lian (9):
irqchip/ls-scfg-msi: fix typo of MSI compatible strings
arm: dts: ls1021a: fix typo of MSI
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
v3-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dt
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
v3-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
v3-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3
This patch set is to update Layerscape MSI driver.
1. fix the compatible strings typo
2. Add MSI support to LS1046a
3. Add MSI support to LS1043a v1.1
4. Add MSI affinity support
Minghuan Lian (9):
irqchip/ls-scfg-msi: fix typo of MSI compatible strings
arm: dts: ls1021a: fix typo of MSI
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v3-v1:
- None
.../devicetree/bindings/interrupt-contr
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v3-v1:
- None
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt| 6 +++---
drivers/irqch
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
v2-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dt
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arc
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dt
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
v2-v1:
- None
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v2-v1:
- change whitespace number
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/ar
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v2-v1:
- change whitespace number
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 31
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v2-v1:
- None
.../interrup
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v2-v1:
- None
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file chan
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
v2-v1:
- None
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- MSI dts node change has been merged into the patch 6/9
drivers/irqchip/irq-ls-scfg-msi.c | 161 +-
1 file change
, the bits of all 4 MSIR will be reserved.
The parameter 'msi_affinity_flag' is provide to change this mode.
"lsmsi=no-affinity" will disable affinity, all MSI can only be
associated with CPU 0.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
v2-v1:
- None
drivers/irqchip/i
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian
---
v2-v1:
- MSI dts node change has been merged into the patch 6/9
drivers/irqchip/irq-ls-scfg-msi.c | 161 +-
1 file changed, 126 insertions(+), 35
, the bits of all 4 MSIR will be reserved.
The parameter 'msi_affinity_flag' is provide to change this mode.
"lsmsi=no-affinity" will disable affinity, all MSI can only be
associated with CPU 0.
Signed-off-by: Minghuan Lian
---
v2-v1:
- None
drivers/irqchip/irq-ls-scfg-
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
v2-v1:
- None
.../devicetree/bindings/interrupt-contr
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian
Acked-by: Rob Herring
---
v2-v1:
- None
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt| 6 +++---
drivers/irqch
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
drivers/irqchip/
in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
drivers/irqchip/irq-ls-scfg-msi.c
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insert
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 2 +-
drivers/irqchip/irq-ls-scfg-msi.c | 161 -
2 files change
MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 2 +-
drivers/irqchip/irq-ls-scfg-msi.c | 161 -
2 files changed, 127 insertions(+), 36 deletions
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 31 ++
2 files chang
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 31 ++
2 files changed, 32 insertions(+)
diff --git
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt| 6 +++---
drivers
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian
---
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt| 6 +++---
drivers/irqchip/irq-ls-scfg-msi.c
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
in
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes msi-parent to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
, the bits of all 4 MSIR will be reserved.
The parameter 'msi_affinity_flag' is provide to change this mode.
"lsmsi=no-affinity" will disable affinity, all MSI can only be
associated with CPU 0.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
drivers/irqchip/irq-ls
, the bits of all 4 MSIR will be reserved.
The parameter 'msi_affinity_flag' is provide to change this mode.
"lsmsi=no-affinity" will disable affinity, all MSI can only be
associated with CPU 0.
Signed-off-by: Minghuan Lian
---
drivers/irqchip/irq-ls-scfg-
LS1046a has three MSI controllers. each controller is assigned
four SPI interrupts.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/bo
LS1046a has three MSI controllers. each controller is assigned
four SPI interrupts.
Signed-off-by: Minghuan Lian
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b
a MSI interrupt affinity, the MSI message
data will be changed to refer to a new MSIR that has
been associated with the core.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
The patch depends on https://patchwork.kernel.org/patch/9342915/
drivers/irqchip/irq-ls-scfg-msi.c
a MSI interrupt affinity, the MSI message
data will be changed to refer to a new MSIR that has
been associated with the core.
Signed-off-by: Minghuan Lian
---
The patch depends on https://patchwork.kernel.org/patch/9342915/
drivers/irqchip/irq-ls-scfg-msi.c | 444
From: Gong Qianyu <qianyu.g...@nxp.com>
In order to support kvm, rev1.1 LS1043a GIC register has been
changed to align as 64K. The patch updates GIC node according to
the rev1.1 hardware.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Minghuan Lian <minghu
1. Change compatible to "fsl,ls-scfg-msi"
2. Move two MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the two MSI controllers.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm/
From: Gong Qianyu
In order to support kvm, rev1.1 LS1043a GIC register has been
changed to align as 64K. The patch updates GIC node according to
the rev1.1 hardware.
Signed-off-by: Gong Qianyu
Signed-off-by: Minghuan Lian
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8
1
1. Change compatible to "fsl,ls-scfg-msi"
2. Move two MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the two MSI controllers.
Signed-off-by: Minghuan Lian
---
arch/arm/boot/dts/ls1021a.dtsi | 28
1. Change compatible to "fsl,ls-scfg-msi"
2. Move three MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the three MSI controllers.
3. The rev1.1 of LS1043a moves PCIe INTB/C/D interrupts to MSI controller.
Signed-off-by: Mingh
1. Change compatible to "fsl,ls-scfg-msi"
2. Move three MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the three MSI controllers.
3. The rev1.1 of LS1043a moves PCIe INTB/C/D interrupts to MSI controller.
Signed-off-by: Minghuan L
e MSI controllers.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 57 +++---
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
e MSI controllers.
Signed-off-by: Minghuan Lian
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 57 +++---
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
b/Documentation/devicetree/bin
LS1046a has three PCIe controllers.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 66 ++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/bo
LS1046a has three PCIe controllers.
Signed-off-by: Minghuan Lian
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 66 ++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
nal Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, April 22, 2016 3:43 PM
> To: Leo Li <pku@gmail.com>
> Cc: Minghuan Lian <minghuan.l...@nxp.com>;
> linux-arm-ker...@lists.infradead.org; lkml <linux-kernel@vger.kernel.org>;
> Thom
nal Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, April 22, 2016 3:43 PM
> To: Leo Li
> Cc: Minghuan Lian ;
> linux-arm-ker...@lists.infradead.org; lkml ;
> Thomas Gleixner ; Jason Cooper
> ; Roy Zang ; Mingkai Hu
> ; Stuart Yoder ; Yang-Le
Add SCFG MSI dts node and add msi-parent property to PCIe dts node
that points to the corresponding MSI node.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/bo
Add SCFG MSI dts node and add msi-parent property to PCIe dts node
that points to the corresponding MSI node.
Signed-off-by: Minghuan Lian
---
arch/arm/boot/dts/ls1021a.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts
Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
Tested-by: Alexander Stein <ale
Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian
Tested-by: Alexander Stein
Acked-by: Marc Zyngier
---
Change log
v6
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
change log:
v6-v4: no change
v
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian
---
change log:
v6-v4: no change
v4: add interrupt-parent
>hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
desc);
}
Thanks,
Minghuan
> -Original Message-
> From: Alexander Stein [mailto:alexander.st...@systec-electronic.com]
> Sent: Wednesday, March 23, 2016 5:18 PM
> To: linux-kerne
>hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
desc);
}
Thanks,
Minghuan
> -Original Message-
> From: Alexander Stein [mailto:alexander.st...@systec-electronic.com]
> Sent: Wednesday, March 23, 2016 5:18 PM
> To: linux-kernel@
Hi Rob Herring,
Could you help to review this patch?
Thanks a lot.
Regards,
Minghuan
> -Original Message-
> From: Minghuan Lian [mailto:minghuan.l...@nxp.com]
> Sent: Monday, March 07, 2016 11:36 AM
> To: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.or
Hi Rob Herring,
Could you help to review this patch?
Thanks a lot.
Regards,
Minghuan
> -Original Message-
> From: Minghuan Lian [mailto:minghuan.l...@nxp.com]
> Sent: Monday, March 07, 2016 11:36 AM
> To: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.or
Some kind of NXP Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
Change log
v5:
1. drop nr_irqs from
Some kind of NXP Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian
---
Change log
v5:
1. drop nr_irqs from struct ls_scfg_msi
v4:
1. do
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
change log:
v4: add interrupt-
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian
---
change log:
v4: add interrupt-parent description
v3-v1
Hi Marc,
Please see my comments inline.
Thanks,
Minghaun
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Monday, February 29, 2016 6:14 PM
> To: Minghuan Lian <minghuan.l...@nxp.com>;
> linux-arm-ker...@lists.infradead.org
>
Hi Marc,
Please see my comments inline.
Thanks,
Minghaun
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Monday, February 29, 2016 6:14 PM
> To: Minghuan Lian ;
> linux-arm-ker...@lists.infradead.org
> Cc: Thomas Gleixner ; Jason C
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
change log:
v4: add interrupt-
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian
---
change log:
v4: add interrupt-parent description
v3-v1
Some kind of NXP Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com>
---
Change log
v4:
1. do not register irq_
Some kind of NXP Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian
---
Change log
v4:
1. do not register irq_enable irq_disable
2. shorten
2016 1:30 AM
> To: Minghuan Lian <minghuan.l...@nxp.com>;
> linux-arm-ker...@lists.infradead.org
> Cc: Thomas Gleixner <t...@linutronix.de>; Jason Cooper
> <ja...@lakedaemon.net>; Roy Zang <roy.z...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; Stuar
2016 1:30 AM
> To: Minghuan Lian ;
> linux-arm-ker...@lists.infradead.org
> Cc: Thomas Gleixner ; Jason Cooper
> ; Roy Zang ; Mingkai Hu
> ; Stuart Yoder ; Yang-Leo Li
> ; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/2 v3] irqchip/Layerscape: Add SCFG MSI controller
>
The patch is ok to me.
Thanks,
Minghuan
> -Original Message-
> From: Bhupesh Sharma
> Sent: Friday, February 05, 2016 1:36 PM
> To: Shi, Yang ; Bjorn Helgaas ;
> Yang-Leo Li ; shawn@linaro.org
> Cc: Mingkai Hu ; Minghuan Lian
> ; bhelg...@google.com; linu
aro.org
> Cc: Mingkai Hu <mingkai...@nxp.com>; Minghuan Lian
> <minghuan.l...@nxp.com>; bhelg...@google.com; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linaro-ker...@lists.linaro.org
> Subject: RE: [PATCH] PCI: layers
Commit-ID: 3ad2a5f57656a14d964b673a5a0e4ab0e583c870
Gitweb: http://git.kernel.org/tip/3ad2a5f57656a14d964b673a5a0e4ab0e583c870
Author: Minghuan Lian
AuthorDate: Wed, 20 May 2015 10:13:15 -0500
Committer: Thomas Gleixner
CommitDate: Wed, 20 May 2015 22:13:37 +0200
irqchip/gicv3-its
Commit-ID: 3ad2a5f57656a14d964b673a5a0e4ab0e583c870
Gitweb: http://git.kernel.org/tip/3ad2a5f57656a14d964b673a5a0e4ab0e583c870
Author: Minghuan Lian minghuan.l...@freescale.com
AuthorDate: Wed, 20 May 2015 10:13:15 -0500
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 20
page number will cause
kernel hang.
Signed-off-by: Minghuan Lian
---
v2-v1:
Increase allocation size instead of decreasing PSZ
drivers/irqchip/irq-gic-v3-its.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
page number will cause
kernel hang.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
v2-v1:
Increase allocation size instead of decreasing PSZ
drivers/irqchip/irq-gic-v3-its.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b
100 matches
Mail list logo
