> boot time).
>
> However we do not need to sleep as we can instead mark a point of time
> in the future when we should start processing the events.
>
> Reported-by: Nicolas Boichat
> Signed-off-by: Dmitry Torokhov
> ---
> drivers/hid/usbhid/hid-core.c | 27 +++
ss the maintainer can help you with that.
> --->This --- is automatically generated, it looks like I can't move it to
> below ---
Sure, but you can always edit the message before you send it
(--annotate parameter of git send-email).
>
> -- Original --
> From: "
pecific, you can drop this line.
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: ST Lin
Tested-by: Nicolas Boichat
>
> This patch copied from:https://patchwork.ozlabs.org/patch/1150756/,
> The original patch is invalid,so re-submit a new patch for this.
This belongs below
Hi,
First, you need to cc linux-...@lists.infradead.org, make sure to use
the get_maintainer.pl script to get the cc list (you're cc-ing mm
people here, but you should cc mtd folks instead).
On Sun, Apr 26, 2020 at 11:24 AM wrote:
>
> From: wuxy
>
> Winbond has new 1.8V SPI NOR Flash IDs,we
On Mon, Apr 27, 2020 at 2:18 PM Xin Ji wrote:
>
> The ANX7625 is an ultra-low power 4K Mobile HD Transmitter designed
> for portable device. It converts MIPI DSI/DPI to DisplayPort 1.3 4K.
>
> The ANX7625 can support both USB Type-C PD feature and MIPI DSI/DPI
> to DP feature. This driver only
On Thu, Oct 10, 2019 at 5:11 PM Tomasz Figa wrote:
>
> On Thu, Oct 10, 2019 at 6:08 PM Nicolas Boichat wrote:
> >
> > On Thu, Oct 10, 2019 at 3:50 PM Tomasz Figa wrote:
> > >
> > > MediaTek XHCI host controller does not support 64-bit addressing despite
>
On Thu, Oct 10, 2019 at 3:50 PM Tomasz Figa wrote:
>
> MediaTek XHCI host controller does not support 64-bit addressing despite
> the AC64 bit of HCCPARAMS1 register being set. The platform-specific
> glue sets the DMA mask to 32 bits on its own, but it has no effect,
> because xhci_gen_setup()
Some other hammer-like device will emit a similar code, let's look for
the folded event in HID usage table, instead of hard-coding whiskers
in many places.
Signed-off-by: Nicolas Boichat
---
drivers/hid/hid-google-hammer.c | 53 -
1 file changed, 25 insertions
Add 2 additional hammer-like devices.
Signed-off-by: Nicolas Boichat
---
drivers/hid/hid-google-hammer.c | 4
drivers/hid/hid-ids.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/hid/hid-google-hammer.c b/drivers/hid/hid-google-hammer.c
index 31e4a39946f59ad
On Fri, Aug 2, 2019 at 9:13 PM Shik Chen wrote:
>
> Similar to the commit 1161db6776bd ("media: usb: pwc: Don't use coherent
> DMA buffers for ISO transfer") [1] for the pwc driver. Use streaming DMA
> APIs to transfer buffers and sync them explicitly, because accessing
> buffers allocated by
Thanks Rob and Alyssa.
+Douglas Anderson +Dominik Behr who may be interested (if not already aware)
On Sat, Sep 14, 2019 at 2:17 AM Alyssa Rosenzweig
wrote:
>
> > > > The binding we use with out-of-tree Mali drivers includes more
> > > > clocks, I assume this would be required eventually if we
On Sat, Sep 14, 2019 at 6:03 AM Dmitry Torokhov wrote:
>
> The USB interface may get detected before the platform/EC one, so let's
> note the state of the base (if we receive event) and use it to correctly
> initialize the tablet mode switch state.
>
> Also let's start the HID interface
Thanks for the quick review!
On Thu, Sep 5, 2019 at 5:09 PM Rob Herring wrote:
>
> On Thu, Sep 5, 2019 at 9:16 AM Nicolas Boichat wrote:
> >
> > Add a basic GPU node and opp table for mt8183.
> >
> > The binding we use with out-of-tree Mali drivers includes more
&
< CLK_MFG_BG3D>;
clock-names =
"clk_main_parent",
"clk_mux",
"clk_sub_parent",
"subsys_mfg_cg";
Signed-off-by: Nicolas Boichat
---
Upstreaming what matches existing bindings from our Chromium OS tree:
https://chromiu
he missing mask.
>
> Fixes: d096aa3eb604 ("Input: cros_ec_keyb: mask out extra flags in
> event_type")
> Signed-off-by: Fei Shao
Reviewed-by: Nicolas Boichat
> ---
> drivers/input/keyboard/cros_ec_keyb.c | 6 --
> 1 file changed, 4 insertions(+), 2 deleti
~2.5MB of RAM), but the memory would later be freed
(early_log is __initdata).
Suggested-by: Dmitry Vyukov
Signed-off-by: Nicolas Boichat
---
lib/Kconfig.debug | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index f567875b87657de
On Wed, Jul 24, 2019 at 2:01 AM Andrey Ryabinin wrote:
>
>
>
> On 7/23/19 11:13 AM, Nicolas Boichat wrote:
> > On Tue, Jul 23, 2019 at 3:46 PM Dmitry Vyukov wrote:
> >>
> >> On Tue, Jul 23, 2019 at 9:26 AM Nicolas Boichat
> >> wrote:
>
On Tue, Jul 23, 2019 at 3:46 PM Dmitry Vyukov wrote:
>
> On Tue, Jul 23, 2019 at 9:26 AM Nicolas Boichat wrote:
> >
> > When KASan is enabled, a lot of memory is allocated early on,
> > and kmemleak complains (this is on a 4GB RAM system):
> > kmemleak: Early log bu
(each early_log entry is 160 bytes), but
the memory would later be freed (early_log is __initdata).
Signed-off-by: Nicolas Boichat
---
lib/Kconfig.debug | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index f567875b87657de..1a197b8125768b9
On Wed, Jul 17, 2019 at 7:17 AM Florian Fainelli wrote:
>
> On 7/16/19 4:12 PM, Rob Herring wrote:
> > On Tue, Jul 16, 2019 at 4:46 PM Florian Fainelli
> > wrote:
> >>
> >> On 7/2/19 10:08 PM, Nicolas Boichat wrote:
> >>> If the dev
On Thu, Jul 18, 2019 at 4:01 PM Zhiyong Tao wrote:
>
> This patch support efuse calibration in auxadc driver
>
> Signed-off-by: Zhiyong Tao
> Signed-off-by: jg_poxu
> ---
> drivers/iio/adc/mt6577_auxadc.c | 71
> +
> 1 file changed, 71 insertions(+)
>
>
as memblock
explicitly allows reserved regions to overlap, and the commit
that this fixes removed the check for that precise reason.
Fixes: 094cb98179f19b7 ("of/fdt: memblock_reserve /memreserve/ regions in the
case of partial overlap")
Signed-off-by: Nicolas Boichat
---
drivers/of/fdt.c | 10
On Thu, Jun 27, 2019 at 9:48 AM Stephen Rothwell wrote:
>
> Hi Nicolas,
>
> On Thu, 27 Jun 2019 08:32:34 +0800 Nicolas Boichat
> wrote:
> >
> > Ouch, sorry, for some reasons I thought it was 10, not 12...
>
> It used to be 10, but will slowly grow over time.
On Wed, Jun 26, 2019 at 10:11 PM Linus Walleij wrote:
>
> On Wed, Jun 26, 2019 at 3:50 PM Stephen Rothwell
> wrote:
>
> > In commit
> >
> > 99fd24aa4a45 ("pinctrl: mediatek: Ignore interrupts that are wake only
> > during resume")
> >
> > Fixes tag
> >
> > Fixes: bf22ff45bed ("genirq:
and suspend
resume")
Signed-off-by: Nicolas Boichat
Acked-by: Sean Wang
---
Applies on top of linux-pinctrl.git/fixes.
Changes from v2:
- Added Fixes tag
- Reworded the commit message, added an example. Sean: I hope
that's what you had in mind, I can reword further,
On Wed, Jun 12, 2019 at 4:53 PM Bibby Hsieh wrote:
>
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
>
On Mon, Jun 3, 2019 at 4:01 PM Chuanjia Liu wrote:
>
> On Fri, 2019-05-31 at 10:17 -0700, Evan Green wrote:
> > On Fri, May 31, 2019 at 1:06 AM Chuanjia Liu
> > wrote:
> > >
> > > On Thu, 2019-05-30 at 10:12 -0700, Evan Green wrote:
> > > >
In Chromium OS kernel builds, we split the debug information as
.ko.debug files, and that's what decode_stacktrace.sh needs to use.
Relax objfile matching rule to allow any .ko* file to be matched.
Signed-off-by: Nicolas Boichat
---
Changes since v1:
- Added quotes around name pattern.
(note
On Tue, May 28, 2019 at 4:38 PM Konstantin Khlebnikov
wrote:
>
> On 22.05.2019 2:41, Nicolas Boichat wrote:
> > In Chromium OS kernel builds, we split the debug information as
> > .ko.debug files, and that's what decode_stacktrace.sh needs to use.
> >
> > Relax objf
In Chromium OS kernel builds, we split the debug information as
.ko.debug files, and that's what decode_stacktrace.sh needs to use.
Relax objfile matching rule to allow any .ko* file to be matched.
Signed-off-by: Nicolas Boichat
---
scripts/decode_stacktrace.sh | 2 +-
1 file changed, 1
On Tue, May 21, 2019 at 12:10 PM Hsin-Yi Wang wrote:
>
> On Mon, May 20, 2019 at 7:54 AM Nicolas Boichat wrote:
>
> > Alphabetical order.
> Original headers are not sorted, should I sort them here?
> >
>
> >
> > I'm a little bit concerned about this, a
On Tue, May 21, 2019 at 4:01 PM kbuild test robot wrote:
> sparse warnings: (new ones prefixed by >>)
>
> >> mm/failslab.c:27:26: sparse: sparse: restricted gfp_t degrades to integer
> 26 if (failslab.ignore_gfp_reclaim &&
> > 27 (gfpflags &
l intent of the code, by ignoring calls
that directly reclaim only (__GFP_DIRECT_RECLAIM), and thus,
failing GFP_ATOMIC calls again by default.
Fixes: 71baba4b92dc1fa1 ("mm, page_alloc: rename __GFP_WAIT to __GFP_RECLAIM")
Signed-off-by: Nicolas Boichat
Reviewed-by: Akinobu Mita
Acked-by: Davi
On Tue, May 21, 2019 at 12:29 AM Akinobu Mita wrote:
>
> 2019年5月20日(月) 13:49 Nicolas Boichat :
> >
> > When failslab was originally written, the intention of the
> > "ignore-gfp-wait" flag default value ("N") was to fail
> > GFP_ATO
l intent of the code, by ignoring calls
that directly reclaim only (___GFP_DIRECT_RECLAIM), and thus,
failing GFP_ATOMIC calls again by default.
Fixes: 71baba4b92dc1fa1 ("mm, page_alloc: rename __GFP_WAIT to __GFP_RECLAIM")
Signed-off-by: Nicolas Boichat
---
mm/failslab.c | 3 ++-
1 file change
s/amr64/arm64/ in the commit title.
On Mon, May 20, 2019 at 1:09 AM Hsin-Yi Wang wrote:
>
> Currently in arm64, FDT is mapped to RO before it's passed to
> early_init_dt_scan(). However, there might be some code that needs
> to modify FDT during init.
I'd give a specific example (i.e. mention
On Mon, May 20, 2019 at 1:09 AM Hsin-Yi Wang wrote:
>
> Introducing a chosen node, rng-seed, which is an entropy that can be
> passed to kernel called very early to increase initial device
> randomness. Bootloader should provide this entropy and the value is
> read from /chosen/rng-seed in DT.
>
The basepath may contain special characters, which would confuse
the regex matcher. ${var#prefix} does the right thing.
Fixes: 67a28de47faa8358 ("scripts/decode_stacktrace: only strip base path when
a prefix of the path")
Signed-off-by: Nicolas Boichat
Reviewed-by: Stephen Boyd
On Thu, May 16, 2019 at 7:55 PM Linus Walleij wrote:
>
> On Wed, May 8, 2019 at 9:33 AM Nicolas Boichat wrote:
>
> > This adds support for wake sources in pinctrl-mtk-common-v2, and
> > pinctrl-mt8183. Without this patch, all interrupts that are left
> > enabled on
On Sat, Apr 27, 2019 at 11:36 AM Long Cheng wrote:
>
> Modify uart rx and complete for DMA.
I don't know much about the DMA framework, but can you please explain
why you are making the changes in this CL? I see that you are dropping
dma_sync_single_for_device calls, for example, why?
>
>
On Wed, May 15, 2019 at 4:14 AM Stephen Boyd wrote:
>
> Quoting Nicolas Boichat (2019-05-13 18:37:58)
> > On Tue, May 14, 2019 at 6:29 AM Stephen Boyd wrote:
> > >
> > > Quoting Nicolas Boichat (2019-04-28 20:55:15)
> > > > During suspend
On Tue, May 14, 2019 at 6:29 AM Stephen Boyd wrote:
>
> Quoting Nicolas Boichat (2019-04-28 20:55:15)
> > During suspend/resume, mtk_eint_mask may be called while
> > wake_mask is active. For example, this happens if a wake-source
> > with an active interrupt handler w
On Thu, May 2, 2019 at 7:45 PM michael.kao wrote:
>
> From: Michael Kao
>
> Provide thermal zone to read thermal sensor
> in the SoC. We can read all the thermal sensors
> value in the SoC by the node /sys/class/thermal/
>
> Signed-off-by: Michael Kao
> ---
> drivers/thermal/mtk_thermal.c | 68
On Sat, May 4, 2019 at 2:09 AM Sean Wang wrote:
>
> Hi, Nicolas
>
> On Thu, May 2, 2019 at 5:53 PM Nicolas Boichat wrote:
> >
> > On Thu, May 2, 2019 at 9:48 PM Yingjoe Chen
> > wrote:
> > >
> > > On Mon, 2019-04-29 at 11:25 +0800, Nicolas Boic
pctrl->eint, and struct mtk_pinctrl *pctl has a
different structure definition for v1 and v2 (which is
what paris variant uses).
Signed-off-by: Nicolas Boichat
---
drivers/pinctrl/mediatek/pinctrl-paris.c | 19 +++
drivers/pinctrl/mediatek/pinctrl-paris.h | 2 ++
2 files chan
Setting this up will configure wake from suspend properly,
and wake only for the interrupts that are setup in wake_mask,
not all interrupts.
Signed-off-by: Nicolas Boichat
---
drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/mediatek
, as
recommended by Sean, to keep better separation between eint
and pinctrl-common features.
Nicolas Boichat (2):
pinctrl: mediatek: Add pm_ops to pinctrl-paris
pinctrl: mediatek: mt8183: Add mtk_pinctrl_paris_pm_ops
drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 +
drivers/pinctrl
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
wrote:
>
> This adds support for the MediaTek MT6358 PMIC. This is a
> multifunction device with the following sub modules:
>
> - Regulator
> - RTC
> - Codec
> - Interrupt
>
> It is interfaced to the host controller using SPI interface
> by a
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
wrote:
>
> The MT6358 is a regulator found on boards based on MediaTek MT8183 and
> probably other SoCs. It is a so called pmic and connects as a slave to
> SoC using SPI, wrapped inside the pmic-wrapper.
>
> Signed-off-by: Hsin-Hsiung Wang
> ---
>
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
wrote:
>
> This adds compatible for the MediaTek MT6358 PMIC.
>
> Acked-for-MFD-by: Lee Jones
> Signed-off-by: Hsin-Hsiung Wang
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 11 ---
> 1 file changed, 8 insertions(+), 3
On Tue, May 7, 2019 at 2:11 PM Nicolas Boichat wrote:
>
> On Fri, May 3, 2019 at 6:33 PM Hsin-Hsiung Wang
> wrote:
> >
> > In order to support different types of irq design, we decide to add
> > separate irq drivers for different design and keep mt6397 mfd core
>
On Fri, May 3, 2019 at 6:33 PM Hsin-Hsiung Wang
wrote:
>
> In order to support different types of irq design, we decide to add
> separate irq drivers for different design and keep mt6397 mfd core
> simple and reusable to all generations of PMICs so far.
>
> Signed-off-by: Hsin-Hsiung Wang
> ---
On Thu, May 2, 2019 at 9:48 PM Yingjoe Chen wrote:
>
> On Mon, 2019-04-29 at 11:25 +0800, Nicolas Boichat wrote:
> > pinctrl variants that include pinctrl-mtk-common-v2.h (and not
> > pinctrl-mtk-common.h) also need to use mtk_eint_pm_ops to setup
> > wake mask properly,
-by: Pi-Hsun Shih
The warning from clang is spurious, but in another case, we felt that
the cleanup was worth it, nevertheless
(https://lore.kernel.org/patchwork/patch/1050040/).
Reviewed-By: Nicolas Boichat
> ---
> include/uapi/linux/wireless.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deleti
the need to read the current mask in eint_do_suspend,
and we can remove mtk_eint_chip_read_mask function.
Signed-off-by: Nicolas Boichat
---
drivers/pinctrl/mediatek/mtk-eint.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/mediatek/mtk
This fixes 2 issues when resuming from a wake source, especially if these
wake sources are level-sensitive.
Tested on mt8183 with the series in
https://patchwork.kernel.org/cover/10921121/,
but this should affect all mediatek platforms.
Nicolas Boichat (2):
pinctrl: mediatek: Ignore
quot;)
Signed-off-by: Nicolas Boichat
---
drivers/pinctrl/mediatek/mtk-eint.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/mtk-eint.c
b/drivers/pinctrl/mediatek/mtk-eint.c
index f464f8cd274b75c..737385e86beb807 100644
--- a/drivers/pin
Setting this up will configure wake from suspend properly,
and wake only for the interrupts that are setup in wake_mask,
not all interrupts.
Signed-off-by: Nicolas Boichat
Reviewed-by: Chuanjia Liu
---
drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 +
1 file changed, 1 insertion(+)
diff --git
->eint, and struct mtk_pinctrl *pctl has a
different structure definition for v1 and v2.
Signed-off-by: Nicolas Boichat
Reviewed-by: Chuanjia Liu
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 19 +++
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
2 files changed,
This adds support for wake sources in pinctrl-mtk-common-v2, and
pinctrl-mt8183. Without this patch, all interrupts that are left
enabled on suspend act as wake sources (and wake sources without
interrupt enabled do not).
Nicolas Boichat (2):
pinctrl: mediatek: Add mtk_eint_pm_ops to common-v2
Dear stable maintainers,
I encountered a similar issue on a 4.19.33 kernel (Chromium OS). On my
board, the system would not even be able to boot if KASLR decides to
map the linear region to the top of the virtual address space. This
happens every 253 boots on average (there are 0xfd possible
On Fri, Mar 29, 2019 at 2:46 PM Andrew-sh.Cheng
wrote:
>
> This API will get voltage as input parameter.
> Search all opp items for the item which with max frequency,
> and the voltae is smaller than provided voltage.
>
> Signed-off-by: Andrew-sh.Cheng
> ---
> drivers/opp/core.c | 55
>
On Thu, Mar 28, 2019 at 11:46 PM Andrew-sh.Cheng
wrote:
>
> For new mediatek chip mt8183,
> cci and little cluster share the same buck,
> so need to modify the attribute of regulator from exclusive to optional
>
> Intermediate clock is not always enabled by ccf in different projects,
> so cpufreq
On Mon, Mar 25, 2019 at 5:23 AM Zhiyong Tao wrote:
>
> This patch provides the advanced drive for I2C used pins on MT8183.
> The detail strength specification description of the I2C pin:
> When E1=0/E0=0, the strength is 0.125mA.
> When E1=0/E0=1, the strength is 0.25mA.
> When E1=1/E0=0, the
On Mon, Mar 25, 2019 at 5:41 AM Zhiyong Tao wrote:
>
> The commit adds pintcrl device node for mt8183
Minor nit: This should say pinctrl (in the commit title as well).
>
> Signed-off-by: Zhiyong Tao
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 +-
> 1 file
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Try to stop extending the clk_id or clk_names if there are
> more and more new BASIC clocks. To get its own clocks by the
> basic_clk_name of each power domain.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 27
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Both MT8183 & MT6765 have more control steps of bus protection
> than previous project. And there add more bus protection registers
> reside at infracfg & smi-common. Also add new APIs for multiple
> step bus protection control with more
On Mon, Feb 18, 2019 at 12:55 PM Henry Chen wrote:
>
> Hi Rob,
>
> Sorry for late reply. I missed this mail before.
>
> On Fri, 2019-01-11 at 10:09 -0600, Rob Herring wrote:
> > On Wed, Jan 02, 2019 at 10:09:52PM +0800, Henry Chen wrote:
> > > Document the binding for enabling DVFSRC on MediaTek
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Put bus protection enable and disable control in separate functions.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 48 ++-
> 1 file changed, 34 insertions(+), 14 deletions(-)
>
> diff --git
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Put sram enable and disable control in separate functions.
>
> Signed-off-by: Weiyi Lu
Refactoring looks ok, just a small comment.
Reviewed-by: Nicolas Boichat
> ---
> drivers/soc/mediatek
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Put clock enable and disable control in separate function.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 49 ---
> 1 file changed, 32 insertions(+), 17 deletions(-)
>
> diff --git
On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu wrote:
>
> Use USEC_PER_SEC to indicate the polling timeout directly.
> And add documentation of scp_domain_data.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
On Wed, Mar 13, 2019 at 5:45 PM wrote:
>
> 在 2019-03-07 14:49，Balakrishna Godavarthi 写道：
> > Hi Stepen,
> >
> > On 2019-03-07 04:03, Stephen Boyd wrote:
> >> Quoting Balakrishna Godavarthi (2019-03-06 08:21:13)
> >>> This patch enables enough time to ROME controller to bootup
> >>> after we bring
+Claire Chang who found some issue with this patch.
On Mon, Mar 11, 2019 at 11:48 AM Hsin-Hsiung Wang
wrote:
>
> This adds support for the MediaTek MT6358 PMIC. This is a
> multifunction device with the following sub modules:
>
> - Regulator
> - RTC
> - Codec
> - Interrupt
>
> It is interfaced
On Mon, Mar 11, 2019 at 11:48 AM Hsin-Hsiung Wang
wrote:
>
> In order to support different types of irq design, we decide to add
> separate irq drivers for different design and keep mt6397 mfd core
> simple and reusable to all generations of PMICs so far.
>
> Signed-off-by: Hsin-Hsiung Wang
>
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new
On Mon, Mar 11, 2019 at 1:41 PM Qii Wang wrote:
>
> This patch adds nodes for I2C controller.
>
> Signed-off-by: Qii Wang
> ---
This applies on top of some other uncommitted series, right? This is
fine, but please say which one.
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 190
>
MING support could be split as yet-another-subpatch, but otherwise LGTM.
Reviewed-by: Nicolas Boichat
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 62
> +--
> 1 file changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/buss
i2c controllers also have
> the bit.
>
> Signed-off-by: Qii Wang
I'll let Matthias comment too (I think the comment above is just
enough), but otherwise:
Reviewed-by: Nicolas Boichat
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 25 ++---
> 1 file chang
On Mon, Mar 11, 2019 at 11:48 AM Hsin-Hsiung Wang
wrote:
>
> This adds support for the MediaTek MT6358 PMIC. This is a
> multifunction device with the following sub modules:
>
> - Regulator
> - RTC
> - Codec
> - Interrupt
>
> It is interfaced to the host controller using SPI interface
> by a
On Thu, Mar 7, 2019 at 9:45 AM Long Cheng wrote:
>
> In DMA engine framework, add 8250 uart dma to support MediaTek uart.
> If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve
> the performance, can enable the function.
>
> Signed-off-by: Long Cheng
> ---
>
On Fri, Mar 8, 2019 at 2:42 PM Nicolas Boichat wrote:
>
> )
> On Tue, Mar 5, 2019 at 1:05 PM Weiyi Lu wrote:
> >
> > Add MT8183 clock support, include topckgen, apmixedsys,
> > infracfg, mcucfg and subsystem clocks.
> >
> > Signed-off-by:
ication between these many files, and
wondering if we can make simplify a lot of this code.
Apart from that:
Tested-by: Nicolas Boichat
> ---
> drivers/clk/mediatek/Kconfig | 75 ++
> drivers/clk/mediatek/Makefile | 12 +
> drivers/clk/mediatek/c
; Add configurable pcw_chg_reg to set the pcw change control register
> address or using the default control register CON1 if without
> setting in pll data.
>
> Signed-off-by: Weiyi Lu
Reviewed-and-tested-by: Nicolas Boichat
> ---
> drivers/clk/mediatek/clk-mtk.h | 1 +
&g
Minor nit: frequency (Stephen I guess you could fix that when applying...)
>1.5Ghz, add a variable to indicate platform-dependent.
>
> Signed-off-by: Owen Chen
> Signed-off-by: Weiyi Lu
> Acked-by: Sean Wang
Reviewed-and-tested-by: Nicolas Boichat
> ---
> drivers/clk
: Weiyi Lu
Reviewed-and-tested-by: Nicolas Boichat
> ---
> drivers/clk/mediatek/clk-gate.c | 5 +++--
> drivers/clk/mediatek/clk-gate.h | 3 ++-
> drivers/clk/mediatek/clk-mtk.c | 3 ++-
> drivers/clk/mediatek/clk-mtk.h | 1 +
> 4 files changed, 8 insertions(+), 4 deletions(-)
&g
gt; The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
>
> Signed-off-by: Owen Chen
> Signed-off-by: Weiyi Lu
Reviewed-and-tested-by: Nicolas Boichat
> ---
> driver
This is a v3, I think, please make sure the update the email title,
and add a changelog below ---.
On Sun, Mar 3, 2019 at 9:54 AM Zhiyong Tao wrote:
>
> This patch provides the advanced drive for I2C used pins on MT8183.
> The detail strength specification description of the I2C pin is as
On Tue, Feb 26, 2019 at 9:11 PM Qii Wang wrote:
>
> Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
> MT8183 has different register offsets. Ltiming_reg is added to
> adjust low width of SCL. Arb clock and dma_sync are needed.
>
> Signed-off-by: Qii Wang
> ---
>
One thing I missed from Matthias' comment on v4:
https://patchwork.kernel.org/patch/10822083/
On Wed, Mar 6, 2019 at 6:44 PM Nicolas Boichat wrote:
>
> On Tue, Feb 26, 2019 at 9:11 PM Qii Wang wrote:
> >
> > When two i2c controllers are internally connected to the same
>
On Tue, Feb 26, 2019 at 9:11 PM Qii Wang wrote:
>
> When i2c and apdma use different source clocks, we should enable
> synchronization between them.
>
> Signed-off-by: Qii Wang
Reviewed-by: Nicolas Boichat
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 11 +++
On Tue, Feb 26, 2019 at 9:11 PM Qii Wang wrote:
>
> When two i2c controllers are internally connected to the same
> GPIO pins, the arb clock is needed to ensure that the waveforms
> do not interfere with each other.
>
> Signed-off-by: Qii Wang
Reviewed-by: Nicolas Boichat
&g
On Wed, Feb 13, 2019 at 4:56 PM Nicolas Boichat wrote:
>
> On Tue, Jan 22, 2019 at 4:46 PM Prateek Patel wrote:
> >
> >
> > On 11/10/2018 2:58 AM, Rob Herring wrote:
> > > On Fri, Nov 9, 2018 at 1:09 AM Prateek Patel wrote:
> > >> From: Sri Kr
On Thu, Feb 14, 2019 at 1:12 AM Vlastimil Babka wrote:
>
> On 1/22/19 11:51 PM, Nicolas Boichat wrote:
> > Hi Andrew,
> >
> > On Fri, Jan 11, 2019 at 6:21 PM Joerg Roedel wrote:
> >>
> >> On Wed, Jan 02, 2019 at 01:51:45PM +0800, Nicolas Boichat wrote:
&
Joerg: Just to make sure, is this patch in your queue? Thanks.
On Thu, Jan 31, 2019 at 2:21 AM Will Deacon wrote:
>
> On Mon, Jan 28, 2019 at 05:43:01PM +0800, Nicolas Boichat wrote:
> > L1 tables are allocated with __get_dma_pages, and therefore already
> > ignored by kmemlea
On Fri, Feb 15, 2019 at 2:07 PM Erin Lo wrote:
> Subject: [PATCH v7 5/6] arm64: dts: mt8183: add pintcrl file
minor spelling mistake in the commit title: pinctrl
>
> This patch adds pinctrl file for mt8183.
>
> Signed-off-by: Zhiyong Tao
> Signed-off-by: Erin Lo
> ---
On Sun, Feb 17, 2019 at 10:48 PM Jitao Shi wrote:
>
> On Thu, 2019-02-14 at 13:54 +0800, Nicolas Boichat wrote:
> > On Thu, Feb 14, 2019 at 12:43 PM Jitao Shi wrote:
> > >
> > > MT8183 dsi has two changes with mt8173.
> > > 1. Add the register double buf
Just some comments on the error path, I'm not sure about the change itself.
On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
>
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more
On Thu, Feb 14, 2019 at 12:43 PM Jitao Shi wrote:
>
> MT8183 dsi has two changes with mt8173.
> 1. Add the register double buffer control, but we no need it, So make
>it default off.
Can you describe a little bit more what this is about? That's shadow
registers, right?
> 2. Add picture size
On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
>
> Config the different CMDQ reg address in driver data.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 39 --
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git
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