Re: [PATCH v2 2/6] perf report: Caculate and return the branch counting in callchain

On 20 October 2016 at 11:48, Andi Kleen <a...@linux.intel.com> wrote: > On Thu, Oct 20, 2016 at 11:41:11AM -0500, Nilay Vaish wrote: >> On 19 October 2016 at 17:01, Jin Yao <yao@linux.intel.com> wrote: >> > diff --git a/tools/perf/util/callchain.h b/tools/pe

Re: [PATCH v2 2/6] perf report: Caculate and return the branch counting in callchain

On 20 October 2016 at 11:48, Andi Kleen wrote: > On Thu, Oct 20, 2016 at 11:41:11AM -0500, Nilay Vaish wrote: >> On 19 October 2016 at 17:01, Jin Yao wrote: >> > diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h >> > index 40ecf25..4f6bf6c 100644

Re: [PATCH v2 2/6] perf report: Caculate and return the branch counting in callchain

On 19 October 2016 at 17:01, Jin Yao wrote: > diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h > index 40ecf25..4f6bf6c 100644 > --- a/tools/perf/util/callchain.h > +++ b/tools/perf/util/callchain.h > @@ -115,6 +115,10 @@ struct callchain_list { >

Re: [PATCH v2 2/6] perf report: Caculate and return the branch counting in callchain

On 19 October 2016 at 17:01, Jin Yao wrote: > diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h > index 40ecf25..4f6bf6c 100644 > --- a/tools/perf/util/callchain.h > +++ b/tools/perf/util/callchain.h > @@ -115,6 +115,10 @@ struct callchain_list { > bool

Re: [PATCH 1/9] perf/jit: improve error messages from JVMTI

On 13 October 2016 at 05:59, Stephane Eranian wrote: > diff --git a/tools/perf/jvmti/libjvmti.c b/tools/perf/jvmti/libjvmti.c > index ac12e4b91a92..2d9bc04b79a8 100644 > --- a/tools/perf/jvmti/libjvmti.c > +++ b/tools/perf/jvmti/libjvmti.c > @@ -12,6 +12,17 @@ > static int

Re: [PATCH 1/9] perf/jit: improve error messages from JVMTI

On 13 October 2016 at 05:59, Stephane Eranian wrote: > diff --git a/tools/perf/jvmti/libjvmti.c b/tools/perf/jvmti/libjvmti.c > index ac12e4b91a92..2d9bc04b79a8 100644 > --- a/tools/perf/jvmti/libjvmti.c > +++ b/tools/perf/jvmti/libjvmti.c > @@ -12,6 +12,17 @@ > static int has_line_numbers; >

Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface

On 10 October 2016 at 12:19, Luck, Tony <tony.l...@intel.com> wrote: > On Sat, Oct 08, 2016 at 01:33:06PM -0700, Fenghua Yu wrote: >> On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote: >> > On 7 October 2016 at 21:45, Fenghua Yu <fenghua...@intel.com>

Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface

On 10 October 2016 at 12:19, Luck, Tony wrote: > On Sat, Oct 08, 2016 at 01:33:06PM -0700, Fenghua Yu wrote: >> On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote: >> > On 7 October 2016 at 21:45, Fenghua Yu wrote: >> > > From: Fenghua Yu >> &

Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

On 8 October 2016 at 14:52, Borislav Petkov wrote: > On Sat, Oct 08, 2016 at 01:54:54PM -0700, Fenghua Yu wrote: >> > I think these #defines are specific to Intel. I would prefer if we >> > have _INTEL_ somewhere in them. > > We don't generally add vendor names to those defines.

Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

On 8 October 2016 at 14:52, Borislav Petkov wrote: > On Sat, Oct 08, 2016 at 01:54:54PM -0700, Fenghua Yu wrote: >> > I think these #defines are specific to Intel. I would prefer if we >> > have _INTEL_ somewhere in them. > > We don't generally add vendor names to those defines. Even more so if

Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id

On 10 October 2016 at 11:45, Luck, Tony <tony.l...@intel.com> wrote: > On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote: >> On 7 October 2016 at 21:45, Fenghua Yu <fenghua...@intel.com> wrote: >> > From: Fenghua Yu <fenghua...@intel.com> > >>

Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id

On 10 October 2016 at 11:45, Luck, Tony wrote: > On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote: >> On 7 October 2016 at 21:45, Fenghua Yu wrote: >> > From: Fenghua Yu > >> > + caches typically exist per core, but there may not be a >

Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > diff --git a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c > b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c > index 28df92e..efcbfe7 100644 > --- a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c >

Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > diff --git a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c > b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c > index 28df92e..efcbfe7 100644 > --- a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c > +++ b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c

Re: [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > diff --git a/arch/x86/include/asm/intel_rdt.h > b/arch/x86/include/asm/intel_rdt.h > index bad8dc7..f63815c 100644 > --- a/arch/x86/include/asm/intel_rdt.h > +++

Re: [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > diff --git a/arch/x86/include/asm/intel_rdt.h > b/arch/x86/include/asm/intel_rdt.h > index bad8dc7..f63815c 100644 > --- a/arch/x86/include/asm/intel_rdt.h > +++ b/arch/x86/include/asm/intel_rdt.h > @@ -2,6 +2,23 @@ > #define

Re: [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Tony Luck > > diff --git a/arch/x86/include/asm/intel_rdt.h > b/arch/x86/include/asm/intel_rdt.h > index 251ac2a..bad8dc7 100644 > --- a/arch/x86/include/asm/intel_rdt.h > +++

Re: [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Tony Luck > > diff --git a/arch/x86/include/asm/intel_rdt.h > b/arch/x86/include/asm/intel_rdt.h > index 251ac2a..bad8dc7 100644 > --- a/arch/x86/include/asm/intel_rdt.h > +++ b/arch/x86/include/asm/intel_rdt.h > @@ -40,6 +40,39 @@ struct

Re: [PATCH v3 02/18] cacheinfo: Introduce cache id

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index e9fd32e..2a21c15 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -233,6 +233,7

Re: [PATCH v3 02/18] cacheinfo: Introduce cache id

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index e9fd32e..2a21c15 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -233,6 +233,7 @@ static ssize_t file_name##_show(struct

Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > +L3 details (code and data prioritization disabled) > +-- > +With CDP disabled the L3 schemata format is: > + > + L3:=;=;... > +

Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > +L3 details (code and data prioritization disabled) > +-- > +With CDP disabled the L3 schemata format is: > + > + L3:=;=;... > + > +L3 details (CDP enabled via mount option

Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > Check CPUID leaves for all the Resource Director Technology (RDT) > Cache Allocation Technology (CAT) bits. > > Prescence of allocation features: Presence > diff --git

Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > Check CPUID leaves for all the Resource Director Technology (RDT) > Cache Allocation Technology (CAT) bits. > > Prescence of allocation features: Presence > diff --git a/arch/x86/include/asm/cpufeatures.h >

Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id. > > Signed-off-by: Fenghua Yu > Signed-off-by: Tony Luck > ---

Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id

On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id. > > Signed-off-by: Fenghua Yu > Signed-off-by: Tony Luck > --- > Documentation/ABI/testing/sysfs-devices-system-cpu | 16 > 1 file

Re: [PATCH v5 1/9] sched: Extend scheduler's asym packing

On 1 October 2016 at 06:45, Srinivas Pandruvada wrote: > diff --git a/kernel/sched/core.c b/kernel/sched/core.c > index e86c4a5..08135ca 100644 > --- a/kernel/sched/core.c > +++ b/kernel/sched/core.c > @@ -6237,7 +6237,25 @@ static void

Re: [PATCH v5 1/9] sched: Extend scheduler's asym packing

On 1 October 2016 at 06:45, Srinivas Pandruvada wrote: > diff --git a/kernel/sched/core.c b/kernel/sched/core.c > index e86c4a5..08135ca 100644 > --- a/kernel/sched/core.c > +++ b/kernel/sched/core.c > @@ -6237,7 +6237,25 @@ static void init_sched_groups_capacity(int cpu, struct > sched_domain

Re: [PATCH 05/61] perf tools: Introduce c2c_decode_stats function

On 19 September 2016 at 08:09, Jiri Olsa wrote: > diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h > index 7f69bf9d789d..27c6bb5abafb 100644 > --- a/tools/perf/util/mem-events.h > +++ b/tools/perf/util/mem-events.h > @@ -2,6 +2,10 @@ > #define

Re: [PATCH 05/61] perf tools: Introduce c2c_decode_stats function

On 19 September 2016 at 08:09, Jiri Olsa wrote: > diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h > index 7f69bf9d789d..27c6bb5abafb 100644 > --- a/tools/perf/util/mem-events.h > +++ b/tools/perf/util/mem-events.h > @@ -2,6 +2,10 @@ > #define __PERF_MEM_EVENTS_H > >

Re: [PATCH v3 03/15] lockdep: Refactor lookup_chain_cache()

On 18 September 2016 at 22:05, Byungchul Park <byungchul.p...@lge.com> wrote: > On Thu, Sep 15, 2016 at 10:33:46AM -0500, Nilay Vaish wrote: >> On 13 September 2016 at 04:45, Byungchul Park <byungchul.p...@lge.com> wrote: >> > @@ -2215,6 +2178,75 @@ ca

Re: [PATCH v3 03/15] lockdep: Refactor lookup_chain_cache()

On 18 September 2016 at 22:05, Byungchul Park wrote: > On Thu, Sep 15, 2016 at 10:33:46AM -0500, Nilay Vaish wrote: >> On 13 September 2016 at 04:45, Byungchul Park wrote: >> > @@ -2215,6 +2178,75 @@ cache_hit: >> > return 1; >> > } >> >

Re: [PATCH v3 15/15] lockdep: Crossrelease feature documentation

On 13 September 2016 at 04:45, Byungchul Park wrote: > This document describes the concept of crossrelease feature, which > generalizes what causes a deadlock and how can detect a deadlock. > > Signed-off-by: Byungchul Park > --- >

Re: [PATCH v3 15/15] lockdep: Crossrelease feature documentation

On 13 September 2016 at 04:45, Byungchul Park wrote: > This document describes the concept of crossrelease feature, which > generalizes what causes a deadlock and how can detect a deadlock. > > Signed-off-by: Byungchul Park > --- > Documentation/locking/crossrelease.txt | 785 >

Re: [PATCH v3 15/15] lockdep: Crossrelease feature documentation

On 13 September 2016 at 04:45, Byungchul Park wrote: > This document describes the concept of crossrelease feature, which > generalizes what causes a deadlock and how can detect a deadlock. > > Signed-off-by: Byungchul Park > --- >

Re: [PATCH v3 15/15] lockdep: Crossrelease feature documentation

On 13 September 2016 at 04:45, Byungchul Park wrote: > This document describes the concept of crossrelease feature, which > generalizes what causes a deadlock and how can detect a deadlock. > > Signed-off-by: Byungchul Park > --- > Documentation/locking/crossrelease.txt | 785 >

Re: [PATCH v3 03/15] lockdep: Refactor lookup_chain_cache()

On 13 September 2016 at 04:45, Byungchul Park wrote: > @@ -2215,6 +2178,75 @@ cache_hit: > return 1; > } > > +/* > + * Look up a dependency chain. > + */ > +static inline struct lock_chain *lookup_chain_cache(u64 chain_key) > +{ > + struct hlist_head

Re: [PATCH v3 03/15] lockdep: Refactor lookup_chain_cache()

On 13 September 2016 at 04:45, Byungchul Park wrote: > @@ -2215,6 +2178,75 @@ cache_hit: > return 1; > } > > +/* > + * Look up a dependency chain. > + */ > +static inline struct lock_chain *lookup_chain_cache(u64 chain_key) > +{ > + struct hlist_head *hash_head =

Re: [PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache Allocation

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index 9f30492..4537658 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -141,6 +145,80 @@ static

Re: [PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache Allocation

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index 9f30492..4537658 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -141,6 +145,80 @@ static inline bool

Re: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index 9cf3a7d..9f30492 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -21,6 +21,8 @@ > */ >

Re: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index 9cf3a7d..9f30492 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -21,6 +21,8 @@ > */ > #include > #include >

Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index b25940a..9cf3a7d 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -31,8 +31,22 @@ static struct

Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index b25940a..9cf3a7d 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -31,8 +31,22 @@ static struct clos_cbm_table

Re: [PATCH v2 08/33] x86/intel_rdt: Add Class of service management

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index fcd0642..b25940a 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -21,17 +21,94 @@ > */ >

Re: [PATCH v2 08/33] x86/intel_rdt: Add Class of service management

On 8 September 2016 at 04:57, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c > index fcd0642..b25940a 100644 > --- a/arch/x86/kernel/cpu/intel_rdt.c > +++ b/arch/x86/kernel/cpu/intel_rdt.c > @@ -21,17 +21,94 @@ > */ > #include > #include >

Re: [PATCH v2 02/33] Documentation, ABI: Add a document entry for cache id

On 8 September 2016 at 14:33, Thomas Gleixner wrote: > On Thu, 8 Sep 2016, Fenghua Yu wrote: >> +What:/sys/devices/system/cpu/cpu*/cache/index*/id >> +Date:July 2016 >> +Contact: Linux kernel mailing list >>

Re: [PATCH v2 02/33] Documentation, ABI: Add a document entry for cache id

On 8 September 2016 at 14:33, Thomas Gleixner wrote: > On Thu, 8 Sep 2016, Fenghua Yu wrote: >> +What:/sys/devices/system/cpu/cpu*/cache/index*/id >> +Date:July 2016 >> +Contact: Linux kernel mailing list >> +Description: Cache id >> + >> + The id

Re: [PATCH v2 01/33] cacheinfo: Introduce cache id

On 8 September 2016 at 04:56, Fenghua Yu wrote: > diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h > index 2189935..cf6984d 100644 > --- a/include/linux/cacheinfo.h > +++ b/include/linux/cacheinfo.h > @@ -18,6 +18,7 @@ enum cache_type { > > /** > *

Re: [PATCH v2 01/33] cacheinfo: Introduce cache id

On 8 September 2016 at 04:56, Fenghua Yu wrote: > diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h > index 2189935..cf6984d 100644 > --- a/include/linux/cacheinfo.h > +++ b/include/linux/cacheinfo.h > @@ -18,6 +18,7 @@ enum cache_type { > > /** > * struct cacheinfo -

Re: [PATCH v2 1/1] x86, relocs: add function attributes to die()

@ -14,4 +14,7 @@ > #define ELF_ST_BIND(o) ELF64_ST_BIND(o) > #define ELF_ST_VISIBILITY(o)ELF64_ST_VISIBILITY(o) > > +/* printf format for Elf64_Off */ > +#define PRIuELF PRIu64 > + > #include "relocs.c" > diff --git a/arch/x86/tools/relocs_common.c b/arch/x86/tools/relocs_common.c > index acab636bcb34..30adb44eff79 100644 > --- a/arch/x86/tools/relocs_common.c > +++ b/arch/x86/tools/relocs_common.c > @@ -1,6 +1,6 @@ > #include "relocs.h" > > -void die(char *fmt, ...) > +void die(const char *fmt, ...) > { > va_list ap; > va_start(ap, fmt); > -- > 2.9.3 > I have to admit that this is the first time I am looking at these format specifier macros from inttypes.h. I looked at that file. Your usage seems correct to me and should achieve the desired outcome. Reviewed-by: Nilay Vaish <nilayva...@gmail.com>

Re: [PATCH v2 1/1] x86, relocs: add function attributes to die()

nclude "relocs.c" > diff --git a/arch/x86/tools/relocs_64.c b/arch/x86/tools/relocs_64.c > index 56b61b743c4c..2cf4de5c9d99 100644 > --- a/arch/x86/tools/relocs_64.c > +++ b/arch/x86/tools/relocs_64.c > @@ -14,4 +14,7 @@ > #define ELF_ST_BIND(o) ELF64_ST_BIND(o)

Re: [PATCH 0/3] perf report: Recognize hugetlb mapping as anon mapping

lib/api/fs/fs.h | 1 + > tools/perf/util/event.c | 7 +++ > tools/perf/util/map.c | 8 +--- > 4 files changed, 28 insertions(+), 3 deletions(-) > > Signed-off-by: Wang Nan <wangn...@huawei.com> > Cc: Hou Pengyang <houpengy...@huawei.com> > Cc: He

Re: [PATCH 0/3] perf report: Recognize hugetlb mapping as anon mapping

> tools/perf/util/event.c | 7 +++ > tools/perf/util/map.c | 8 +--- > 4 files changed, 28 insertions(+), 3 deletions(-) > > Signed-off-by: Wang Nan > Cc: Hou Pengyang > Cc: He Kuang > Cc: Arnaldo Carvalho de Melo Reviewed-by: Nilay Vaish

Re: [PATCH 1/3] perf tools: Recognize hugetlb mapping as anon mapping

On 2 September 2016 at 08:59, Wang Nan wrote: > Hugetlbfs mapping should be recognized as anon mapping so user has > a chance to create /tmp/perf-.map file for symbol resolving. This > patch utilizes MAP_HUGETLB to identify hugetlb mapping. > > After this patch, if perf is

Re: [PATCH 1/3] perf tools: Recognize hugetlb mapping as anon mapping

On 2 September 2016 at 08:59, Wang Nan wrote: > Hugetlbfs mapping should be recognized as anon mapping so user has > a chance to create /tmp/perf-.map file for symbol resolving. This > patch utilizes MAP_HUGETLB to identify hugetlb mapping. > > After this patch, if perf is started before the

Re: [PATCH 1/1] x86, relocs: add function attributes to die()

On 3 September 2016 at 09:50, Nicolas Iooss wrote: > > arch/x86/tools/relocs.c:460:5: error: format specifies type 'int' > but the argument has type 'Elf64_Xword' (aka 'unsigned long') > [-Werror,-Wformat] >

Re: [PATCH 1/1] x86, relocs: add function attributes to die()

On 3 September 2016 at 09:50, Nicolas Iooss wrote: > > arch/x86/tools/relocs.c:460:5: error: format specifies type 'int' > but the argument has type 'Elf64_Xword' (aka 'unsigned long') > [-Werror,-Wformat] > sec->shdr.sh_size); >

Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to include perf_arch_regs

On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: > diff --git a/kernel/events/core.c b/kernel/events/core.c > index 274288819829..e16bf4d057d1 100644 > --- a/kernel/events/core.c > +++ b/kernel/events/core.c > @@ -5371,16 +5371,24 @@ u64 __attribute__((weak))

Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to include perf_arch_regs

On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: > diff --git a/kernel/events/core.c b/kernel/events/core.c > index 274288819829..e16bf4d057d1 100644 > --- a/kernel/events/core.c > +++ b/kernel/events/core.c > @@ -5371,16 +5371,24 @@ u64 __attribute__((weak)) perf_arch_reg_value(struct >

Re: [PATCH 00/13] Add support for perf_arch_regs

On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: > Patchset to extend PERF_SAMPLE_REGS_INTR to include > platform specific PMU registers. > > Patchset applies cleanly on tip:perf/core branch > > It's a perennial request from hardware folks to be able to > see the

Re: [PATCH 00/13] Add support for perf_arch_regs

On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: > Patchset to extend PERF_SAMPLE_REGS_INTR to include > platform specific PMU registers. > > Patchset applies cleanly on tip:perf/core branch > > It's a perennial request from hardware folks to be able to > see the raw values of the pmu

Re: [PATCH v2 1/4] tracing: Added hardware latency tracer

On 10 August 2016 at 08:53, Steven Rostedt wrote: > diff --git a/kernel/trace/trace_hwlat.c b/kernel/trace/trace_hwlat.c > new file mode 100644 > index ..08dfabe4e862 > --- /dev/null > +++ b/kernel/trace/trace_hwlat.c > @@ -0,0 +1,527 @@ > +/* > + *

Re: [PATCH v2 1/4] tracing: Added hardware latency tracer

On 10 August 2016 at 08:53, Steven Rostedt wrote: > diff --git a/kernel/trace/trace_hwlat.c b/kernel/trace/trace_hwlat.c > new file mode 100644 > index ..08dfabe4e862 > --- /dev/null > +++ b/kernel/trace/trace_hwlat.c > @@ -0,0 +1,527 @@ > +/* > + * trace_hwlatdetect.c - A simple

Re: [PATCH v3 14/51] x86/asm/head: put real return address on idle task stack

On 12 August 2016 at 09:28, Josh Poimboeuf wrote: > The frame at the end of each idle task stack has a zeroed return > address. This is inconsistent with real task stacks, which have a real > return address at that spot. This inconsistency can be confusing for > stack

Re: [PATCH v3 14/51] x86/asm/head: put real return address on idle task stack

On 12 August 2016 at 09:28, Josh Poimboeuf wrote: > The frame at the end of each idle task stack has a zeroed return > address. This is inconsistent with real task stacks, which have a real > return address at that spot. This inconsistency can be confusing for > stack unwinders. > > Make it a

Re: [PATCH 3/3] perf/x86/intel/uncore: Add Skylake server uncore support

On 15 August 2016 at 09:12, Liang, Kan wrote: > > >> > diff --git a/arch/x86/events/intel/uncore_snbep.c >> > b/arch/x86/events/intel/uncore_snbep.c >> > index 3719af5..55a081e 100644 >> > --- a/arch/x86/events/intel/uncore_snbep.c >> > +++

Re: [PATCH 3/3] perf/x86/intel/uncore: Add Skylake server uncore support

On 15 August 2016 at 09:12, Liang, Kan wrote: > > >> > diff --git a/arch/x86/events/intel/uncore_snbep.c >> > b/arch/x86/events/intel/uncore_snbep.c >> > index 3719af5..55a081e 100644 >> > --- a/arch/x86/events/intel/uncore_snbep.c >> > +++ b/arch/x86/events/intel/uncore_snbep.c >> > + >> >

Re: [PATCH 3/3] perf/x86/intel/uncore: Add Skylake server uncore support

On 12 August 2016 at 16:30, Kan Liang wrote: > From: Kan Liang > > This patch implements the uncore monitoring driver for Skylake server. > The uncore subsystem in Skylake server is similar to previous > server. There are some differences in config

Re: [PATCH 3/3] perf/x86/intel/uncore: Add Skylake server uncore support

On 12 August 2016 at 16:30, Kan Liang wrote: > From: Kan Liang > > This patch implements the uncore monitoring driver for Skylake server. > The uncore subsystem in Skylake server is similar to previous > server. There are some differences in config register encoding and pci > device IDs.

Re: [PATCH 1/3] perf/x86/intel/uncore: remove hard code for Node ID mapping location

On 12 August 2016 at 16:30, Kan Liang wrote: > From: Kan Liang > > The method to build PCI bus to socket mapping is similar among > platforms. However, the PCI location where store Node ID mapping could I think we should replace "where store" with

Re: [PATCH 1/3] perf/x86/intel/uncore: remove hard code for Node ID mapping location

On 12 August 2016 at 16:30, Kan Liang wrote: > From: Kan Liang > > The method to build PCI bus to socket mapping is similar among > platforms. However, the PCI location where store Node ID mapping could I think we should replace "where store" with "which store". > vary for different platforms.

Re: [PATCH v3 04/51] x86/asm/head: use a common function for starting CPUs

On 12 August 2016 at 09:28, Josh Poimboeuf wrote: > There are two different pieces of code for starting a CPU: start_cpu0() > and the end of secondary_startup_64(). They're identical except for the > stack setup. Combine the common parts into a shared start_cpu() >

Re: [PATCH v3 04/51] x86/asm/head: use a common function for starting CPUs

On 12 August 2016 at 09:28, Josh Poimboeuf wrote: > There are two different pieces of code for starting a CPU: start_cpu0() > and the end of secondary_startup_64(). They're identical except for the > stack setup. Combine the common parts into a shared start_cpu() > function. > > Signed-off-by:

Re: [PATCH v2 0/4] remove unnecessary IPI reading uncore events

/intel/rapl.c | 2 ++ > arch/x86/events/intel/uncore.c | 2 ++ > arch/x86/events/intel/uncore_snb.c | 2 ++ > include/linux/perf_event.h | 21 +++ > kernel/events/core.c | 52 > +++++- > 5 files changed, 57 insertions(+), 22 deletions(-) > > -- > 2.8.0.rc3.226.g39d4020 > Reviewed-by: Nilay Vaish <nilayva...@gmail.com>

Re: [PATCH v2 0/4] remove unnecessary IPI reading uncore events

++ > arch/x86/events/intel/uncore.c | 2 ++ > arch/x86/events/intel/uncore_snb.c | 2 ++ > include/linux/perf_event.h | 21 +++ > kernel/events/core.c | 52 > +----- > 5 files changed, 57 insertions(+), 22 deletions(-) > > -- > 2.8.0.rc3.226.g39d4020 > Reviewed-by: Nilay Vaish

Re: [PATCH 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 9 August 2016 at 17:28, David Carrillo-Cisneros wrote: > Introduce the flag PMU_EV_CAP_READ_ACTIVE_PKG, useful for uncore events, > that allows a PMU to signal the generic perf code that an event is readable > in the current CPU if the event is active in a CPU in the same

Re: [PATCH 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 9 August 2016 at 17:28, David Carrillo-Cisneros wrote: > Introduce the flag PMU_EV_CAP_READ_ACTIVE_PKG, useful for uncore events, > that allows a PMU to signal the generic perf code that an event is readable > in the current CPU if the event is active in a CPU in the same package as > the

Re: [PATCH v2 30/44] x86/unwind: add new unwind interface and implementations

On 4 August 2016 at 17:22, Josh Poimboeuf wrote: > diff --git a/arch/x86/kernel/unwind_frame.c b/arch/x86/kernel/unwind_frame.c > new file mode 100644 > index 000..f28f1b5 > --- /dev/null > +++ b/arch/x86/kernel/unwind_frame.c > @@ -0,0 +1,84 @@ > +#include > +#include

Re: [PATCH v2 30/44] x86/unwind: add new unwind interface and implementations

On 4 August 2016 at 17:22, Josh Poimboeuf wrote: > diff --git a/arch/x86/kernel/unwind_frame.c b/arch/x86/kernel/unwind_frame.c > new file mode 100644 > index 000..f28f1b5 > --- /dev/null > +++ b/arch/x86/kernel/unwind_frame.c > @@ -0,0 +1,84 @@ > +#include > +#include > +#include >

Re: [PATCH v2 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 7 August 2016 at 15:10, David Carrillo-Cisneros wrote: > Hi Nilay, > >>> static int perf_event_read(struct perf_event *event, bool group) >>> { >>> - int ret = 0; >>> + int ret = 0, cpu_to_read; >>> >>> - /* >>> -* If event is enabled and

Re: [PATCH v2 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 7 August 2016 at 15:10, David Carrillo-Cisneros wrote: > Hi Nilay, > >>> static int perf_event_read(struct perf_event *event, bool group) >>> { >>> - int ret = 0; >>> + int ret = 0, cpu_to_read; >>> >>> - /* >>> -* If event is enabled and currently active on a CPU,

Re: [PATCH v2 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 08/06/16 22:12, David Carrillo-Cisneros wrote: diff --git a/kernel/events/core.c b/kernel/events/core.c index 34049cc..77f1bd3 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -,6 +,26 @@ struct perf_read_data { int ret; }; +static int find_cpu_to_read(struct

Re: [PATCH v2 3/4] perf/core: introduce PMU_EV_CAP_READ_ACTIVE_PKG

On 08/06/16 22:12, David Carrillo-Cisneros wrote: diff --git a/kernel/events/core.c b/kernel/events/core.c index 34049cc..77f1bd3 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -,6 +,26 @@ struct perf_read_data { int ret; }; +static int find_cpu_to_read(struct

Re: [PATCH v2 04/44] x86/asm/head: use a common function for starting CPUs

On 4 August 2016 at 17:22, Josh Poimboeuf wrote: > There are two different pieces of code for starting a CPU: start_cpu0() > and the end of secondary_startup_64(). They're identical except for the > stack setup. Combine the common parts into a shared start_cpu() > function.

Re: [PATCH v2 04/44] x86/asm/head: use a common function for starting CPUs

On 4 August 2016 at 17:22, Josh Poimboeuf wrote: > There are two different pieces of code for starting a CPU: start_cpu0() > and the end of secondary_startup_64(). They're identical except for the > stack setup. Combine the common parts into a shared start_cpu() > function. > > Signed-off-by:

Re: [PATCH v2 03/44] x86/asm/head: rename 'stack_start' -> 'initial_stack'

On 4 August 2016 at 17:21, Josh Poimboeuf wrote: > The 'stack_start' variable is similar in usage to 'initial_code' and > 'initial_gs': they're all stored in head_64.S and they're all updated by > SMP and ACPI suspend before starting a CPU. > > Rename it to 'initial_stack' to

Re: [PATCH v2 03/44] x86/asm/head: rename 'stack_start' -> 'initial_stack'

On 4 August 2016 at 17:21, Josh Poimboeuf wrote: > The 'stack_start' variable is similar in usage to 'initial_code' and > 'initial_gs': they're all stored in head_64.S and they're all updated by > SMP and ACPI suspend before starting a CPU. > > Rename it to 'initial_stack' to be consistent with

Re: [PATCH 21/32] x86/intel_rdt.h: Header for inter_rdt.c

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > The header mainly provides functions to call from the user interface > file intel_rdt_rdtgroup.c. > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck

Re: [PATCH 21/32] x86/intel_rdt.h: Header for inter_rdt.c

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > The header mainly provides functions to call from the user interface > file intel_rdt_rdtgroup.c. > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck > --- > arch/x86/include/asm/intel_rdt.h | 87 >

Re: [PATCH 20/32] magic number for rscctrl file system

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck > --- > include/uapi/linux/magic.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff

Re: [PATCH 20/32] magic number for rscctrl file system

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck > --- > include/uapi/linux/magic.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/uapi/linux/magic.h b/include/uapi/linux/magic.h > index 546b388..655036a

Re: [PATCH 19/32] sched.h: Add rg_list and rdtgroup in task_struct

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > rg_list is linked list to connect to other tasks in a rdtgroup. > > The point of rdtgroup allows the task to access its own rdtgroup directly. > > Signed-off-by: Fenghua Yu

Re: [PATCH 19/32] sched.h: Add rg_list and rdtgroup in task_struct

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > rg_list is linked list to connect to other tasks in a rdtgroup. > > The point of rdtgroup allows the task to access its own rdtgroup directly. > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck > --- >

Re: [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Enable cache id in x86. Cache id comes from APIC ID and CPUID4. > I think one of these patches on cache ids should refer to some documentation from Intel on this subject, either in the

Re: [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Enable cache id in x86. Cache id comes from APIC ID and CPUID4. > I think one of these patches on cache ids should refer to some documentation from Intel on this subject, either in the commit message or in the comments in some

Re: [PATCH 15/32] cacheinfo: Introduce cache id

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Each cache is described by cacheinfo and is unique in the same index > across the platform. But there is no id for a cache. We introduce cache > ID to identify a cache. > > Intel Cache

Re: [PATCH 15/32] cacheinfo: Introduce cache id

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Each cache is described by cacheinfo and is unique in the same index > across the platform. But there is no id for a cache. We introduce cache > ID to identify a cache. > > Intel Cache Allocation Technology (CAT) allows some

Re: [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Define two new cpuid leaves for CAT and CDP. The leaves are used in > x86_capability to avoid hard coded index. > > Clean comments for RDT, CAT_L3, and CDP_L3 cpufeatures. > >

Re: [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code

On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Define two new cpuid leaves for CAT and CDP. The leaves are used in > x86_capability to avoid hard coded index. > > Clean comments for RDT, CAT_L3, and CDP_L3 cpufeatures. > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck

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