On Mon, 19 Oct 2020 13:43:27 PDT (-0700), ati...@atishpatra.org wrote:
On Mon, Oct 19, 2020 at 12:08 PM Palmer Dabbelt wrote:
The following changes since commit d012a7190fc1fd72ed48911e77ca97ba4521bccd:
Linux 5.9-rc2 (2020-08-23 14:08:43 -0700)
are available in the Git repository at
on functions
RISC-V: Add PE/COFF header for EFI stub
RISC-V: Add EFI stub support.
RISC-V: Add EFI runtime services
RISC-V: Add page table dump support for uefi
Palmer Dabbelt (1):
Merge tag 'efi-riscv-shared-for-v5.10' of
ssh://gitolite.kernel.org/.../efi/
From: Palmer Dabbelt
I was going to copy this but I didn't want to chase around the build
system stuff so I did it a different way.
Signed-off-by: Palmer Dabbelt
---
arch/nds32/kernel/vdso/gen_vdso_offsets.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
From: Palmer Dabbelt
I was going to copy this but I didn't want to chase around the build
system stuff so I did it a different way.
Signed-off-by: Palmer Dabbelt
---
arch/arm64/kernel/vdso/gen_vdso_offsets.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
On Fri, 09 Oct 2020 14:16:00 PDT (-0700), ati...@atishpatra.org wrote:
On Thu, Oct 8, 2020 at 6:53 PM Guo Ren wrote:
On Thu, Oct 8, 2020 at 11:54 AM Palmer Dabbelt wrote:
>
> On Wed, 07 Oct 2020 08:08:33 PDT (-0700), guo...@kernel.org wrote:
> > From: Guo Ren
> >
The following changes since commit 549738f15da0e5a00275977623be199fbbf7df50:
Linux 5.9-rc8 (2020-10-04 16:04:34 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.9
for you to fetch changes up to 84814460eef9a
s_kernel_data to fixup it.
Link:
https://lore.kernel.org/linux-riscv/1593266228-61125-1-git-send-email-guo...@kernel.org/T/#t
Signed-off-by: Guo Ren
Reported-by: Aurelien Jarno
Cc: Palmer Dabbelt
Cc: Atish Patra
Cc: Andreas Schwab
Cc: Aurelien Jarno
---
arch/riscv/inclu
On Tue, 06 Oct 2020 03:39:06 PDT (-0700), Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
arch/riscv/mm/init.c
between commit:
c29c38fa2a8b ("RISC-V: Remove any memblock representing unusable memory area")
from the risc-v tree and comm
:issuer "pal...@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt " [ultimate]
gpg: aka "Palmer Dabbelt " [ultimate]
Author: Guo Ren
Date: Tue Oct 6 16:49:33 2020 +
riscv: Fixup bootup failure with HARDENED_USERCOPY
On Mon, 05 Oct 2020 14:12:44 PDT (-0700), ati...@atishpatra.org wrote:
On Mon, Oct 5, 2020 at 12:46 PM Palmer Dabbelt wrote:
On Mon, 05 Oct 2020 11:40:54 PDT (-0700), sch...@linux-m68k.org wrote:
> On Okt 05 2020, Palmer Dabbelt wrote:
>
>> On Mon, 05 Oct 2020 01:25:22 PDT
On Mon, 05 Oct 2020 11:40:54 PDT (-0700), sch...@linux-m68k.org wrote:
On Okt 05 2020, Palmer Dabbelt wrote:
On Mon, 05 Oct 2020 01:25:22 PDT (-0700), sch...@linux-m68k.org wrote:
On Sep 14 2020, Aurelien Jarno wrote:
How should we proceed to get that fixed in time for 5.9? For the older
On Mon, 05 Oct 2020 01:25:22 PDT (-0700), sch...@linux-m68k.org wrote:
On Sep 14 2020, Aurelien Jarno wrote:
How should we proceed to get that fixed in time for 5.9? For the older
branches where it has been backported (so far 5.7 and 5.8), should we
just get that commit reverted instead?
Why
On Mon, 05 Oct 2020 00:16:32 PDT (-0700), Christoph Hellwig wrote:
On Fri, Oct 02, 2020 at 09:07:27AM -0700, Palmer Dabbelt wrote:
* The addition of a symbol export for clint_time_val, which has been inlined
into some timex functions and can be used by drivers.
Err, haven't we just a
On Thu, 01 Oct 2020 12:05:57 PDT (-0700), Atish Patra wrote:
RISC-V limits the physical memory size by -PAGE_OFFSET. Any memory beyond
that size from DRAM start is unusable. Just remove any memblock pointing
to those memory region without worrying about computing the maximum size.
Signed-off-by:
On Thu, 01 Oct 2020 12:04:56 PDT (-0700), Atish Patra wrote:
Currently, the memory containing DT is not reserved. Thus, that region
of memory can be reallocated or reused for other purposes. This may result
in corrupted DT for nommu virt board in Qemu. We may not face any issue
in kendryte as DT
On Sun, 04 Oct 2020 14:16:10 PDT (-0700), a...@kernel.org wrote:
On Sun, 4 Oct 2020 at 20:48, Stephan Müller wrote:
The RISC-V architecture is about to implement the callback
random_get_entropy with a function that is not exported to modules.
Why is that? Wouldn't it be better to export the
On Sat, 26 Sep 2020 12:13:41 PDT (-0700), Arnd Bergmann wrote:
On Sat, Sep 26, 2020 at 7:50 PM Palmer Dabbelt wrote:
I'm OK taking it, but there's a few things I'd like to sort out. IIRC I put it
on a temporary branch over here
https://git.kernel.org/pub/scm/linux/ke
On Thu, 17 Sep 2020 15:37:09 PDT (-0700), Atish Patra wrote:
This series adds UEFI support for RISC-V.
Thanks, this is on for-next.
Palmer Dabbelt (1):
clocksource: clint: Export clint_time_val for modules
arch/riscv/include/asm/stackprotector.h | 4
arch/riscv/include/asm/timex.h | 13 +
drivers/clocksource/timer-clint.c | 1 +
3 files changed, 14 insertions(+), 4 deletions(-)
boot_init_stack_canary() on get_cycles() and this is aligned with the
boot_init_stack_canary() implementations of ARM, ARM64 and MIPS kernel.
Fixes: d5be89a8d118 ("RISC-V: Resurrect the MMIO timer implementation
for M-mode systems")
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
---
Changes since v
On Mon, 28 Sep 2020 05:49:28 PDT (-0700), Christoph Hellwig wrote:
On Sat, Sep 26, 2020 at 10:50:52AM -0700, Palmer Dabbelt wrote:
On Mon, 21 Sep 2020 21:37:52 PDT (-0700), Christoph Hellwig wrote:
Given tht we've not made much progress with the common branch,
are you fine just picking th
boot_init_stack_canary() implementations of ARM, ARM64 and MIPS kernel.
Fixes: d5be89a8d118 ("RISC-V: Resurrect the MMIO timer implementation
for M-mode systems")
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
---
Changes since v2:
- Take different approach and provide custom random_g
On Sat, 26 Sep 2020 22:38:17 PDT (-0700), a...@brainfault.org wrote:
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
>> The NoMMU kernel is broken for QEMU vir
On Sat, 26 Sep 2020 22:35:39 PDT (-0700), a...@brainfault.org wrote:
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
>> The NoMMU kernel is broken for QEMU vir
On Fri, 18 Sep 2020 01:55:58 PDT (-0700), li...@allwinnertech.com wrote:
The argument to pfn_to_virt() should be pfn not the value of CSR_SATP.
Reviewed-by: Palmer Dabbelt
Signed-off-by: liush
IIUC you're supposed to use an actual name.
---
arch/riscv/mm/fault.c | 4 +++-
1
On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
because the get_cycles() and friends are called very early from
rand_initialize() before CLINT driver is probed
does not
seem to cause any problem for now.
Signed-off-by: Damien Le Moal
Signed-off-by: Palmer Dabbelt
Signed-off-by: Sasha Levin
---
arch/riscv/boot/dts/kendryte/k210.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi
b/arch
On Mon, 21 Sep 2020 21:37:52 PDT (-0700), Christoph Hellwig wrote:
Given tht we've not made much progress with the common branch,
are you fine just picking this up through the riscv tree for 5.10?
I'll defer other architectures that depend on the common changes to
5.11 then.
I'm OK taking it,
ryte K210 device tree
Greentime Hu (1):
riscv: Add sfence.vma after early page table changes
Palmer Dabbelt (2):
RISC-V: Take text_mutex in ftrace_init_nop()
RISC-V: Resurrect the MMIO timer implementation for M-mode systems
arch/riscv/Kconfig | 1 +
arch/ris
On Mon, 14 Sep 2020 20:58:13 PDT (-0700), greentime...@sifive.com wrote:
Palmer Dabbelt 於 2020年8月5日 週三 上午10:03寫道：
On Mon, 03 Aug 2020 20:29:32 PDT (-0700), a...@brainfault.org wrote:
> On Tue, Aug 4, 2020 at 8:32 AM Greentime Hu wrote:
>>
>> This patch addes local_flush_tlb_pa
On Sun, 13 Sep 2020 18:52:03 PDT (-0700), li...@allwinnertech.com wrote:
This patch adds a cpuidle driver for systems based RISCV architecture.
This patch supports state WFI. Other states will be supported in the
future.
Signed-off-by: liush
---
arch/riscv/Kconfig | 7 +
arc
On Tue, 08 Sep 2020 23:55:15 PDT (-0700), Christoph Hellwig wrote:
On Tue, Sep 08, 2020 at 09:59:29PM -0700, Palmer Dabbelt wrote:
The first four patches are general improvements and enablement for all nommu
ports, and might make sense to merge through the above base branch.
Seems like it to
On Tue, 08 Sep 2020 23:00:45 PDT (-0700), Christoph Hellwig wrote:
On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote:
I don't know enough about the block to know if the subtle difference in
register names/offsets means. They look properly jumbled up (ie, not just an
offset
gt;sp = sp;
- set_fs(USER_DS);
}
void flush_thread(void)
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
; \
+} while (0)
+
#else /* CONFIG_MMU */
#include
#endif /* CONFIG_MMU */
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
;\
- } \
+ \
+ __enable_user_access(); \
+ __put_user_nocheck(x, __gu_ptr, __pu_err); \
+ __disable_user_access();\
+ \
__pu_err; \
})
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
On Sun, 06 Sep 2020 22:58:17 PDT (-0700), Christoph Hellwig wrote:
Hi all,
this series converts riscv to the new set_fs less world and is on top of this
branch:
https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git/log/?h=base.set_fs
The first four patches are general improvements
Dabbelt
Acked-by: Palmer Dabbelt
arch/$(SRCARCH)/include/asm/module.lds.h, which is included from
scripts/module.lds.S.
scripts/module.lds is fine because 'make clean' keeps all the
build artifacts under scripts/.
You can add arch-specific sections in .
for the arch/riscv stuff
Acked-by: Palmer Dabbelt
Thanks!
On Sun, 06 Sep 2020 23:11:26 PDT (-0700), Christoph Hellwig wrote:
On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote:
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be
On Fri, 28 Aug 2020 10:20:27 PDT (-0700), Atish Patra wrote:
This series adds UEFI support for RISC-V.
Linux kernel: v5.9-rc2
U-Boot: v2020.07
OpenSBI: master
Patch 1-3 are generic riscv feature addition required for UEFI support.
Patch 4-7 adds the efi stub support for RISC-V which was reviewe
On Fri, 04 Sep 2020 09:57:09 PDT (-0700), Christoph Hellwig wrote:
On Fri, Sep 04, 2020 at 10:13:18PM +0530, Anup Patel wrote:
I respectfully disagree. IMHO, the previous code made the RISC-V
timer driver convoluted (both SBI call and CLINT in one place) and
mandated CLINT for NoMMU kernel. In f
On Mon, 31 Aug 2020 00:33:47 PDT (-0700), zong...@sifive.com wrote:
There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
could use them to
On Thu, 27 Aug 2020 01:22:25 PDT (-0700), zong...@sifive.com wrote:
There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
could use them to
On Thu, 27 Aug 2020 10:02:57 PDT (-0700), Atish Patra wrote:
On Thu, 2020-08-27 at 10:37 +0200, Anders Roxell wrote:
On Thu, 27 Aug 2020 at 07:11, Stephen Rothwell
wrote:
> Hi all,
>
> News: There will be no linux-next releases next Monday or Tuesday.
>
> Changes since 20200826:
>
> The net
On Wed, 26 Aug 2020 04:22:07 PDT (-0700), a...@kernel.org wrote:
On Tue, 25 Aug 2020 at 20:04, Palmer Dabbelt wrote:
On Wed, 19 Aug 2020 15:24:16 PDT (-0700), Atish Patra wrote:
> This series adds UEFI support for RISC-V.
>
> Linux kernel: v5.9-rc1
> U-Boot: v2020.07
>
lk);
- }
+ if (IS_ERR(ddata->clk))
+ return dev_err_probe(dev, PTR_ERR(ddata->clk),
+"Unable to find controller clock\n");
ret = clk_prepare_enable(ddata->clk);
if (ret) {
Acked-by: Palmer Dabbelt
On Wed, 19 Aug 2020 15:24:16 PDT (-0700), Atish Patra wrote:
This series adds UEFI support for RISC-V.
Linux kernel: v5.9-rc1
U-Boot: v2020.07
OpenSBI: master
Patch 1-3 are generic riscv feature addition required for UEFI support.
Patch 4-7 adds the efi stub support for RISC-V which was reviewe
On Wed, 19 Aug 2020 15:24:21 PDT (-0700), Atish Patra wrote:
Linux kernel Image can appear as an EFI application With appropriate
PE/COFF header fields in the beginning of the Image header. An EFI
application loader can directly load a Linux kernel Image and an EFI
stub residing in kernel can boo
On Tue, 25 Aug 2020 09:19:58 PDT (-0700), b...@alien8.de wrote:
On Tue, Aug 25, 2020 at 09:02:54AM -0700, Palmer Dabbelt wrote:
Thanks. These look good to me and I'm happy to take them through the RISC-V
tree, but I'm going to wait for a bit to see if there are any comment
On Tue, 25 Aug 2020 05:06:19 PDT (-0700), yash.s...@sifive.com wrote:
The series add supports for SiFive DDR controller driver. This driver
is use to manage the Cadence DDR controller present in SiFive SoCs.
Currently it manages only the EDAC feature of the DDR controller.
The series also adds Me
device_unregister(sifive_pdev);
+ ret = ecc_mc_register(sifive_pdev);
+ if (ret) {
+ ecc_unregister(sifive_pdev);
+ platform_device_unregister(sifive_pdev);
+ }
+
return ret;
}
static void __exit sifive_edac_exit(void)
{
ecc_unregister(sifive_pdev);
+ ecc_mc_unregister(sifive_pdev);
platform_device_unregister(sifive_pdev);
}
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
interrupts = <31>;
+};
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
MASK GENMASK(6, 5)
+#define ECC_INT_CE_EVENT BIT(3)
+#define ECC_INT_SECOND_CE_EVENTBIT(4)
+#define ECC_INT_UE_EVENT BIT(5)
+#define ECC_INT_SECOND_UE_EVENT BIT(6)
+#define ECC_CTL_ECC_ENABLE BIT(16)
+
+#define ECC_C_ID_MASK GENMASK(28, 16)
+#define ECC_U_ID_MASK GENMASK(12, 0)
+#define ECC_C_ID_SHIFT (16)
+#define ECC_U_ID_SHIFT (0)
+#define ECC_SYND_MASK GENMASK(15, 8)
+#define ECC_SYND_SHIFT (8)
+
+#define CTL_REG_WIDTH_SHIFT(32)
+
+#endif /* __SOC_SIFIVE_DDR_H */
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
On Thu, 13 Aug 2020 08:37:43 PDT (-0700), rost...@goodmis.org wrote:
On Wed, 12 Aug 2020 22:13:19 -0700 (PDT)
Palmer Dabbelt wrote:
Sorry, I'm not really sure what's going on here. I'm not really seeing code
that matches this in our port right now, so maybe this is aginst
The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5:
Linux 5.9-rc1 (2020-08-16 13:04:57 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.9-rc2
for you to fetch changes up to fc26f5bbf
On Fri, 03 Jul 2020 01:57:52 PDT (-0700), zong...@sifive.com wrote:
There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
could use them to
On Fri, 03 Jul 2020 01:57:53 PDT (-0700), zong...@sifive.com wrote:
Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: Zong Li
---
arch/riscv/kernel/cacheinfo.c | 59 ++---
init(struct cacheinfo *this_leaf, enum cache_type type,
unsigned int level, unsigned int size,
Reviewed-by: Palmer Dabbelt
riscv/include/uapi/asm/auxvec.h
@@ -10,4 +10,7 @@
/* vDSO location */
#define AT_SYSINFO_EHDR 33
+/* entries in ARCH_DLINFO */
+#define AT_VECTOR_SIZE_ARCH1
+
#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
Reviewed-by: Palmer Dabbelt
On Tue, 18 Aug 2020 02:29:53 PDT (-0700), bmeng...@gmail.com wrote:
On Fri, Jul 17, 2020 at 12:39 AM Alistair Francis
wrote:
On Wed, 2020-07-15 at 21:39 -0700, Bin Meng wrote:
> From: Bin Meng
>
> This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> 64-bit config. This is us
On Mon, 17 Aug 2020 05:42:47 PDT (-0700), Anup Patel wrote:
The current RISC-V timer driver is convoluted and implements two
distinct timers:
1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented usin
ptr_t dtb_pa)
#else
dtb_early_va = (void *)dtb_pa;
#endif
+ dtb_early_pa = dtb_pa;
}
static inline void setup_vm_final(void)
Reviewed-by: Palmer Dabbelt
pr_warn("FIX_BTMAP_BEGIN: %d\n", FIX_BTMAP_BEGIN);
+ }
+#endif
}
static void __init setup_vm_final(void)
Reviewed-by: Palmer Dabbelt
merged tag 'riscv-for-linus-5.9-mw0'
The following changes since commit dbf83817315d9ce93b3e5b1c83a167f537245bd8:
Merge tag 'riscv-for-linus-5.9-mw0' of
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2020-08-07 10:11:12
-0700)
are available in the Git repository at:
git://git.k
On Thu, 13 Aug 2020 01:49:44 PDT (-0700), a...@brainfault.org wrote:
On Thu, Aug 13, 2020 at 9:10 AM Qiu Wenbo wrote:
Exception vector is missing on nommu platform and that is an issue.
This patch is tested in Sipeed Maix Bit Dev Board.
Fixes: 79b1feba5455 ("RISC-V: Setup exception vector ear
ff-by: Guo Ren
Cc: Masami Hiramatsu
Cc: Palmer Dabbelt
---
arch/riscv/kernel/mcount-dyn.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
index 35a6ed7..4b58b54 100644
--- a/arch/riscv/kernel/mcount-dyn.S
+++ b/
l.org/linux-csky/20200403044150.20562-9-guo...@kernel.org/
Signed-off-by: Guo Ren
Co-Developed-by: Patrick Stählin
Acked-by: Masami Hiramatsu
Tested-by: Zong Li
Reviewed-by: Pekka Enberg
Cc: Patrick Stählin
Cc: Palmer Dabbelt
Cc: Björn Töpel
---
arch/riscv/Kconfig
h doesn't have any checks against text_mutex being held,
because it only happens at boot up.
The solution is ok for me, but I want to get riscv maintainer's
opinion before the next patch.
@Paul Walmsley
@Palmer Dabbelt
Sorry, I'm not really sure what's going on here. I'm
The following changes since commit 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68:
Linux 5.8-rc3 (2020-06-28 15:00:24 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.9-mw0
for you to fetch changes up to 40284a072
On Wed, 05 Aug 2020 03:25:11 PDT (-0700), ma...@wdc.com wrote:
On Wed, 5 Aug 2020, Al Viro wrote:
> I'm not sure I understand what you're saying, but given that branch replaces
> all of this I guess it's best to just do nothing on our end here?
It doesn't replace ->put() (for now); it _does_ r
On Tue, 04 Aug 2020 19:48:07 PDT (-0700), v...@zeniv.linux.org.uk wrote:
On Tue, Aug 04, 2020 at 07:20:05PM -0700, Palmer Dabbelt wrote:
On Tue, 04 Aug 2020 19:07:45 PDT (-0700), v...@zeniv.linux.org.uk wrote:
> On Tue, Aug 04, 2020 at 07:01:01PM -0700, Palmer Dabbelt wrote:
>
&g
On Tue, 04 Aug 2020 19:07:45 PDT (-0700), v...@zeniv.linux.org.uk wrote:
On Tue, Aug 04, 2020 at 07:01:01PM -0700, Palmer Dabbelt wrote:
> We currently have @start_pos fixed at 0 across all calls, which works as
> a result of the implementation, in particular because we have no p
On Mon, 03 Aug 2020 20:29:32 PDT (-0700), a...@brainfault.org wrote:
On Tue, Aug 4, 2020 at 8:32 AM Greentime Hu wrote:
This patch addes local_flush_tlb_page(addr) to use sfence.vma after the
s/addes/adds
page table changed. That address will be used immediately in
memset(nextp, 0, PAGE_SI
offsetof(struct __riscv_d_ext_state,
fcsr) +
-sizeof(fstate->fcsr));
+&fstate->fcsr, fgr_size,
+fgr_size + sizeof(fstate->fcsr));
}
return ret;
Reviewed-by: Palmer Dabbelt
(Though the comments in the first patch apply here)
Thanks!
On Thu, 23 Jul 2020 16:22:15 PDT (-0700), ma...@wdc.com wrote:
Adjust the calls to `user_regset_copyout' and `user_regset_copyin' in
`riscv_fpr_get' and `riscv_fpr_set' respectively so as to use @start_pos
and @end_pos according to API documentation in , that is
to point at the beginning and the
On Fri, 24 Jul 2020 00:18:22 PDT (-0700), Anup Patel wrote:
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
---
.../bindings/timer/sifive,clint.yaml | 60 +++
1 file changed, 60
On Fri, 24 Jul 2020 00:18:18 PDT (-0700), Anup Patel wrote:
The current RISC-V timer driver is convoluted and implements two
distinct timers:
1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented usin
--git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 191772d4a4d7..1451f4625833 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -132,6 +132,7 @@ enum cpuhp_state {
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
CPUHP_AP_ARC_TIMER_STARTING,
CPUHP_AP_RISCV_TIMER_STARTING,
+ CPUHP_AP_CLINT_TIMER_STARTING,
CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,
Reviewed-by: Palmer Dabbelt
);
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_set_timer(get_cycles64() + delta);
- else
- mmio_set_timer(get_cycles64() + delta);
+ sbi_set_timer(get_cycles64() + delta);
return 0;
}
Reviewed-by: Palmer Dabbelt
@@ -147,8 +147,7 @@ asmlinkage __visible void smp_callin(void)
{
struct mm_struct *mm = &init_mm;
- if (!IS_ENABLED(CONFIG_RISCV_SBI))
- clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
+ riscv_clear_ipi();
/* All kernel threads share the same mm context. */
mmgrab(mm);
I don't really care that much, though, so:
Reviewed-by: Palmer Dabbelt
On Tue, 04 Aug 2020 17:39:43 PDT (-0700), Stephen Rothwell wrote:
Hi all,
On Mon, 13 Jul 2020 16:58:46 +1000 Stephen Rothwell
wrote:
Today's linux-next merge of the pidfd tree got a conflict in:
arch/riscv/Kconfig
between commit:
95ce6c73da3b ("riscv: Enable context tracking")
929f6
On Mon, 27 Jul 2020 20:33:58 PDT (-0700), npig...@gmail.com wrote:
Cc: Paul Walmsley
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc: linux-ri...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/riscv/include/asm/mmu_context.h | 22 ++
1 file changed, 2 insertions(+), 20
On Thu, 23 Jul 2020 09:36:28 PDT (-0700), ker...@esmil.dk wrote:
Like other arch's we use patch_text_nosync or equivalent
to patch the jump-labels, but also like other arch's we
need to hold the text_mutex before calling that.
Signed-off-by: Emil Renner Berthing
---
Fixes: b6e0878a4ec8 ("riscv
On Mon, 20 Jul 2020 14:38:49 PDT (-0700), sas...@kernel.org wrote:
From: Palmer Dabbelt
[ Upstream commit 38b7c2a3ffb1fce8358ddc6006cfe5c038ff9963 ]
While digging through the recent mmiowb preemption issue it came up that
we aren't actually preventing IO from crossing a scheduling bou
>
>> Signed-off-by: Anup Patel
>> Reviewed-by: Palmer Dabbelt
>> Tested-by: Emil Renner Berhing
>> ---
>> .../bindings/timer/sifive,clint.yaml | 58 +++
>> 1 file changed, 58 insertions(+)
>> create mode 100644 Documentation
__ARCH_WANT_SECRETMEMFD
#include
Acked-by: Palmer Dabbelt
The following changes since commit ba47d845d715a010f7b51f6f89bae32845e6acb7:
Linux 5.8-rc6 (2020-07-19 15:41:18 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.8-rc7
for you to fetch changes up to fa5a19835
On Wed, 15 Jul 2020 23:15:25 PDT (-0700), zong...@sifive.com wrote:
These patches fix some build warnings when W=1, the most of warnings are
missing prototype as follows:
arch/riscv/mm/init.c:520:13: warning: no previous prototype for 'resource_init'
[-Wmissing-prototypes]
arch/riscv/mm/pageatt
On Wed, 15 Jul 2020 16:30:09 PDT (-0700), Atish Patra wrote:
Currently, maximum physical memory allowed is equal to -PAGE_OFFSET.
That's why we remove any memory blocks spanning beyond that size. However,
it is done only for memblock containing linux kernel which will not work
if there are multip
On Wed, 15 Jul 2020 16:30:08 PDT (-0700), Atish Patra wrote:
Currently, initrd_start/end are computed during early_init_dt_scan
but used during arch_setup. We will get the following panic if initrd is used
and CONFIG_DEBUG_VIRTUAL is turned on.
[0.00] [ cut here ]
On Wed, 15 Jul 2020 16:30:06 PDT (-0700), Atish Patra wrote:
The trap vector is set only in trap_init which may be too late in some
cases. Early ioremap/efi spits many warning messages which may be useful.
Setup the trap vector early so that any warning/bug can be handled before
generic code inv
On Wed, 15 Jul 2020 16:30:07 PDT (-0700), Atish Patra wrote:
Currently, maximum number of mapper pages are set to the pfn calculated
from the memblock size of the memblock containing kernel. This will work
until that memblock spans the entire memory. However, it will be set to
a wrong value if th
generate mul(w) instruction in this case
+ */
+#if defined(CONFIG_ARCH_HAS_FAST_MULTIPLIER) && !defined(CONFIG_RISCV)
w -= (w >> 1) & 0x;
w = (w & 0x) + ((w >> 2) & 0x);
w = (w + (w >> 4)) & 0x0f0f0f0f;
Ch
On Wed, 22 Jul 2020 02:43:50 PDT (-0700), Arnd Bergmann wrote:
On Tue, Jul 21, 2020 at 9:06 PM Palmer Dabbelt wrote:
On Tue, 21 Jul 2020 11:36:10 PDT (-0700), a...@ghiti.fr wrote:
> Let's try to make progress here: I add linux-mm in CC to get feedback on
> this patch as it blocks s
On Tue, 21 Jul 2020 21:50:42 PDT (-0700), m...@ellerman.id.au wrote:
Benjamin Herrenschmidt writes:
On Tue, 2020-07-21 at 16:48 -0700, Palmer Dabbelt wrote:
> Why ? Branch distance limits ? You can't use trampolines ?
Nothing fundamental, it's just that we don't have a l
On Tue, 14 Jul 2020 14:26:11 PDT (-0700), ker...@esmil.dk wrote:
This allows the pgtable tests to be built.
Signed-off-by: Emil Renner Berthing
---
The tests seem to succeed both in Qemu and on the HiFive Unleashed
Both with and without the recent additions in
https://lore.kernel.org/linux-ri
On Mon, 13 Jul 2020 01:32:16 PDT (-0700), greentime...@sifive.com wrote:
This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the
code flow for both m-mode and s-mode then we can remove the ifdef here.
Signed-off-by: Greentime Hu
---
arch/riscv/kernel/entry.S | 7 +--
On Mon, 13 Jul 2020 01:32:15 PDT (-0700), greentime...@sifive.com wrote:
arch/riscv/kernel/entry.S: Assembler messages:
arch/riscv/kernel/entry.S:106: Error: illegal operands `andi a0,s1,0x1800'
This building error is because of the SR_MPP value is too large to be used
as an immediate value
this on for-next.
Thanks!
ret
ENDPROC(__switch_to)
Reviewed-by: Palmer Dabbelt
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