We shouldn't be directly passing device tree values to userspace, both
because there could be mistakes in device trees and because the kernel
doesn't support arbitrary ISAs.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/cpu.c | 62 +++--
1 file
f1f1007644ff ("mm: add new mmgrab() helper") added a helper that we
missed out on.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpbo
This isn't readily apparent from reading the code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 5437a04babcd..953bc540207d 100644
--- a/arch/riscv/kernel
The old name was a bit odd.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 5f29f8562cf6..e1f6a5ad0416 100644
--- a/arch/riscv/kernel
These are just hard coded in the RISC-V port, which doesn't make any
sense. We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel
It's a bit confusing exactly what this function does: it actually
returns the hartid of an OF processor node, failing with -1 on invalid
nodes. I've changed the name to _hartid() in order to make that a bit
more clear, as well as adding a comment.
Signed-off-by: Palmer Dabbelt
---
arch/riscv
It's a bit confusing exactly what this function does: it actually
returns the hartid of an OF processor node, failing with -1 on invalid
nodes. I've changed the name to _hartid() in order to make that a bit
more clear, as well as adding a comment.
Signed-off-by: Palmer Dabbelt
---
arch/riscv
The old name was a bit odd.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 5f29f8562cf6..e1f6a5ad0416 100644
--- a/arch/riscv/kernel
These are just hard coded in the RISC-V port, which doesn't make any
sense. We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel
I'm not sure, but I think this was a bug: if the scheduler fired right
here then I believe it would blow up.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel
I'm not sure, but I think this was a bug: if the scheduler fired right
here then I believe it would blow up.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel
I'm not sure how I managed to miss this the first time, but this is much
better.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/smp.h | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
I'm not sure how I managed to miss this the first time, but this is much
better.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/smp.h | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
I finally got around to answering a very old email in my inbox that was
a response to our original patch set. These are meant to cause little
to no functional changes to the port, but I've given them very little
testing so I wouldn't be surprised if I've managed to screw something
up here.
I'll
I finally got around to answering a very old email in my inbox that was
a response to our original patch set. These are meant to cause little
to no functional changes to the port, but I've given them very little
testing so I wouldn't be surprised if I've managed to screw something
up here.
I'll
ter type. Here it is with a commit message,
although still untested because I haven't got round to setting up a riscv
toolchain yet.
FWIW, Arnd built them last time he updated the cross tools so you should be
able to get GCC 8.1.0 for RISC-V from there. I use this make.cross script that
I stole
ter type. Here it is with a commit message,
although still untested because I haven't got round to setting up a riscv
toolchain yet.
FWIW, Arnd built them last time he updated the cross tools so you should be
able to get GCC 8.1.0 for RISC-V from there. I use this make.cross script that
I stole
essing around in here recently and
assumed there was some reason for the non-orthogonality. As far as the RISC-V
stuff goes, feel free to add a
Reviewed-by: Palmer Dabbelt
I can deal with the inevitable merge conflicts on our end, as they'll be
trivial :).
essing around in here recently and
assumed there was some reason for the non-orthogonality. As far as the RISC-V
stuff goes, feel free to add a
Reviewed-by: Palmer Dabbelt
I can deal with the inevitable merge conflicts on our end, as they'll be
trivial :).
On Tue, 21 Aug 2018 23:03:53 PDT (-0700), Christoph Hellwig wrote:
On Tue, Aug 21, 2018 at 10:34:38PM +0530, Anup Patel wrote:
The cpu_operations is certainly required because SOC vendors will add
vendor-specific mechanism to selectively bringing-up CPUs/HARTs instead
of all CPUs entering Linux
On Tue, 21 Aug 2018 23:03:53 PDT (-0700), Christoph Hellwig wrote:
On Tue, Aug 21, 2018 at 10:34:38PM +0530, Anup Patel wrote:
The cpu_operations is certainly required because SOC vendors will add
vendor-specific mechanism to selectively bringing-up CPUs/HARTs instead
of all CPUs entering Linux
On Tue, 21 Aug 2018 12:45:50 PDT (-0700), mer...@debian.org wrote:
On Tue, Aug 21, 2018 at 11:31:48AM -0700, Palmer Dabbelt wrote:
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
[...]
> Do you have vmlinux embedded in bbl ?
>
> With separate bbl an
On Tue, 21 Aug 2018 12:45:50 PDT (-0700), mer...@debian.org wrote:
On Tue, Aug 21, 2018 at 11:31:48AM -0700, Palmer Dabbelt wrote:
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
[...]
> Do you have vmlinux embedded in bbl ?
>
> With separate bbl an
urce()")
first patched then removed pcibios_align_resource() from the microblaze
architecture code but failed to remove the comment that was added to
it.
Remove it since it has now become stale and it is quite confusing.
Signed-off-by: Lorenzo Pieralisi
Cc: Palmer Dabbelt
Cc: Bjorn Helgaas
Cc:
urce()")
first patched then removed pcibios_align_resource() from the microblaze
architecture code but failed to remove the comment that was added to
it.
Remove it since it has now become stale and it is quite confusing.
Signed-off-by: Lorenzo Pieralisi
Cc: Palmer Dabbelt
Cc: Bjorn Helgaas
Cc:
On Mon, 20 Aug 2018 19:47:28 PDT (-0700), alan...@andestech.com wrote:
On Mon, Aug 20, 2018 at 03:22:55PM -0700, Palmer Dabbelt wrote:
On Tue, 07 Aug 2018 20:24:43 PDT (-0700), alan...@andestech.com wrote:
>Just a side note: (Assume that atomic and compressed is on)
>
>Before t
On Mon, 20 Aug 2018 19:47:28 PDT (-0700), alan...@andestech.com wrote:
On Mon, Aug 20, 2018 at 03:22:55PM -0700, Palmer Dabbelt wrote:
On Tue, 07 Aug 2018 20:24:43 PDT (-0700), alan...@andestech.com wrote:
>Just a side note: (Assume that atomic and compressed is on)
>
>Before t
On Sat, 18 Aug 2018 11:15:18 PDT (-0700), Linus Torvalds wrote:
On Fri, Aug 17, 2018 at 1:28 PM Palmer Dabbelt wrote:
I remember having sent this on Wednesday, but for some reason I don't see it in
your tree or my outbox so I might be crazy.
You might indeed have been having hallucinations
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
Hi Palmer,
On Fri, Aug 17, 2018 at 01:28:11PM -0700, Palmer Dabbelt wrote:
[ ... ]
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
On Sat, 18 Aug 2018 11:15:18 PDT (-0700), Linus Torvalds wrote:
On Fri, Aug 17, 2018 at 1:28 PM Palmer Dabbelt wrote:
I remember having sent this on Wednesday, but for some reason I don't see it in
your tree or my outbox so I might be crazy.
You might indeed have been having hallucinations
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
Hi Palmer,
On Fri, Aug 17, 2018 at 01:28:11PM -0700, Palmer Dabbelt wrote:
[ ... ]
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
On Tue, 14 Aug 2018 06:39:23 PDT (-0700), Christoph Hellwig wrote:
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
uintptr_t, flags)
{
+#ifdef CONFIG_SMP
struct mm_struct *mm = current->mm;
bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0;
On Tue, 14 Aug 2018 06:39:23 PDT (-0700), Christoph Hellwig wrote:
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
uintptr_t, flags)
{
+#ifdef CONFIG_SMP
struct mm_struct *mm = current->mm;
bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0;
On Tue, 14 Aug 2018 06:40:27 PDT (-0700), Christoph Hellwig wrote:
index 818655b0d535..690beb002d1d 100644
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ b/arch/riscv/include/uapi/asm/syscalls.h
@@ -1,10 +1,13 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
On Tue, 14 Aug 2018 06:40:27 PDT (-0700), Christoph Hellwig wrote:
index 818655b0d535..690beb002d1d 100644
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ b/arch/riscv/include/uapi/asm/syscalls.h
@@ -1,10 +1,13 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
l interrupt
controller")
Cc: Rob Herring
Cc: Christoph Hellwig
Cc: Karsten Merker
Signed-off-by: Palmer Dabbelt
---
.../bindings/interrupt-controller/riscv,cpu-intc.txt | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git
a/Documentation/devicetree/bi
l interrupt
controller")
Cc: Rob Herring
Cc: Christoph Hellwig
Cc: Karsten Merker
Signed-off-by: Palmer Dabbelt
---
.../bindings/interrupt-controller/riscv,cpu-intc.txt | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git
a/Documentation/devicetree/bi
On Thu, 09 Aug 2018 21:11:40 PDT (-0700), li...@roeck-us.net wrote:
setup_initrd() does not appear to serve a practical purpose other than
preventing qemu boots with "-initrd" parameter, so let's drop it.
Signed-off-by: Guenter Roeck
---
arch/riscv/kernel/setup.c | 39
On Thu, 09 Aug 2018 21:11:40 PDT (-0700), li...@roeck-us.net wrote:
setup_initrd() does not appear to serve a practical purpose other than
preventing qemu boots with "-initrd" parameter, so let's drop it.
Signed-off-by: Guenter Roeck
---
arch/riscv/kernel/setup.c | 39
On Tue, 07 Aug 2018 20:24:40 PDT (-0700), alan...@andestech.com wrote:
This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point procedures.
Kernel's new behavior will be as follows:
* with CONFIG_FPU=y
All FPU codes are reserved. If no FPU is found during booting, a
On Tue, 07 Aug 2018 20:24:40 PDT (-0700), alan...@andestech.com wrote:
This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point procedures.
Kernel's new behavior will be as follows:
* with CONFIG_FPU=y
All FPU codes are reserved. If no FPU is found during booting, a
On Tue, 07 Aug 2018 20:24:43 PDT (-0700), alan...@andestech.com wrote:
Just a side note: (Assume that atomic and compressed is on)
Before this patch, assembler was always given the riscv64imafdc
MARCH string because there are fld/fsd's in entry.S; compiler was
always given riscv64imac because
On Tue, 07 Aug 2018 20:24:43 PDT (-0700), alan...@andestech.com wrote:
Just a side note: (Assume that atomic and compressed is on)
Before this patch, assembler was always given the riscv64imafdc
MARCH string because there are fld/fsd's in entry.S; compiler was
always given riscv64imac because
: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: add a definition for the SIE SEIE bit
RISC-V: implement low-level interrupt handling
irqchip: add a SiFive PLIC driver
Jim Wilson (1):
RISC-V: Don't increment sepc after breakpoint.
Palmer Dabbelt (5):
RIS
: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: add a definition for the SIE SEIE bit
RISC-V: implement low-level interrupt handling
irqchip: add a SiFive PLIC driver
Jim Wilson (1):
RISC-V: Don't increment sepc after breakpoint.
Palmer Dabbelt (5):
RIS
On Fri, 10 Aug 2018 11:31:08 PDT (-0700), atish.pa...@wdc.com wrote:
On 8/6/18 4:17 PM, Atish Patra wrote:
Enabling both CONFIG_PERF_EVENTS without !CONFIG_SMP
generates following compilation error.
arch/riscv/include/asm/perf_event.h:80:2: error: expected
specifier-qualifier-list before
On Fri, 10 Aug 2018 11:47:15 PDT (-0700), li...@roeck-us.net wrote:
On Fri, Aug 10, 2018 at 11:27:37AM -0700, Palmer Dabbelt wrote:
On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote:
>On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote:
>>This would be
On Fri, 10 Aug 2018 11:31:08 PDT (-0700), atish.pa...@wdc.com wrote:
On 8/6/18 4:17 PM, Atish Patra wrote:
Enabling both CONFIG_PERF_EVENTS without !CONFIG_SMP
generates following compilation error.
arch/riscv/include/asm/perf_event.h:80:2: error: expected
specifier-qualifier-list before
On Fri, 10 Aug 2018 11:47:15 PDT (-0700), li...@roeck-us.net wrote:
On Fri, Aug 10, 2018 at 11:27:37AM -0700, Palmer Dabbelt wrote:
On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote:
>On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote:
>>This would be
On Fri, 10 Aug 2018 09:57:03 PDT (-0700), robh...@kernel.org wrote:
On Thu, Aug 9, 2018 at 12:29 AM Palmer Dabbelt wrote:
On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote:
> On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote:
>>
>> On Wed, 08 Aug 2018 07:1
On Fri, 10 Aug 2018 09:57:03 PDT (-0700), robh...@kernel.org wrote:
On Thu, Aug 9, 2018 at 12:29 AM Palmer Dabbelt wrote:
On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote:
> On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote:
>>
>> On Wed, 08 Aug 2018 07:1
On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote:
On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote:
This would be necessary to make non-SMP builds work, but there is
another error in the implementation of our syscall linkage that actually
just causes
On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote:
On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote:
This would be necessary to make non-SMP builds work, but there is
another error in the implementation of our syscall linkage that actually
just causes
On Thu, 09 Aug 2018 19:40:55 PDT (-0700), li...@roeck-us.net wrote:
On 08/09/2018 06:03 PM, Palmer Dabbelt wrote:
On Thu, 09 Aug 2018 14:24:22 PDT (-0700), li...@roeck-us.net wrote:
On Thu, Aug 09, 2018 at 01:25:24PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple
On Thu, 09 Aug 2018 19:40:55 PDT (-0700), li...@roeck-us.net wrote:
On 08/09/2018 06:03 PM, Palmer Dabbelt wrote:
On Thu, 09 Aug 2018 14:24:22 PDT (-0700), li...@roeck-us.net wrote:
On Thu, Aug 09, 2018 at 01:25:24PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple
On Thu, 09 Aug 2018 17:37:39 PDT (-0700), zong...@gmail.com wrote:
Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.
Signed-off-by:
On Thu, 09 Aug 2018 17:37:39 PDT (-0700), zong...@gmail.com wrote:
Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.
Signed-off-by:
On Thu, 09 Aug 2018 14:24:22 PDT (-0700), li...@roeck-us.net wrote:
On Thu, Aug 09, 2018 at 01:25:24PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include
On Thu, 09 Aug 2018 14:24:22 PDT (-0700), li...@roeck-us.net wrote:
On Thu, Aug 09, 2018 at 01:25:24PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include
: Christoph Hellwig
CC: Guenter Roeck
In-Reply-To: <20180809055830.ga17...@infradead.org>
In-Reply-To: <20180809132612.ga31...@roeck-us.net>
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/vdso.h | 2 --
arch/riscv/kernel/sys_riscv.c | 12 ++--
2 files changed, 10 inse
: Christoph Hellwig
CC: Guenter Roeck
In-Reply-To: <20180809055830.ga17...@infradead.org>
In-Reply-To: <20180809132612.ga31...@roeck-us.net>
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/vdso.h | 2 --
arch/riscv/kernel/sys_riscv.c | 12 ++--
2 files changed, 10 inse
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
It turns out that we weren't actually hooking sys_riscv_flush_icache
into the syscall table, which results in any flush_icache() call that
escapes the vDSO to silently do nothing.
Changes since v2:
* sys_riscv_flush_icache actually flushes the icache when SMP=n. Thanks
to Andrew for pointing
It turns out that we weren't actually hooking sys_riscv_flush_icache
into the syscall table, which results in any flush_icache() call that
escapes the vDSO to silently do nothing.
Changes since v2:
* sys_riscv_flush_icache actually flushes the icache when SMP=n. Thanks
to Andrew for pointing
On Wed, 08 Aug 2018 22:58:30 PDT (-0700), Christoph Hellwig wrote:
This actually seems to break the compilation for me in for-next:
hch@carbon:~/work/linux$ make ARCH=riscv
CALLscripts/checksyscalls.sh
:1335:2: warning: #warning syscall rseq not implemented [-Wcpp]
CHK
On Wed, 08 Aug 2018 22:58:30 PDT (-0700), Christoph Hellwig wrote:
This actually seems to break the compilation for me in for-next:
hch@carbon:~/work/linux$ make ARCH=riscv
CALLscripts/checksyscalls.sh
:1335:2: warning: #warning syscall rseq not implemented [-Wcpp]
CHK
On Thu, 09 Aug 2018 06:26:12 PDT (-0700), li...@roeck-us.net wrote:
On Fri, Aug 03, 2018 at 12:53:44PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include
On Thu, 09 Aug 2018 06:26:12 PDT (-0700), li...@roeck-us.net wrote:
On Fri, Aug 03, 2018 at 12:53:44PM -0700, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include
It turns out that we weren't actually hooking sys_riscv_flush_icache
into the syscall table, which results in any flush_icache() call that
escapes the vDSO to silently do nothing.
Changes since v1:
* sys_riscv_flush_icache is now defined even when SMP=n, which allows
this patch set to build
: Christoph Hellwig
CC: Guenter Roeck
In-Reply-To: <20180809055830.ga17...@infradead.org>
In-Reply-To: <20180809132612.ga31...@roeck-us.net>
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/vdso.h | 2 --
arch/riscv/kernel/sys_riscv.c | 10 --
2 files changed, 8 inse
It turns out that we weren't actually hooking sys_riscv_flush_icache
into the syscall table, which results in any flush_icache() call that
escapes the vDSO to silently do nothing.
Changes since v1:
* sys_riscv_flush_icache is now defined even when SMP=n, which allows
this patch set to build
: Christoph Hellwig
CC: Guenter Roeck
In-Reply-To: <20180809055830.ga17...@infradead.org>
In-Reply-To: <20180809132612.ga31...@roeck-us.net>
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/vdso.h | 2 --
arch/riscv/kernel/sys_riscv.c | 10 --
2 files changed, 8 inse
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote:
On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote:
On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote:
> On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote:
>>
>> On Mon, 06 Aug 2018 13:5
On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote:
On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote:
On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote:
> On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote:
>>
>> On Mon, 06 Aug 2018 13:5
On Wed, 08 Aug 2018 09:15:58 PDT (-0700), robh...@kernel.org wrote:
On Wed, Aug 8, 2018 at 8:59 AM Christoph Hellwig wrote:
On Wed, Aug 08, 2018 at 08:29:50AM -0600, Rob Herring wrote:
> Version numbers on the individual patches would be nice...
We've never done these in the subsystems I'm
On Wed, 08 Aug 2018 09:15:58 PDT (-0700), robh...@kernel.org wrote:
On Wed, Aug 8, 2018 at 8:59 AM Christoph Hellwig wrote:
On Wed, Aug 08, 2018 at 08:29:50AM -0600, Rob Herring wrote:
> Version numbers on the individual patches would be nice...
We've never done these in the subsystems I'm
On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote:
On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote:
On Mon, 06 Aug 2018 13:59:48 PDT (-0700), robh...@kernel.org wrote:
> On Thu, Aug 2, 2018 at 4:08 PM Atish Patra wrote:
>>
>> On 8/2/18 4:50 AM, Christop
On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote:
On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote:
On Mon, 06 Aug 2018 13:59:48 PDT (-0700), robh...@kernel.org wrote:
> On Thu, Aug 2, 2018 at 4:08 PM Atish Patra wrote:
>>
>> On 8/2/18 4:50 AM, Christop
On Sat, 04 Aug 2018 01:23:11 PDT (-0700), Christoph Hellwig wrote:
This series tries adds support for interrupt handling and timers
for the RISC-V architecture.
The basic per-hart interrupt handling implemented by the scause
and sie CSRs is extremely simple and implemented directly in
On Sat, 04 Aug 2018 01:23:11 PDT (-0700), Christoph Hellwig wrote:
This series tries adds support for interrupt handling and timers
for the RISC-V architecture.
The basic per-hart interrupt handling implemented by the scause
and sie CSRs is extremely simple and implemented directly in
On Mon, 06 Aug 2018 13:59:48 PDT (-0700), robh...@kernel.org wrote:
On Thu, Aug 2, 2018 at 4:08 PM Atish Patra wrote:
On 8/2/18 4:50 AM, Christoph Hellwig wrote:
> From: Palmer Dabbelt
>
> This patch adds documentation for the platform-level interrupt
> controller (PLIC) found i
On Mon, 06 Aug 2018 13:59:48 PDT (-0700), robh...@kernel.org wrote:
On Thu, Aug 2, 2018 at 4:08 PM Atish Patra wrote:
On 8/2/18 4:50 AM, Christoph Hellwig wrote:
> From: Palmer Dabbelt
>
> This patch adds documentation for the platform-level interrupt
> controller (PLIC) found i
From: "Wesley W. Terpstra"
This is used of the HiFive Unleashed development board, and follows the
pattern of similar ISSI devices already listed.
Signed-off-by: Wesley W. Terpstra
Signed-off-by: Palmer Dabbelt
---
drivers/mtd/spi-nor/spi-nor.c | 2 ++
1 file changed, 2 insertion
error when writing SR_TB to these
chips, as it aliases with this extra protection bit in the status
register. It looks like that's always conditional on SNOR_F_HAS_SR_TB,
so at least what's there is safe.
Signed-off-by: Wesley W. Terpstra
Signed-off-by: Palmer Dabbelt
---
drivers/mtd/spi-nor
From: "Wesley W. Terpstra"
This is used of the HiFive Unleashed development board, and follows the
pattern of similar ISSI devices already listed.
Signed-off-by: Wesley W. Terpstra
Signed-off-by: Palmer Dabbelt
---
drivers/mtd/spi-nor/spi-nor.c | 2 ++
1 file changed, 2 insertion
error when writing SR_TB to these
chips, as it aliases with this extra protection bit in the status
register. It looks like that's always conditional on SNOR_F_HAS_SR_TB,
so at least what's there is safe.
Signed-off-by: Wesley W. Terpstra
Signed-off-by: Palmer Dabbelt
---
drivers/mtd/spi-nor
This adds support for the is25wp256 flash chip, which is on our HiFive
Unleashed board. Additionally it adds support for ISSI's special
unlocking scheme, which we need to unlock block protection on the whole
chip.
Changes since v1 [<20180804014947.24601-1-pal...@sifive.com>]:
* There are now two
This adds support for the is25wp256 flash chip, which is on our HiFive
Unleashed board. Additionally it adds support for ISSI's special
unlocking scheme, which we need to unlock block protection on the whole
chip.
Changes since v1 [<20180804014947.24601-1-pal...@sifive.com>]:
* There are now two
On Mon, 06 Aug 2018 14:00:53 PDT (-0700), rdun...@infradead.org wrote:
On 08/06/2018 01:42 PM, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include guard we end up
On Mon, 06 Aug 2018 14:05:11 PDT (-0700), marek.va...@gmail.com wrote:
On 08/06/2018 10:58 PM, Palmer Dabbelt wrote:
On Sat, 04 Aug 2018 02:27:54 PDT (-0700), marek.va...@gmail.com wrote:
On 08/04/2018 03:49 AM, Palmer Dabbelt wrote:
From: "Wesley W. Terpstra"
This is used of
On Mon, 06 Aug 2018 14:00:53 PDT (-0700), rdun...@infradead.org wrote:
On 08/06/2018 01:42 PM, Palmer Dabbelt wrote:
This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables. With
a global include guard we end up
On Mon, 06 Aug 2018 14:05:11 PDT (-0700), marek.va...@gmail.com wrote:
On 08/06/2018 10:58 PM, Palmer Dabbelt wrote:
On Sat, 04 Aug 2018 02:27:54 PDT (-0700), marek.va...@gmail.com wrote:
On 08/04/2018 03:49 AM, Palmer Dabbelt wrote:
From: "Wesley W. Terpstra"
This is used of
On Sun, 05 Aug 2018 14:37:05 PDT (-0700), Stephen Rothwell wrote:
Hi Palmer,
Commit
bce17edfe6af ("fixup: ". " in PLIC docs")
is missing a Signed-off-by from its author and committer.
Oh, sorry about that. It should be gone, it was just meant as a review
comment.
On Sun, 05 Aug 2018 14:37:05 PDT (-0700), Stephen Rothwell wrote:
Hi Palmer,
Commit
bce17edfe6af ("fixup: ". " in PLIC docs")
is missing a Signed-off-by from its author and committer.
Oh, sorry about that. It should be gone, it was just meant as a review
comment.
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
is the canonical way to do it.
Cc: Marcus Comstedt
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/unistd.h| 5 +
arch/riscv/include/uapi/asm/syscalls.h | 15 +--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv
On Sat, 04 Aug 2018 02:27:54 PDT (-0700), marek.va...@gmail.com wrote:
On 08/04/2018 03:49 AM, Palmer Dabbelt wrote:
From: "Wesley W. Terpstra"
This is used of the HiFive Unleashed development board.
Signed-off-by: Wesley W. Terpstra
Signed-off-by: Palmer Dabbelt
---
drivers/m
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