From: Christophe Branchereau
In case a poll for RUP times out, we might be left with some IRQ flags
that should be cleared before the next power on.
Signed-off-by: Christophe Branchereau
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/jz4770.c | 6 +++---
1 file changed, 3 insertions(+), 3
Use regmap_{set,clear}_bits instead of regmap_update_bits, when
applicable.
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/jz4725b.c | 26 ++--
sound/soc/codecs/jz4740.c | 20 +++--
sound/soc/codecs/jz4770.c | 85 +-
3 files changed, 55
From: Christophe Branchereau
When using cap-coupled outputs, the RUP/RDO can take much longer than
the 100ms timeout we used to have. Increase that timeout to one second.
Signed-off-by: Christophe Branchereau
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/jz4770.c | 8
1 file
Hi Arnd,
Le ven. 4 déc. 2020 à 15:14, Arnd Bergmann a écrit
:
On Fri, Dec 4, 2020 at 11:02 AM Ulf Hansson
wrote:
On Thu, 3 Dec 2020 at 23:29, Arnd Bergmann wrote:
> -#ifdef CONFIG_PM
> static void msdc_save_reg(struct msdc_host *host)
Shouldn't msdc_save|restore_reg() be turned
Hi,
Le ven. 4 déc. 2020 à 15:14, Arnd Bergmann a écrit
:
On Fri, Dec 4, 2020 at 11:02 AM Ulf Hansson
wrote:
On Thu, 3 Dec 2020 at 23:29, Arnd Bergmann wrote:
> -#ifdef CONFIG_PM
> static void msdc_save_reg(struct msdc_host *host)
Shouldn't msdc_save|restore_reg() be turned into
off-by: Zhang Changzhong
Acked-by: Paul Cercueil
Cheers,
-Paul
---
drivers/memory/jz4780-nemc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/memory/jz4780-nemc.c
b/drivers/memory/jz4780-nemc.c
index 3ec5cb0..465ea92 100644
--- a/drivers/memory/jz4780-nemc.c
+++ b/drivers/
Hi Krzysztof,
Le ven. 4 déc. 2020 à 10:18, Krzysztof Kozlowski a
écrit :
On Mon, Nov 16, 2020 at 07:54:03PM +, Paul Cercueil wrote:
Hi Krzysztof,
Le lun. 16 nov. 2020 à 18:53, Krzysztof Kozlowski
a écrit
:
> The Ingenic DRM uses Common Clock Framework thus it cannot be
bu
y: Chuhong Yuan
Acked-by: Paul Cercueil
Cheers,
-Paul
---
sound/soc/jz4740/jz4740-i2s.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/soc/jz4740/jz4740-i2s.c
b/sound/soc/jz4740/jz4740-i2s.c
index c7bd20104b20..0793e284d0e7 100644
--- a/sound/soc/jz4740/jz4740-i2s.c
+++ b
Hi,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Stephen: this patch can be merged independently of the other
Hi,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
Add CIM, AIC, DMIC clocks bindings for the X1000 SoC, and CIM, AIC,
DMIC, I2S clocks for the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
include/dt-bindings/clock
Hi Zhou,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
Add CIM, AIC, DMIC clocks for the X1000 SoC, and CIM, AIC, DMIC, I2S
clocks for the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/x1000-cgu.c | 19
drivers/clk/ingenic/x1830-cgu.c |
Hi Zhou,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
1.Fill unused bits in parents in jz4780-cgu.c, x1000-cgu.c,
and x1830-cgu.c, these bits should be filled with -1.
2.Reformat code, add missing blank lines, remove unnecessary
tabs, and align code.
Signed-off-by: 周琰杰 (Zhou
Le lun. 30 nov. 2020 à 13:18, Rob Herring a
écrit :
On Mon, Nov 30, 2020 at 12:39 PM Paul Cercueil
wrote:
Hi Rob,
Le lun. 30 nov. 2020 à 7:32, Rob Herring a
écrit
:
> On Mon, Nov 2, 2020 at 3:19 AM Paul Cercueil
> wrote:
>>
>>
>>
>> Le
Hi Rob,
Le lun. 30 nov. 2020 à 7:32, Rob Herring a écrit
:
On Mon, Nov 2, 2020 at 3:19 AM Paul Cercueil
wrote:
Le dim. 1 nov. 2020 à 13:29, Sam Ravnborg a
écrit :
> On Sun, Nov 01, 2020 at 09:31:48AM +0000, Paul Cercueil wrote:
>> The Asia Better Technology (ABT) Y030XX0
Call drm_mode_config_helper_suspend() and
drm_mode_config_helper_resume() on suspend and resume, respectively.
This makes sure that the display stack is properly disabled when the
hardware is put to sleep.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 20
Le sam. 28 nov. 2020 à 19:58, Sam Ravnborg a écrit
:
Hi Paul.
On Sat, Nov 28, 2020 at 05:16:06PM +, Paul Cercueil wrote:
Call drm_mode_config_helper_suspend() and
drm_mode_config_helper_resume() on suspend and resume, respectively.
This makes sure that the display stack
for the ingenic_tcu_get_clock()
function.
One 'ta' too many ;)
Fixes: f19d838d08fc (clocksource/drivers/ingenic: Add high resolution
timer support for SMP/SMT)
Reported-by: kernel test robot
Signed-off-by: Daniel Lezcano
With the above fixed:
Reviewed-by: Paul Cercueil
Cheers,
-Paul
Hi Suman,
Le ven. 20 nov. 2020 à 17:06, Suman Anna a écrit :
Hi Paul,
On 11/20/20 4:37 PM, Mathieu Poirier wrote:
Hi Paul,
On Sun, Nov 15, 2020 at 11:50:56AM +, Paul Cercueil wrote:
Until now the remoteproc core would always default to trying to
boot the
remote processor
Hi Mathieu,
Le ven. 20 nov. 2020 à 15:37, Mathieu Poirier
a écrit :
Hi Paul,
On Sun, Nov 15, 2020 at 11:50:56AM +, Paul Cercueil wrote:
Until now the remoteproc core would always default to trying to
boot the
remote processor at startup. The various remoteproc drivers could
however
Add support for 24-bit panels that are connected through a 8-bit bus and
use delta-RGB, which means a RGB pixel ordering on odd lines, and a GBR
pixel ordering on even lines.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 7 ++-
drivers/gpu/drm/ingenic/ingenic
-280M
and RG-280V handheld gaming consoles.
Cheers,
-Paul
Paul Cercueil (3):
drm/ingenic: Compute timings according to adjusted_mode->crtc_*
drm/ingenic: Properly compute timings when using a 3x8-bit panel
drm/ingenic: Add support for serial 8-bit delta-RGB panels
drivers/gpu/drm/inge
The LCD controller expects timing values in dot-clock ticks, which is 3x
the timing values in pixels when using a 3x8-bit display; but it will
count the display area size in pixels either way. Go figure.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 15
The adjusted_mode->crtc_* fields contain the values adjusted for the
hardware, and are the ones that should be written to the registers.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
d
Le mer. 18 nov. 2020 à 16:25, Vinod Koul a écrit :
On 10-11-20, 08:54, Paul Cercueil wrote:
Hi Zhou,
Le sam. 7 nov. 2020 à 20:20, 周琰杰 (Zhou Yanjie)
a écrit :
> Add the dmaengine bindings for the JZ4775 SoC and the X2000 SoC
from
> Ingenic.
>
> 周琰杰 (Zhou Yanjie)
Acked-by: Paul Cercueil
Cheers,
-Paul
---
drivers/gpu/drm/ingenic/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/ingenic/Kconfig
b/drivers/gpu/drm/ingenic/Kconfig
index 477d5387e43e..3b57f8be007c 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu
to load.
Add a 'auto_boot' module parameter that instructs the remoteproc whether
or not it should auto-boot the remote processor, which will default to
"true" to respect the previous behaviour.
Signed-off-by: Paul Cercueil
---
drivers/remoteproc/remoteproc_core.c | 7 ++-
1 file
Hi Zhou,
Le mar. 10 nov. 2020 à 14:31, Zhou Yanjie
a écrit :
Hi Paul,
On 2020/11/10 上午7:37, Paul Cercueil wrote:
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU
Le mar. 10 nov. 2020 à 9:56, Sam Ravnborg a écrit :
Hi Paul,
On Tue, Nov 10, 2020 at 08:50:22AM +, Paul Cercueil wrote:
Hi,
Le sam. 7 nov. 2020 à 20:33, Sam Ravnborg a
écrit :
> Hi Paul.
>
> On Thu, Nov 05, 2020 at 08:39:05AM +0000, Paul Cercueil wrote:
>
Hi Zhou,
Le sam. 7 nov. 2020 à 20:20, 周琰杰 (Zhou Yanjie)
a écrit :
Add the dmaengine bindings for the JZ4775 SoC and the X2000 SoC from
Ingenic.
周琰杰 (Zhou Yanjie) (2):
dt-bindings: dmaengine: Add JZ4775 bindings.
dt-bindings: dmaengine: Add X2000 bindings.
Hi,
Le sam. 7 nov. 2020 à 20:33, Sam Ravnborg a écrit :
Hi Paul.
On Thu, Nov 05, 2020 at 08:39:05AM +, Paul Cercueil wrote:
Increase the scaled image's theorical width/height until we find a
configuration that has valid scaling coefficients, up to 102% of the
screen's resolution
level and
SoC specific code")
Signed-off-by: Yu Kuai
Acked-by: Paul Cercueil
Thanks,
-Paul
---
drivers/mtd/nand/raw/ingenic/ingenic_ecc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
b/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
index 8e
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
Hi Zhou,
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
Hi,
Le dim. 8 nov. 2020 à 0:36, Rikard Falkeborn
a écrit :
The only usage of ingenic_rproc_ops is to pass its address to
devm_rproc_alloc(), which accepts a const pointer. Make it const to
allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn
Acked-by: Paul
are not modified.
This algorithm was already in place but would not try to go above the
screen's resolution, and as a result would only work if the CRTC_W /
CRTC_H were smaller than the screen resolution. It will now try until it
reaches 102% of the screen's resolution.
Signed-off-by: Paul Cercueil
Hi Artur,
Le mer. 4 nov. 2020 à 23:29, Artur Rojek a
écrit :
Hi Paul,
On 2020-11-04 20:28, Paul Cercueil wrote:
The reference voltage for the battery is clearly marked as 1.2V in
the
programming manual. With this fixed, the battery channel now returns
correct values.
Fixes: a515d6488505
The reference voltage for the battery is clearly marked as 1.2V in the
programming manual. With this fixed, the battery channel now returns
correct values.
Fixes: a515d6488505 ("IIO: Ingenic JZ47xx: Add support for JZ4770 SoC ADC.")
Cc:
Signed-off-by: Paul Cercueil
---
drivers/iio/a
f-extracting targets scenarios
mips: boot: add support for self-extracting FIT images (vmlinuz.itb)
It doesn't break anything on my end, so:
Acked-by: Paul Cercueil
for the series.
Why vmlinuz.itb and not vmlinuz.fit or vmlinuz.uhi? Is the .itb suffix
already a thing?
Cheers,
-Paul
Hi,
Le dim. 1 nov. 2020 à 6:09, t...@redhat.com a écrit :
From: Tom Rix
A semicolon is not needed after a switch statement.
Signed-off-by: Tom Rix
Acked-by: Paul Cercueil
Cheers,
-Paul
---
drivers/power/supply/ingenic-battery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Hi,
Le mer. 4 nov. 2020 à 7:11, Xu Wang a écrit :
Because clk_enable and clk_disable already checked NULL clock
parameter,
so the additional checks are unnecessary, just remove them.
Signed-off-by: Xu Wang
Reviewed-by: Paul Cercueil
Cheers,
-Paul
---
drivers/clk/ingenic/tcu.c | 6
.
Fixes: b96952f498db ("IIO: Ingenic JZ47xx: Add touchscreen mode.")
Cc:
Signed-off-by: Paul Cercueil
---
drivers/iio/adc/ingenic-adc.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ing
Hi Christoph,
Le mar. 3 nov. 2020 à 18:50, Christoph Hellwig a
écrit :
On Mon, Nov 02, 2020 at 10:06:49PM +, Paul Cercueil wrote:
This function can be used by drivers that need to mmap dumb buffers
created with non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers
Hi Daniel,
Le mar. 3 nov. 2020 à 11:17, Daniel Vetter a écrit :
On Mon, Nov 02, 2020 at 10:06:51PM +, Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
possible
to specify that we want GEM buffers backed by non-coherent memory.
This dramatically
).
Leave it disabled by default, since it is specific to one use-case
(software rendering).
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 58 +--
drivers/gpu/drm/ingenic/ingenic-drm.h | 4 ++
drivers/gpu/drm/ingenic/ingenic-ipu.c | 12
rt for non-coherent GEM buffers to the
ingenic-drm driver. The functionality is enabled through a module
parameter, and is disabled by default.
Cheers,
-Paul
Paul Cercueil (5):
drm: Add and export function drm_gem_cma_create_noncoherent
drm: Add and export function drm_gem_cma_dumb_create_noncoherent
This function can be used by drivers that use damage clips and have
CMA GEM objects backed by non-coherent memory. Calling this function
in a plane's .atomic_update ensures that all the data in the backing
memory have been written to RAM.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm
This function can be used by drivers to create dumb buffers with
non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 37 +---
include/drm/drm_gem_cma_helper.h | 4 +++
2 files changed, 37 insertions(+), 4 deletions
This function can be used by drivers that need to create a GEM object
with non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 71 +---
include/drm/drm_gem_cma_helper.h | 2 +
2 files changed, 56 insertions(+), 17
This function can be used by drivers that need to mmap dumb buffers
created with non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 39
include/drm/drm_gem_cma_helper.h | 2 ++
2 files changed, 41 insertions
Le dim. 1 nov. 2020 à 13:29, Sam Ravnborg a écrit :
On Sun, Nov 01, 2020 at 09:31:48AM +, Paul Cercueil wrote:
The Asia Better Technology (ABT) Y030XX067A panel is a 3.0" 320x480
24-bit IPS LCD panel. Its particularity is that it has non-square
pixels
(as it is 4:3 for a resol
Add prefix for ShenZhen Asia Better Technology Ltd.
Signed-off-by: Paul Cercueil
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor
Add media bus format for 24-bit panels that expect their pixel data to
be sent serially on a 8-bit bus, in RGB ordering on odd lines, and in
GBR ordering on even lines (aka delta-RGB).
Signed-off-by: Paul Cercueil
---
include/uapi/linux/media-bus-format.h | 3 ++-
1 file changed, 2 insertions
d-off-by: Paul Cercueil
---
.../display/panel/abt,y030xx067a.yaml | 54 +++
1 file changed, 54 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/abt,y030xx067a.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/abt,y030xx067a
, GRB on even lines).
Patch #1 adds the abt,* vendor prefix.
Patch #2 adds the abt,y030xx067a panel binding documentation.
Patch #3 adds the MEDIA_BUS_FMT_RGB888_3X8_DELTA media bus format.
Patch #4 adds the driver itself.
Cheers,
-Paul
Paul Cercueil (4):
dt-bindings: vendor-prefixes: Add abt vendor p
Add support for the ShenZhen Asia Better Technology Ltd. Y030XX067A 3.0"
320x480 IPS panel.
This panel can be found in the YLM RG-280M, RG-300 and RG-99 handheld
gaming consoles. While being 320x480, it is actually a horizontal 4:3
panel with non-square pixels.
Signed-off-by: Paul Cer
tforms. However,
we can't do that without breaking Device Tree ABI, so in that case we
have no choice but to have two groups containing the same pins.
Signed-off-by: Paul Cercueil
---
drivers/pinctrl/pinctrl-ingenic.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/dr
Hi Linus,
A cleanup patch to get rid of a lot of const data, and a patch to add
the lcd-8bit group for JZ4770 SoCs.
Based on your latest for-next branch, since there are already some
commits on pinctrl-ingenic.c there that aren't on v5.10-rc1.
Cheers,
-Paul
Paul Cercueil (2):
pinctrl
ces the number of pin function tables needed, and
drops .data usage by about 2 KiB. Additionally, the few pin function
tables that are still around now contain u8 instead of int, since the
largest number that will be stored is 3.
Signed-off-by: Paul Cercueil
---
drivers/pinctrl/pinctrl-ingenic.c | 1
r hdrc glue")
Cc: sta...@vger.kernel.org # v4.9
Signed-off-by: Paul Cercueil
Reviewed-by: Tony Lindgren
Tested-by: Tony Lindgren
---
drivers/usb/musb/musb_core.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/musb/musb_core
Remove unused-but-set devctl variable.
Signed-off-by: Paul Cercueil
---
drivers/usb/musb/musbhsdma.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 0aacfc8be5a1..7acd1635850d 100644
--- a/drivers/usb/musb/musbhsdma.c
-check on the 'req' pointer
instead.
Signed-off-by: Paul Cercueil
Suggested-by: Maarten ter Huurne
---
drivers/usb/musb/musb_gadget.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index f62ffaede1ab..ef374d4dd94a
Hi Bin,
The first two patches of this series have already been sent before but
were never merged, hence the RESEND. This is not really a V2 as nothing
changed there.
Patches 3/4 are new.
Cheers,
-Paul
Paul Cercueil (4):
usb: musb: Fix runtime PM race in musb_queue_resume_work
usb: musb
If you pass a string that is not terminated with a carriage return to
dev_err(), it will eventually be printed with a carriage return, but
not right away, since the kernel will wait for a pr_cont().
Signed-off-by: Paul Cercueil
---
drivers/usb/musb/jz4740.c | 14 +++---
1 file changed
s/boot/dts/ingenic/jz4740.dtsi | 2 +-
arch/mips/boot/dts/ingenic/jz4770.dtsi | 2 +-
For jz4740.dtsi and jz4770.dtsi:
Acked-by: Paul Cercueil
Cheers,
-Paul
arch/mips/boot/dts/mti/sead3.dts | 2 +-
arch/mips/boot/dts/ralink/mt7628a.dtsi | 2 +-
arch/powerp
Hi Stephen,
Le lun. 12 oct. 2020 à 15:24, Stephen Rothwell
a écrit :
Hi all,
On Thu, 8 Oct 2020 15:42:02 +1100 Stephen Rothwell
wrote:
On Thu, 8 Oct 2020 14:09:03 +1100 Stephen Rothwell
wrote:
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig)
pport for Ingenic SoCs")
Signed-off-by: Paul Cercueil
---
arch/mips/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f52fa211a4cf..29bad5bd3e70 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -103,7 +103,6 @@ config MACH_INGENIC
Le lun. 12 oct. 2020 à 16:10, Daniel Vetter a écrit
:
On Mon, Oct 12, 2020 at 12:25:09PM +0200, Paul Cercueil wrote:
Fix a badly reverted commit. The revert commit was cherry-picked
from
drm-misc-next to drm-misc-next-fixes, and in the process some
unrelated
code was added.
Fixes
Hi Guenter,
Le lun. 12 oct. 2020 à 7:33, Guenter Roeck a
écrit :
On Sun, Sep 06, 2020 at 09:29:31PM +0200, Paul Cercueil wrote:
Add support for Ingenic SoCs in arch/mips/generic/.
The Kconfig changes are here to ensure that it is possible to
compile
either a generic kernel that supports
Fix a badly reverted commit. The revert commit was cherry-picked from
drm-misc-next to drm-misc-next-fixes, and in the process some unrelated
code was added.
Fixes: a3fb64c00d44 "Revert "gpu/drm: ingenic: Add option to mmap GEM buffers
cached""
Signed-off-by: Paul Cercueil
Hi Stephen,
Le lun. 12 oct. 2020 à 15:24, Stephen Rothwell
a écrit :
Hi all,
On Thu, 8 Oct 2020 15:42:02 +1100 Stephen Rothwell
wrote:
On Thu, 8 Oct 2020 14:09:03 +1100 Stephen Rothwell
wrote:
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig)
Hi Linus, Zhou,
The first patch is bogus. Half of the SSI pins are wrong (GPIO chip D/E
start at 0x60/0x80 respectively).
Sorry for not catching that before.
-Paul
Le mar. 29 sept. 2020 à 14:48, Linus Walleij
a écrit :
On Sun, Sep 13, 2020 at 8:59 AM 周琰杰 (Zhou Yanjie)
wrote:
1.Add
The values for the SSI pins on GPIO chips D and E were off by 0x20.
Fixes: d3ef8c6b2286 ("pinctrl: Ingenic: Add SSI pins support for JZ4770 and
JZ4780.")
Signed-off-by: Paul Cercueil
Reported-by: Artur Rojek
---
drivers/pinctrl/pinctrl-ingenic.c | 72 +++--
Hi,
Le lun. 5 oct. 2020 à 16:05, Daniel Vetter a écrit :
On Mon, Oct 05, 2020 at 11:01:50PM +1100, Stephen Rothwell wrote:
Hi Paul,
On Sun, 04 Oct 2020 22:11:23 +0200 Paul Cercueil
wrote:
>
> Pushed to drm-misc-next with the changelog fix, thanks.
>
> Stephen:
> Now
Hi,
Le mer. 23 sept. 2020 à 19:02, Jiaxun Yang a
écrit :
Loongson64C and Loongson64G have extimer feature, which is a
timer sharing Cause.TI with cevt-r4k (named intimer).
To ensure the cevt-r4k's usability, we need to add a callback for
clock device to switch intimer.
Signed-off-by: Jiaxun
Hi,
Le dim. 4 oct. 2020 à 21:59, Sam Ravnborg a écrit :
Hi Paul.
On Sun, Oct 04, 2020 at 04:17:58PM +0200, Paul Cercueil wrote:
This reverts commit 37054fc81443cc6a8c3a38395f384412b8373d82.
In the changelog please refer to commits like this:
37054fc81443 ("gpu/drm: ingenic: Add o
.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 114 +-
drivers/gpu/drm/ingenic/ingenic-drm.h | 4 -
drivers/gpu/drm/ingenic/ingenic-ipu.c | 12 +--
3 files changed, 4 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/ingenic
el.org # v4.0
Signed-off-by: Paul Cercueil
Reported-by: Artur Rojek
Tested-by: Artur Rojek
---
drivers/dma/dma-jz4780.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index 8beed91428bd..a608efaa435f 100644
--- a/dr
dma_alloc_noncoherent() if non-coherent memory is what we want.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 48 ++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm
Add and export the function drm_gem_cma_create_noalloc(), which is just
__drm_gem_cma_create() renamed.
This function can be used by drivers that need to create a GEM object
without allocating the backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 11
The DMA API changed at the same time commit 37054fc81443 ("gpu/drm:
ingenic: Add option to mmap GEM buffers cached") was added. Rework the
code to work with the new DMA API.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 24 +++
1 fi
Le mer. 30 sept. 2020 à 18:40, Christoph Hellwig a écrit
:
On Wed, Sep 30, 2020 at 06:39:18PM +0200, Paul Cercueil wrote:
dma_alloc_pages gives you cached memory, so you can't just use an
uncached protection for the userspace mmap here. If you want
uncached
memory you need to use
Le mer. 30 sept. 2020 à 18:11, Christoph Hellwig a écrit
:
On Wed, Sep 30, 2020 at 03:33:13PM +0200, Paul Cercueil wrote:
One thing missing for remap_pfn_range(), I have no alternative for
this:
vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot,
DMA_ATTR_NON_CONSISTENT);
Hi Christoph,
Le mer. 30 sept. 2020 à 11:02, Christoph Hellwig a écrit
:
On Mon, Sep 28, 2020 at 03:31:28PM +0200, Paul Cercueil wrote:
It's allocated with dma_alloc_wc, but then it's only accessed as
non-coherent.
Anyway, for the time being I guess you could revert 37054fc81443.
But I
-off-by: Paul Cercueil
---
kernel/dma/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig
index 847a9d1fa634..f15e782e19ca 100644
--- a/kernel/dma/Kconfig
+++ b/kernel/dma/Kconfig
@@ -162,7 +162,7 @@ endchoice
config CMA_ALIGNMENT
Le lun. 28 sept. 2020 à 14:10, Christoph Hellwig a écrit
:
On Mon, Sep 28, 2020 at 01:46:55PM +0200, Paul Cercueil wrote:
dma_mmap_attrs can only be used on allocations from dma_mmap_attrs
with
the same attrs. As there is no allocation using
DMA_ATTR_NON_CONSISTENT
in the drm core
Le lun. 28 sept. 2020 à 13:34, Christoph Hellwig a écrit
:
On Mon, Sep 28, 2020 at 12:15:56PM +0200, Paul Cercueil wrote:
Hi Christoph,
Le lun. 28 sept. 2020 à 8:04, Christoph Hellwig a
écrit :
On Mon, Sep 28, 2020 at 01:54:05PM +1000, Stephen Rothwell wrote:
Hi all,
After
Hi Christoph,
Le lun. 28 sept. 2020 à 8:04, Christoph Hellwig a écrit :
On Mon, Sep 28, 2020 at 01:54:05PM +1000, Stephen Rothwell wrote:
Hi all,
After merging the drm tree, today's linux-next build (x86_64
allmodconfig)
failed like this:
The driver needs to switch do
Hi,
Le lun. 17 août 2020 à 13:59, Tony Lindgren a
écrit :
* Paul Cercueil [200809 12:54]:
musb_queue_resume_work() would call the provided callback if the
runtime
PM status was 'active'. Otherwise, it would enqueue the request if
the
hardware was still suspended (musb
Le dim. 27 sept. 2020 à 22:27, Sam Ravnborg a
écrit :
On Sun, Sep 27, 2020 at 09:36:45PM +0200, Paul Cercueil wrote:
On JZ4725B and newer, the F0 plane supports paletted 8bpp with a
256-entry palette. Add support for it.
v3: Only accept a full 256-entry palette.
Signed-off-by: Paul
On JZ4725B and newer, the F0 plane supports paletted 8bpp with a
256-entry palette. Add support for it.
v3: Only accept a full 256-entry palette.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 66 +--
1 file changed, 62 insertions(+), 4
mplete 256-entry palette is accepted.
Cheers,
-Paul
Paul Cercueil (1):
drm/ingenic: Add support for paletted 8bpp
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 66 +--
1 file changed, 62 insertions(+), 4 deletions(-)
--
2.28.0
Hi,
Le sam. 26 sept. 2020 à 20:25, Sam Ravnborg a
écrit :
Hi Paul.
On Sat, Sep 26, 2020 at 07:04:54PM +0200, Paul Cercueil wrote:
Hi,
This is a V2 of my small patchset "Small improvements to
ingenic-drm"
that I sent about two weeks ago. In that time, I worked on new
improv
in JZ4725B, 30bpp was added in
JZ4770.
Prepare the inclusion of paletted 8bpp, 24bpp and 30bpp support by
having separate pixel format lists for F0 and F1 planes.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 57 +++
1 file changed, 47
Starting from the JZ4760 SoC, the primary and overlay planes support
30-bit pixel modes (10 bits per color component). Add support for these
in the ingenic-drm driver.
Signed-off-by: Paul Cercueil
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 8
drivers/gpu
On JZ4725B and newer, the F0 plane supports paletted 8bpp with a
256-entry palette. Add support for it.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 60 +--
1 file changed, 56 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/ingenic
Starting from the JZ4725B SoC, the primary and overlay planes support
24-bit pixel modes (8 bits per color component, without dummy byte).
Add support for these in the ingenic-drm driver.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 8
drivers/gpu/drm
fine provided the kernel configuration is sane.
Signed-off-by: Paul Cercueil
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic
, for an unknown reason.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 51 +--
1 file changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index d34e76f5f57d
ed, I kept your
acked-by on them, please tell me if that's OK.
Cheers,
-Paul
Paul Cercueil (7):
drm/ingenic: Reset pixclock rate when parent clock rate changes
drm/ingenic: Add support for reserved memory
drm/ingenic: Alloc F0 and F1 DMA descriptors at once
drm/ingenic: Support handling diffe
Signed-off-by: Paul Cercueil
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 937d080f5d06
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