[PATCH v9b 10/14] ARM: tegra: Define Tegra114 CAR binding

10/14] ARM: tegra: Define Tegra114 CAR binding' (http://www.spinics.net/lists/linux-tegra/msg10910.html). The rest of the series is not affected. Thanks in advance, Peter. Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra114-car.txt | 303

Re: [PATCH v9 00/14] Tegra114 clockframework

On Thu, Apr 04, 2013 at 01:23:05AM +0200, Stephen Warren wrote: > On 04/03/2013 12:27 PM, Stephen Warren wrote: > > On 04/03/2013 11:52 AM, Stephen Warren wrote: > >> On 04/03/2013 08:40 AM, Peter De Schrijver wrote: > >>> This is the nineth version of the Tegra114

[PATCH v9 14/14] clk: tegra: Remove forced clk_enable of uartd

The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/

[PATCH v9 13/14] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114-dalmore.dts |1 - arch/arm

[PATCH v9 13/14] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114-dalmore.dts |1 - arch/arm

[PATCH v9 12/14] clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |1 + drivers/clk/tegra/clk.h |6 ++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 70b7a47..923ca7e 100644 --- a/drivers/clk/tegra/clk.c +++ b

[PATCH v9 09/14] clk: tegra: Workaround for Tegra114 MSENC problem

Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c |9 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c

[PATCH v9 10/14] ARM: tegra: Define Tegra114 CAR binding

The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra114-car.txt | 317 1 files changed, 317 insertions(+), 0 deletions(-) create mode 100644

[PATCH v9 08/14] clk: tegra: Add flags to tegra_clk_periph()

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph.c | 11 ++- drivers/clk/tegra/clk-tegra20.c |2 +- drivers/clk

[PATCH v9 02/14] clk: tegra: Refactor PLL programming code

* Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver --- drivers/clk/tegra

[PATCH v9 07/14] clk: tegra: Add new fields and PLL types for Tegra114

Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 839 +++ drivers/clk/tegra/clk.h | 50 +++- 2 files changed, 888

[PATCH v9 06/14] clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c |6 +++--- drivers/clk/tegra/clk-tegra20.c | 20

[PATCH v9 05/14] clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 38 -- drivers/clk/tegra/clk-tegra20.c |

[PATCH v9 04/14] clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c |5 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegr

[PATCH v9 03/14] clk: tegra: Add TEGRA_PLL_BYPASS flag

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 12 drivers/clk/tegra/clk.h |2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a

[PATCH v9 01/14] clk: tegra: provide dummy cpu car ops

tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver

[PATCH v9 00/14] Tegra114 clockframework

om v1: * Remove SATA and PCIe clocks. They don't appear in the internal TRM, so I assume they don't exist. * Rebase on top of Hiroshi's latest Tegra114 patches * More generic mux code. This is necessary for the AHUB and DAM clocks. Peter De Schrijver (14): clk: tegra: provide

Re: [PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote: > On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote: > > The device tree binding models Tegra114 CAR (Clock And Reset) as a single > > monolithic clock provider. > > > > Signed

Re: [PATCH 1/1] clk: Add notifier support in clk_prepare/clk_unprepare

On Thu, Mar 28, 2013 at 11:01:09PM +0100, Mike Turquette wrote: > Quoting Colin Cross (2013-03-21 17:06:25) > > On Thu, Mar 21, 2013 at 3:36 PM, Mike Turquette > > wrote: > > > To my knowledge, devfreq performs one task: implements an algorithm > > > (typically one that loops/polls) and applies t

Re: [PATCH] clk: tegra: Don't enable PLLs during early boot

On Fri, Mar 22, 2013 at 04:48:11PM +0100, Stephen Warren wrote: > On 03/22/2013 05:54 AM, Peter De Schrijver wrote: > > The PLL code relies on udelay() which is not available when CCF is > > initialized. Hence we can't enable any PLL during this phase. > > > > S

Re: [PATCH v8 00/14] Tegra114 clockframework

On Fri, Mar 22, 2013 at 01:39:17PM +0100, Peter De Schrijver wrote: > This is the eight version of the Tegra114 clockframework. It is based on the > next-20130320-fixed branch of > git://nv-tegra.nvidia.com/user/swarren/linux-2.6.git, > http://patchwork.ozlabs.org/patch/229972

[PATCH v8 14/14] clk: tegra: Remove forced clk_enable of uartd

The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/

[PATCH v8 13/14] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114-dalmore.dts |1 - arch/arm

[PATCH v8 12/14] clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |1 + drivers/clk/tegra/clk.h |7 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index a6f2fa6..2a8e424 100644 --- a/drivers/clk/tegra/clk.c +++ b

[PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra114-car.txt | 317 1 files changed, 317 insertions(+), 0 deletions(-) create mode 100644

[PATCH v8 09/14] clk: tegra: Workaround for Tegra114 MSENC problem

Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c |9 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c

[PATCH v8 08/14] clk: tegra: Add flags to tegra_clk_periph()

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph.c | 11 ++- drivers/clk/tegra/clk-tegra20.c |2 +- drivers/clk

[PATCH v8 07/14] clk: tegra: Add new fields and PLL types for Tegra114

Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 839 +++ drivers/clk/tegra/clk.h | 50 +++- 2 files changed, 888

[PATCH v8 06/14] clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c |6 +++--- drivers/clk/tegra/clk-tegra20.c | 20

[PATCH v8 05/14] clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 38 -- drivers/clk/tegra/clk-tegra20.c |

[PATCH v8 03/14] clk: tegra: Add TEGRA_PLL_BYPASS flag

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 12 drivers/clk/tegra/clk.h |2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a

[PATCH v8 04/14] clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c |5 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegr

[PATCH v8 02/14] clk: tegra: Refactor PLL programming code

* Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver --- drivers/clk/tegra

[PATCH v8 01/14] clk: tegra: provide dummy cpu car ops

tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver

[PATCH v8 00/14] Tegra114 clockframework

ist. * Rebase on top of Hiroshi's latest Tegra114 patches * More generic mux code. This is necessary for the AHUB and DAM clocks. Peter De Schrijver (14): clk: tegra: provide dummy cpu car ops clk: tegra: Refactor PLL programming code clk: tegra: Add TEGRA_PLL_BYPASS flag clk: teg

Re: [PATCH REPOST v2] clk: add table lookup to mux

On Fri, Mar 22, 2013 at 01:07:53PM +0100, Peter De Schrijver wrote: > Add a table lookup feature to the mux clock. Also allow arbitrary masks > instead of the width. This will be used by some clocks on Tegra114. Also > adapt the tegra periph clk because it uses struct clk_mux directly. &g

Re: [PATCH] clk: tegra: Don't enable PLLs during early boot

On Fri, Mar 22, 2013 at 01:02:33PM +0100, Peter De Schrijver wrote: > The PLL code relies on udelay() which is not available when CCF is > initialized. Hence we can't enable any PLL during this phase. > > Signed-off-by: Peter De Schrijver > Sorry for accidently reposting t

[PATCH REPOST v2] clk: add table lookup to mux

Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver -- Mike, As you can see, I updated the macro in

[PATCH] clk: tegra: Don't enable PLLs during early boot

The PLL code relies on udelay() which is not available when CCF is initialized. Hence we can't enable any PLL during this phase. Signed-off-by: Peter De Schrijver -- Stephen, Can you confirm this is ok for the audio drivers? We used to be lucky that this has worked up to now, but I

[PATCH] clk: tegra: Don't enable PLLs during early boot

The PLL code relies on udelay() which is not available when CCF is initialized. Hence we can't enable any PLL during this phase. Signed-off-by: Peter De Schrijver -- Stephen, Can you confirm this is ok for the audio drivers? We used to be lucky that this has worked up to now, but I

[PATCH] clk: tegra: Don't enable PLLs during early boot

The PLL code relies on udelay() which is not available when CCF is initialized. Hence we can't enable any PLL during this phase. Signed-off-by: Peter De Schrijver -- Stephen, Can you confirm this is ok for the audio drivers? We used to be lucky that this has worked up to now, but I

Re: [PATCH] clk: add table lookup to mux

On Wed, Mar 20, 2013 at 04:51:58PM +0100, Mike Turquette wrote: > Quoting Peter De Schrijver (2013-03-20 02:49:57) > > On Wed, Mar 20, 2013 at 12:51:10AM +0100, Mike Turquette wrote: > > > Quoting Peter De Schrijver (2013-03-12 11:42:23) > > > > diff --git a/include

Re: [PATCH] clk: add table lookup to mux

On Wed, Mar 20, 2013 at 12:51:10AM +0100, Mike Turquette wrote: > Quoting Peter De Schrijver (2013-03-12 11:42:23) > > diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h > > index 9c7f580..53d39c2 100644 > > --- a/include/linux/clk-private.h > &

Re: [PATCH] clk: add table lookup to mux

On Tue, Mar 19, 2013 at 10:33:09PM +0100, Mike Turquette wrote: > Quoting Peter De Schrijver (2013-03-12 11:42:23) > > Add a table lookup feature to the mux clock. Also allow arbitrary masks > > instead of the width. This will be used by some clocks on Tegra114. Also > > adapt

Re: [RFC 1/1] clk: Add notifier support in clk_prepare_enable/clk_disable_unprepare

On Fri, Mar 15, 2013 at 06:22:47AM +0100, Stephen Warren wrote: > On 03/14/2013 07:20 PM, Bill Huang wrote: > > On Fri, 2013-03-15 at 01:54 +0800, Stephen Warren wrote: > >> On 03/14/2013 03:28 AM, Bill Huang wrote: > >>> On Thu, 2013-03-14 at 17:21 +0800, Peter De

Re: [RFC 1/1] clk: Add notifier support in clk_prepare_enable/clk_disable_unprepare

On Thu, Mar 14, 2013 at 03:15:11AM +0100, Bill Huang wrote: > I don't think deferring will work either, considering the usage of DVFS, > device voltage is tightly coupled with frequency, when clock rate is > about to increase, we have to boost voltage first and we can lower the > voltage after the

[PATCH] clk: add table lookup to mux

Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver -- Mike, This is the same patch I posted before

Re: [REPOST PATCH 0/2] Table lookup for mux clock type

On Wed, Mar 06, 2013 at 12:52:02AM +0100, Stephen Warren wrote: > On 03/05/2013 03:48 PM, Stephen Warren wrote: > > On 02/22/2013 08:02 AM, Peter De Schrijver wrote: > >> This patchset adds a table lookup feature to the mux clock type. This will > >> be used by the

Re: [PATCH] arm: omap: RX-51: ARM errata 430973 workaround

On Thu, Feb 28, 2013 at 10:42:28AM +0100, Pali Rohár wrote: > Signed-off-by: Ivaylo Dimitrov > Signed-off-by: Pali Rohár > --- > arch/arm/mach-omap2/Makefile|1 + > arch/arm/mach-omap2/board-rx51-secure.c | 66 > +++ > arch/arm/mach-omap2/board-rx51

[REPOST PATCH 2/2] clk: tegra: adapt tegra periph clk to mux table/mask

The tegra peripheral clock type uses struct clk_mux directly, so it needs to be updated to handle the new mask and table fields. Also the macros need to be updated Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.h | 27 +++ 1 files changed, 19 insertions

[REPOST PATCH 1/2] clk: add table lookup to mux

Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Signed-off-by: Peter De Schrijver --- drivers/clk/clk-mux.c| 51 - include/linux/clk-private.h |3

[REPOST PATCH 0/2] Table lookup for mux clock type

patch adapts the tegra periph clock implementation which uses struct clk_mux directly. -- Mike, This patch is a dependency for the Tegra114 CCF implementation. Could you review it and merge on a topic branch so Stephen can pull it in to verify the integration? Thanks, Peter. Peter De Schrijver

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

On Thu, Feb 21, 2013 at 01:25:36PM +0100, Peter De Schrijver wrote: > On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote: > > ... > > > > I would suggest removing this clock. It's not actually implemented in the > > > CCF > > > and rat

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote: ... > > I would suggest removing this clock. It's not actually implemented in the > > CCF > > and rather useless. If you would gate the CPU clock from the CPU by writing > > to > > this register, how would you ungate it? :) Note th

Re: [PATCH] spi: tegra114: add spi driver

On Wed, Feb 20, 2013 at 06:25:13PM +0100, Stephen Warren wrote: > On 02/20/2013 06:26 AM, Laxman Dewangan wrote: > > On Wednesday 20 February 2013 06:41 PM, Mark Brown wrote: > >> * PGP Signed by an unknown key > >> > >> On Wed, Feb 20, 2013 at 05:59:03PM +0530, Laxman Dewangan wrote: > > +

Re: [PATCH v7 00/12] Tegra114 clockframework

On Fri, Feb 15, 2013 at 01:36:30PM +0100, Peter De Schrijver wrote: > This is the seventh version of the Tegra114 clockframework. It is based on the > for-next branch of > git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git and > http://www.spinics.net/lists/arm-kern

[PATCH v7 12/12] clk: tegra: Remove forced clk_enable of uartd

The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/

[PATCH v7 11/12] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114-dalmore.dts |1 - arch/arm

[PATCH v7 10/12] clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |1 + drivers/clk/tegra/clk.h |7 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index f6c141f..bc5a1f8 100644 --- a/drivers/clk/tegra/clk.c +++ b

[PATCH v7 08/12] ARM: tegra: Define Tegra114 CAR binding

The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra114-car.txt | 316 1 files changed, 316 insertions(+), 0 deletions(-) create mode 100644

[PATCH v7 07/12] clk: tegra: Workaround for Tegra114 MSENC problem

Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c |9 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c

[PATCH v7 06/12] clk: tegra: Add flags to tegra_clk_periph()

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph.c | 11 ++- drivers/clk/tegra/clk-tegra20.c |2 +- drivers/clk

[PATCH v7 05/12] clk: tegra: Add new fields and PLL types for Tegra114

Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 836 +++ drivers/clk/tegra/clk.h | 48 +++ 2 files changed, 884

[PATCH v7 04/12] clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 38 -- drivers/clk/tegra/clk-tegra20.c |

[PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 12 drivers/clk/tegra/clk.h |2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a

[PATCH v7 02/12] clk: tegra: Refactor PLL programming code

* Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver --- drivers/clk/tegra

[PATCH v7 01/12] clk: tegra: provide dummy cpu car ops

tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver

[PATCH v7 00/12] Tegra114 clockframework

n't appear in the internal TRM, so I assume they don't exist. * Rebase on top of Hiroshi's latest Tegra114 patches * More generic mux code. This is necessary for the AHUB and DAM clocks. Peter De Schrijver (12): clk: tegra: provide dummy cpu car ops clk: tegra: Re

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote: > On 02/14/2013 11:59 AM, Hiroshi Doyu wrote: > > To replace magic number in tegra_car: > > > > - clocks = <&tegra_car 28>; > > + clocks = <&tegra_car CLK_HOST1X>; > > > diff --git a/arch/arm/boot/dts/tegr

Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks

> There could be the same kind of requirement from others that both > "dtsip" and "C-source" want to share the same header file. If we > consider that DT is the exact H/W description, C-source should be able > to include a DT header file. > > For example, a C-header file for "enum tegra{20,30}_clk

[PATCH] clk: tegra: provide dummy cpu car ops

or should I make this part of new release of the Tegra114 clock series? Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index a603b9a..f6c141f 100644 --- a

Re: [PATCH 1/1] ARM: dt: add header to define tegra20 clocks

On Thu, Feb 14, 2013 at 07:38:17AM +0100, Hiroshi Doyu wrote: > To replace magic number in "clocks = <&tegra_car 28>;" > But then we should probably also remove the enum tegra20_clk and replace it with this header file. We should also consider removing the list of IDs from the documentation and r

Re: [PATCH v6 08/10] ARM: dt: Add references to tegra_car clocks

On Fri, Feb 08, 2013 at 03:03:02PM +0100, Felipe Balbi wrote: > * PGP Signed by an unknown key > > Hi, > > On Fri, Feb 08, 2013 at 03:36:40PM +0200, Peter De Schrijver wrote: > > tegra_car: clock { > > - compatible = "nvidia,

Re: [PATCH] clk: tegra: No 7.1 super clk dividers on Tegra20

On Fri, Feb 08, 2013 at 06:38:39PM +0100, Stephen Warren wrote: > On 02/08/2013 05:44 AM, Peter De Schrijver wrote: > > Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. > > Remove the clocks related to the divider. > > I assume there's no partic

[PATCH v6 10/10] clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |1 + drivers/clk/tegra/clk.h |7 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index a603b9a..a328365 100644 --- a/drivers/clk/tegra/clk.c +++ b

[PATCH v6 08/10] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114.dtsi |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 96a8235

[PATCH v6 06/10] clk: tegra: Workaround for Tegra114 MSENC problem

Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c |9 + drivers/clk/tegra/clk.h |2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c

[PATCH v6 07/10] ARM: tegra: Define Tegra114 CAR binding

The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra114-car.txt | 316 1 files changed, 316 insertions(+), 0 deletions(-) create mode 100644

[PATCH v6 05/10] clk: tegra: Add flags to tegra_clk_periph()

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph.c | 11 ++- drivers/clk/tegra/clk-tegra20.c |2 +- drivers/clk

[PATCH v6 04/10] clk: tegra: Add new fields and PLL types for Tegra114

Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 836 +++ drivers/clk/tegra/clk.h | 48 +++ 2 files changed, 884

[PATCH v6 03/10] clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 38 -- drivers/clk/tegra/clk-tegra20.c |

[PATCH v6 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 12 drivers/clk/tegra/clk.h |2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a

[PATCH v6 01/10] clk: tegra: Refactor PLL programming code

* Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver --- drivers/clk/tegra

[PATCH] clk: tegra: No 7.1 super clk dividers on Tegra20

Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 36 ++-- 1 files changed, 2 insertions(+), 34 deletions(-) diff --git a

Re: [PATCH] clk: tegra: Implement locking for super clock

On Thu, Feb 07, 2013 at 07:57:42PM +0100, Mike Turquette wrote: > Quoting Peter De Schrijver (2013-02-07 08:24:14) > > Although tegra_clk_register_super_mux() has a lock parameter, the lock is > > not > > actually used by the code. Fixed with this patch. > > > >

[PATCH] clk: tegra: Add missing spinlock for hclk and pclk

The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 11 +++ drivers/clk/tegra/clk-tegra30.c | 11 +++ 2 files changed, 14 insertions(+), 8

[PATCH] clk: tegra: local arrays should be static

cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within clk-tegra30.c. Declare them static to avoid namespace polution. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra30.c | 20 ++-- 1 files changed, 10 insertions(+), 10 deletions

[PATCH] clk: tegra: Implement locking for super clock

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not actually used by the code. Fixed with this patch. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-super.c | 18 +++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers

Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

> > > > + /* xusb_hs_src */ > > > + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); > > > + val |= BIT(25); /* always select PLLU_60M */ > > > + writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); > > > + > > > + clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

On Tue, Feb 05, 2013 at 02:23:55PM +0100, Peter De Schrijver wrote: > On Tue, Feb 05, 2013 at 06:42:11AM +0100, Prashant Gaikwad wrote: > > On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote: > > > On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote: &

Re: [PATCH] clk: tegra: initialise parent of uart clocks

On Wed, Feb 06, 2013 at 11:47:41AM +0100, Laxman Dewangan wrote: > Initialise the parent of UARTs to PLLP and disabling clock by > default. > I wonder if we should move the parent definitions to DT at some point. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

On Tue, Feb 05, 2013 at 06:42:11AM +0100, Prashant Gaikwad wrote: > On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote: > > On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote: > >> On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote: > > .

Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote: > On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote: ... > > + /* xusb_hs_src */ > > + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); > > + val |= BIT(25); /* a

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote: > On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote: ... > > > > -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll, > > -void __iomem *lock_addr, u32 lock

Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

On Mon, Feb 04, 2013 at 11:45:31AM +0100, Peter De Schrijver wrote: > On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote: ... > > > + > > > + /* dsia */ > > > + clk = clk_register_mux(NULL, "

[PATCH] clocksource: tegra: move to of_clk_get

The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver --- arch

Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote: ... > > +#define RST_DEVICES_L 0x004 > > +#define RST_DEVICES_H 0x008 > > +#define RST_DEVICES_U 0x00C > > +#define RST_DEVICES_V 0x358 > > +#define RST_DEVICES_W

Re: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114

On Mon, Feb 04, 2013 at 07:35:29AM +0100, Prashant Gaikwad wrote: > On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote: > > On 2/1/2013 5:18 AM, Peter De Schrijver wrote: > >> Tegra114 introduces new PLL types. This requires new clocktypes as well > >> as

[PATCH v5 10/10] clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk.c |1 + drivers/clk/tegra/clk.h |7 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index a603b9a..a328365 100644 --- a/drivers/clk/tegra/clk.c +++ b

[PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks

Add references to tegra_car clocks for the basic device nodes. Signed-off-by: Peter De Schrijver --- arch/arm/boot/dts/tegra114.dtsi |7 ++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 96a8235

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